CN101752361A - Array substrate for display device and method for fabricating the same - Google Patents

Array substrate for display device and method for fabricating the same Download PDF

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Publication number
CN101752361A
CN101752361A CN200910150955A CN200910150955A CN101752361A CN 101752361 A CN101752361 A CN 101752361A CN 200910150955 A CN200910150955 A CN 200910150955A CN 200910150955 A CN200910150955 A CN 200910150955A CN 101752361 A CN101752361 A CN 101752361A
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metal layer
barrier metal
drain electrode
electrode
photosensitive film
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文教浩
安炳龙
崔熙敬
金哲泰
洪星旭
郑胜宇
赵容秀
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LG Display Co Ltd
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LG Display Co Ltd
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
    • G02F1/136236—Active matrix addressed cells for reducing the number of lithographic steps using a grey or half tone lithographic process
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nonlinear Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Liquid Crystal (AREA)

Abstract

An array substrate for a display device and its fabrication method are disclosed. The array substrate for a display device includes: a gate wiring and a gate electrode connected to the wiring formed on a substrate; a gate insulating layer formed on the gate electrode; an active layer and a barrier metal layer stacked with the gate insulating layer interposed therebetween on the gate electrode; a data wiring formed on the barrier metal layer and source and electrodes connected to the data wiring; a passivation film formed on the source and drain electrodes and the data wiring and having a contact hole exposing a portion of the drain electrode, the barrier metal layer and the active layer; and a pixel electrode formed on the passivation film and being in contact with the drain electrode and the barrier metal layer including the active layer.

Description

The array base palte and the manufacture method thereof that are used for display device
Technical field
The present invention relates to a kind of array base palte that is used for display device, relate more specifically to a kind of array base palte and manufacture method thereof that is used for display device, it can reduce contact resistance between pixel electrode and the plain conductor by making pixel electrode and obstacle (barrier) Metal Contact.
Background technology
In general, plain conductor is used for to the element repeating signal.The plain conductor price that is used for repeating signal is lower, and has low-resistance value, and because metal has very strong corrosion resistance, it can contribute to the high reliability and the price competition of product.
In most of the cases, the quality of the array base palte of LCD (LCD) (i.e. first substrate) is determined according to the material or each circuit elements design specification that are used for each element.
For example, little for little LCD device relationships, but have under the situation of 18 inches or larger sized extensive High Resolution LCD equipment, the specific resistance value that is used for the material of select lines and data wire is a key factor of determining the superiority of image quality.
Therefore, on a large scale/situation of High Resolution LCD equipment under, that preferably uses aluminum or aluminum alloy for example has the material of low-resistance metal as select lines or data wire.
Fine aluminium has chemically more weak corrosion resistance, in high-temperature process subsequently, produce from the surface of select lines and grid hillock (hillock, H).Hillock (H) can bring out the supernormal growth of the gate insulation layer that covers select lines and grid, and can cause being used as switch element owing to the failure of insulation between active layer and the grid causes short circuit.
Thus, under the situation of aluminum conductor, use, or use stepped construction with alloy form.Yet,, disadvantageously should handle extraly when select lines is formed when stacked.
Recently, in the effort of avoiding this problem, copper (Cu) is used in suggestion, and it can form lead by simple process, and has low resistance and low price.
The array base palte of the use copper that is used for display device of correlation technique is described with reference to Fig. 1 and Fig. 2 below.
Fig. 1 is the schematic section of the array base palte that is used for display device of correlation technique.
Fig. 2 is the schematic section of the array base palte that is used for display device of correlation technique, shows the copper oxide film that forms on drain electrode and the surface that contacts with each other of pixel electrode.
With reference to Fig. 1, the array base palte that is used for display device of correlation technique comprises the select lines (not shown) that is formed in the direction extension in transparency carrier 11 upper edges, and vertically intersect to limit the data wire (not shown) of pixel region (not shown) with select lines, gate insulation layer 15 is clipped in therebetween.
At this, although not shown, at infall formation thin-film transistor (TFT) (not shown) of select lines (not shown) and data wire (not shown), i.e. switch element.Source electrode 21 that TFT comprises the grid 13 that extends from select lines, extend from data wire and the active layer 17 that forms raceway groove by the drain electrode 23 that separates specific range with source electrode 21.Source electrode 21 and drain electrode 23 are made by the copper with low resistance and low price (Cu).Active layer 17 is being formed on the gate insulation layer 15 above the grid 13, and is formed by pure amorphous silicon layer.
Molybdenum titanium (MoTi) layer 19 form source electrode 21 and drain 23 and active layer 17 between barrier metal layer.Molybdenum titanium (MoTi) layer 19 is used to prevent that the copper (Cu) that constitutes source electrode 21 and drain electrode 23 is in direct contact with one another to interact with active layer 17.
Be used to protect the passivation layer 25 of TFT, select lines and data wire to be formed on substrate 11.
Pixel electrode 29 is formed on the passivation layer 25 of pixel region, and electrically contacts via contact hole 27 that forms by etch passivation layer 25 and drain electrode 23.Pixel electrode 29 is made by the transparent metal material of for example ITO (or IZO).
Yet the array base palte that is used for display device of correlation technique has following problem.
That is to say, at the array base palte that is used for display device of correlation technique, as shown in Figure 2, when after in passivating film, forming contact hole, forming pixel electrode, because H 2The influence of O gas, with drain electrode that pixel electrode contacts on produce copper oxide film (Cu 2O), to such an extent as to make pixel electrode and the drain electrode between the contact performance deterioration.That is, the signal to the pixel electrode transmission transmits via source electrode and drain electrode data wire.
Be applied at identical voltage under the situation of select lines, determine by the resistance of raceway groove and the resistance of the contact portion between pixel electrode and the drain electrode to the electric current of pixel electrode input.
Therefore, although the contact resistance between copper conductor and the pixel electrode is very low, because the surface of copper conductor because process conditions are oxidized, causes contact resistance to increase.
Thereby, because the contact resistance between drain electrode, copper conductor and the pixel electrode increases, when applying low Vgs voltage, to compare with the situation of the different metal of application examples such as aluminium, the TFT charge characteristic is bad.
Thereby at the array base palte that is used for display device of correlation technique, the increase of the contact resistance between drain electrode, copper conductor and ITO, the pixel electrode causes signal delay.
Summary of the invention
The purpose of embodiments of the present invention provides a kind of array base palte and manufacture method thereof that is used for display device, and it contacts the electrology characteristic that can improve thin-film transistor (TFT) to reduce contact resistance thus by making pixel electrode with barrier metal layer.
According to an aspect of the present invention, provide a kind of array base palte that is used for display device, this array base palte comprises: be formed on select lines and the grid that is connected to described select lines on the substrate; Be formed on the gate insulation layer on the described grid; Be positioned at active layer that piles up and barrier metal layer on the described grid, wherein said gate insulation layer is clipped between described grid and the described active layer and barrier metal layer that piles up; The source electrode and the drain electrode that are formed on the data wire on the described barrier metal layer and are connected to described data wire; Passivating film, it is formed on described source electrode and drain electrode and the described data wire, and has the contact hole of a part of the barrier metal layer of a part of exposing described drain electrode and below; And pixel electrode, it is formed on the described passivating film, and contacts with the barrier metal layer of described drain electrode and below.
According to a further aspect in the invention, the method that provides a kind of manufacturing to be used for the array base palte of display device, this method may further comprise the steps: form select lines and the grid that is connected to described select lines on substrate; On described grid, form gate insulation layer; Form active layer on described grid, wherein said gate insulation layer is clipped between described grid and the described active layer; The source electrode and the drain electrode that on described active layer, form barrier metal layer, data wire and be connected to described data wire; On described source electrode and drain electrode and described data wire, form passivating film; Optionally the part of the part of the described passivating film of etching and described drain electrode is exposed the contact hole of a part of the barrier metal layer of the part of described drain electrode and below with formation; And on described passivating film, forming pixel electrode, this pixel electrode contacts with the barrier metal layer of described drain electrode and below.
The supplementary features of embodiments of the present invention and advantage will be described in the following description and will partly manifest from describe, and perhaps can understand by the practice of embodiments of the present invention.Can realize and obtain purpose and other advantages of embodiments of the present invention by the structure that particularly points out in written specification and claim and the accompanying drawing.
Should be appreciated that above-mentioned general description and following detailed description are exemplary and explanat, and aim to provide the further explanation of execution mode required for protection.
Description of drawings
Accompanying drawing is included in this specification providing further understanding of the present invention, and is attached in this specification and constitutes the part of this specification, and accompanying drawing shows embodiments of the present invention, and is used from specification one and explains principle of the present invention.
In the accompanying drawing:
Fig. 1 is the schematic section according to the array base palte that is used for display device of correlation technique;
Fig. 2 is the schematic section according to the array base palte that is used for display device of correlation technique, shows the copper oxide film that forms on the contact-making surface of drain electrode and pixel electrode;
Fig. 3 is the schematic section of the array base palte that is used for display device according to the embodiment of the present invention; And
Fig. 4 a is the sectional view that sequentially shows the manufacturing process of the array base palte that is used for display device according to the embodiment of the present invention to 4o.
Embodiment
Describe according to an illustrative embodiment of the invention array base palte that is used for display device and manufacture method thereof below with reference to accompanying drawings in detail.
Fig. 3 is the schematic section of the array base palte that is used for display device according to the embodiment of the present invention.
With reference to Fig. 3, the array base palte that is used for display device according to the embodiment of the present invention comprises the select lines (not shown) that is formed in the direction extension in transparency carrier 101 upper edges and vertically intersects to limit the data wire (not shown) of pixel region (not shown) with the select lines (not shown) that gate insulation layer 105 is clipped in therebetween.
At this, although not shown, thin-film transistor (TFT) (not shown) is formed on each infall of select lines (not shown) and data wire (not shown).The source electrode 111a that TFT comprises the grid 103 that extends from select lines, extend from data wire, separate the drain electrode 111b of specific range and the active layer 107 that forms raceway groove with source electrode 111a.Source electrode 111a and drain electrode 111b are made of copper promptly a kind of metal with low resistance and low price.
Active layer 107 is formed on the gate insulation layer 105 on the top of grid 103, and is formed by pure amorphous silicon layer.
The barrier metal layer of being made by molybdenum alloy 109 is formed between source electrode 111a, drain electrode 111b and the active layer 107.At this moment, barrier metal layer 109 is used to prevent that the copper (Cu) that constitutes source electrode 111a and drain electrode 111b from directly contacting to interact with active layer 107.The molybdenum alloy that constitutes barrier metal layer 109 can be select from the group of being made up of titanium (Ti), tantalum (Ta), chromium (Cr), nickel (Ni), indium (In) and aluminium (Al) a kind of.At this, the situation that titanium (Ti) is used as molybdenum alloy will be described.
Passivating film 115 is formed on the substrate 101 with protection TFT, select lines and data wire.
Pixel electrode 123a is formed on the passivating film 115 of pixel region, and together with drain electrode 111b, the contact hole (seeing 121 among Fig. 4 m) that forms via the part by etch passivation film 115 and drain electrode 111b electrically contacts with barrier metal layer 109.Pixel electrode 123a is by ITO (or IZO), and promptly a kind of transparent metal material is made.Copper oxide film 125 is formed on the drain electrode 111b that contacts with pixel electrode 123a, and not with the barrier metal layer 109 that contact of drain electrode 111b on formation.
Thus, in embodiments of the present invention, because copper oxide film 125 does not form between pixel electrode 123a and the barrier metal layer 109 made by MoTi, so can reduce high resistance composition under the low-voltage.
In addition, in the present invention,, the TFT charge characteristic under low Vds voltage can be improved, linear mobility can also be improved greatly to influence the characteristic of model product by using the ohmic contact characteristic of barrier metal layer 109 and pixel electrode 123a.
The manufacture method of the array base palte that is used for display device is according to the embodiment of the present invention described to 4o with reference to Fig. 4 a below.
Fig. 4 a is the sectional view that sequentially shows the manufacturing process of the array base palte that is used for display device according to the embodiment of the present invention to 4o.
Shown in Fig. 4 a, a kind of being deposited on the transparency carrier 101 that to from the conducting metal group of forming by aluminium (Al), aluminium alloy (AlNd), chromium (Cr), tungsten (W), molybdenum (Mo) and copper (Cu), select, and to its composition to form many select lines (not shown) in one direction and to be formed from the outstanding a plurality of grids 103 of select lines.
From by silicon oxide film (SiO 2), select in the inorganic insulating material group formed of silicon nitride film (SiNx) a kind of, or according to circumstances from the organic insulating material group of forming by benzocyclobutene and acrylic based resin, select a kind ofly be deposited or apply to form gate insulation layer 105.
Subsequently, on gate insulation layer 105, form the active layer 107 that forms by amorphous silicon (a-Si:H) as channel region.
Then, although not shown, apply first photosensitive film on active layer 107, exposing by the photoetching process of utilizing exposed mask is limited with the first photosensitive film pattern (not shown) in source region with formation with etching work procedure.
Subsequently, shown in Fig. 4 b, by use the first photosensitive film pattern as mask optionally to active layer 107 compositions and remove the first photosensitive film pattern.
Afterwards, shown in Fig. 4 c,, on the whole surface of comprising of substrate 101 of patterned active layer 107, deposit molybdenum alloy, to form barrier metal layer 109 by sputtering method.At this moment, barrier metal layer 109 is used for preventing constituting the interaction that will directly contact with each other and cause owing to them between the copper (Cu) of source electrode that subsequent handling forms and drain electrode and active layer 107.For molybdenum alloy, can from the group of forming by titanium (Ti), tantalum (Ta), chromium (Cr), nickel (Ni), indium (In) and aluminium (Al), select a kind of.In the present invention, the situation of titanium (Ti) as molybdenum alloy of utilizing will be described.
Subsequently, by sputtering at deposited copper on the barrier metal layer 109 (Cu) forming copper metal layer 111, and on copper metal layer 111 coating second photosensitive film 113.
Then, shown in Fig. 4 d, by utilizing the photo-mask process exposure and etching second photosensitive film 113 of diffracting mask (or slit mask) (not shown), to form the second photosensitive film pattern 113a.In the case, use half-tone mask, in addition, also can use slit mask as diffracting mask.
The second photosensitive film pattern 113a comprises light blocking district and halftoning district.Corresponding to the thickness of the pattern part in halftoning district than thin corresponding to the pattern part in light blocking district.This be because: although not shown, the chromium film figure is formed on the position corresponding with the light blocking district of half-tone mask (not shown), and the semi-transparent film pattern is formed on the position corresponding with the halftoning district of half-tone mask.In addition, the halftoning district of the second photosensitive film pattern 113a is corresponding to channel region, and the light blocking district of the second photosensitive film pattern 113a is corresponding to source region and drain region.
Afterwards, shown in Fig. 4 e, by utilizing the second photosensitive film pattern 113a as mask, optionally the etch copper metal level 111.At this moment, when etch copper metal level 111, barrier metal layer 109 is also etched.
Then, shown in Fig. 4 f, by the ashing operation etching second photosensitive film pattern 113a optionally, to expose the upper surface corresponding copper metal layer 111 with position channel region.
Subsequently, shown in Fig. 4 g, utilization is by the second photosensitive film pattern 113a of the ashing copper metal layer 111 that exposes of etching optionally, intersects with the data wire (not shown) that limits pixel region to form vertically with the select lines (not shown), is formed the source electrode 111a that gives prominence in a side direction of grid 103 from data wire and separates the drain electrode 111b of specific range with source electrode 111a.At this moment, when copper metal layer 111 is etched, also barrier metal layer 109 is etched with the channel region that exposes active layer 107.
Then, shown in Fig. 4 h, after removing the second photosensitive film pattern 113a, that selects from the organic insulating material group is a kind of, or a kind of being deposited of according to circumstances selecting from the inorganic insulating material group to form passivating film 115, then, applies the 3rd photosensitive film 117.At this moment, as the material that is used to form passivating film 115, as mentioned above, from by silicon oxide film (SiO 2), select in the inorganic insulating material group formed of silicon nitride film (SiNx) a kind of, or according to circumstances from the organic insulating material group of forming by benzocyclobutene and acrylic based resin, select a kind ofly be deposited or apply.
Subsequently, shown in Fig. 4 i, photoetching process exposure by using half-tone mask 130 and etching the 3rd photosensitive film 117 are to form the 3rd photosensitive film pattern 117a.At this moment, except half-tone mask, also can use slit mask.
The 3rd photosensitive film pattern 117a comprises light blocking district and halftoning district.Corresponding to the thickness of the pattern part in halftoning district than thin corresponding to the pattern part in light blocking district.This is because semi-transparent film pattern 130a is formed on the position corresponding with the halftoning district of half-tone mask 130, and chromium film figure 130b is formed on the position corresponding with the light blocking district of half-tone mask 130.And the halftoning district of the 3rd photosensitive film pattern 117a forms the zone corresponding to the drain contact hole, and the halftoning district of the 3rd photosensitive film pattern 117a is open fully to expose the part of passivating film 115.
Then, shown in Fig. 4 j and 4k, by using the 3rd photosensitive film pattern 117a as mask etch passivation film 115 optionally, then, optionally the part of the drain electrode 111b below the etch passivation film 115 is to form first contact hole 119.At this moment, passivating film 115 experience are done carved (dryetching) operation, then make the wet operation of carving of drain electrode 111b experience.When forming first contact hole 119, the part that is positioned at below the drain electrode 111b of barrier metal layer 109 is exposed.
In different execution modes of the present invention, although not shown, in forming the process of first contact hole 119, when etching drain electrode 111b, but also the part of etching barrier metal layer 109 to expose its side.
Subsequently, shown in Fig. 4 l, carry out the ashing operation, be removed until the part corresponding with the halftoning district of the 3rd photosensitive film pattern 117a with etching the 3rd photosensitive film pattern 117a.
Then, shown in Fig. 4 m, by using the 3rd photosensitive film pattern 113a as mask, optionally etch passivation film 115 exposes second contact hole 121 of the upper surface of the 111b that drains with formation.At this moment, second contact hole 121 comprises first contact hole 119, and has the diameter bigger than first contact hole 119.
Afterwards, shown in Fig. 4 n, by sputter, deposition is based on the transparent material of ITO, to form transparent metal layer 123 on second contact hole 121 that comprises first contact hole 119 and passivating film 115.At this moment, can from AZO, ZnO, IZO or other transparent metal material, select based on the transparent material of ITO.
Although not shown, coating the 4th photosensitive film (not shown) on transparent metal layer 123, and by photo-mask process with its exposure be etched with and form the 4th photosensitive film pattern (not shown).
Then, shown in Fig. 4 o, by using the 4th photosensitive film pattern (not shown) as mask etching transparent metal layer 123 optionally, forming, and remove remaining the 4th photosensitive film pattern (not shown) to finish the manufacturing of the array base palte that is used for display device thus via first and second contact holes 119 and the 121 pixel electrode 123a that are electrically connected with the barrier metal layer 109 and the 111b that drains.At this moment, generation copper oxide film 125 on drain electrode 111b and interface that pixel electrode 123a contacts.Simultaneously, on barrier metal layer 109 and interface that pixel electrode 123a contacts, do not produce copper oxide film 125.
As mentioned above, the molybdenum alloy (that is molybdenum titanium (MoTi)) of formation barrier metal layer 109 contacts with the ITO that constitutes pixel electrode 123a.
As so far described, the array base palte and the manufacture method thereof that are used for display device have the following advantages.
That is to say,, thereby can reduce the contact resistance between drain electrode and the pixel electrode because molybdenum titanium (MoTi), copper obstacle metal and pixel electrode directly contact with each other reducing the contact resistance between drain electrode (that is, copper conductor) and the pixel electrode.
Thereby, by utilizing the ohmic contact characteristic of barrier metal layer and pixel electrode, can improve the TFT charge characteristic under the low Vds voltage.In addition, can improve linear mobility, thereby the product performance of the model of using the response time is produced a very large impact.
Because the present invention can realize and not break away from its spirit or substantive characteristics by various ways, be to be understood that above-mentioned execution mode is not subject to any details of foregoing description, unless otherwise prescribed, and should in the spirit and scope that claims limit, broadly understand, and therefore fall into the whole variations in the equivalent in the border of claim and the scope or that fall into described border and scope and revise and comprise by claims.

Claims (11)

1. array base palte that is used for display device, this array base palte comprises:
Be formed on select lines and the grid that is connected to described select lines on the substrate;
Be formed on the gate insulation layer on the described grid;
Be positioned at active layer that piles up and barrier metal layer on the described grid, wherein said gate insulation layer is clipped between described grid and the described active layer and barrier metal layer that piles up;
The source electrode and the drain electrode that are formed on the data wire on the described barrier metal layer and are connected to described data wire;
Passivating film, it is formed on described source electrode and drain electrode and the described data wire, and has the contact hole of a part of the barrier metal layer of a part of exposing described drain electrode and below; And
Pixel electrode, it is formed on the described passivating film, and contacts with the barrier metal layer of described drain electrode and below.
2. array base palte according to claim 1, wherein said barrier metal layer is made by molybdenum alloy, and this molybdenum alloy uses select a kind of from the group of being made of titanium (Ti), tantalum (Ta), chromium (Cr), nickel (Ni), indium (In) and aluminium (Al).
3. array base palte according to claim 1, wherein said pixel electrode is made by the transparent material based on ITO, and described transparent material based on ITO uses select a kind of from the group of being made of AZO, ZnO and IZO.
4. array base palte according to claim 1, wherein said pixel electrode contacts with the upper surface of described barrier metal layer.
5. a manufacturing is used for the method for the array base palte of display device, and this method may further comprise the steps:
On substrate, form select lines and the grid that is connected to described select lines;
On described grid, form gate insulation layer;
Form active layer on described grid, wherein said gate insulation layer is clipped between described grid and the described active layer;
The source electrode and the drain electrode that on described active layer, form barrier metal layer, data wire and be connected to described data wire;
On described source electrode and drain electrode and described data wire, form passivating film;
Optionally the part of the part of the described passivating film of etching and described drain electrode is exposed the contact hole of a part of the barrier metal layer of the part of described drain electrode and below with formation; And
Form pixel electrode on described passivating film, this pixel electrode contacts with the barrier metal layer of described drain electrode and below.
6. method according to claim 5, wherein said barrier metal layer is made by molybdenum alloy, and this molybdenum alloy uses select a kind of from the group of being made of titanium (Ti), tantalum (Ta), chromium (Cr), nickel (Ni), indium (In) and aluminium (Al).
7. method according to claim 5, wherein said pixel electrode is made by the transparent material based on ITO, and described transparent material based on ITO uses select a kind of from the group of being made of AZO, ZnO and IZO.
8. method according to claim 5, wherein said pixel electrode contacts with the upper surface of described barrier metal layer.
9. method according to claim 5, wherein optionally the part of the part of the described passivating film of etching and the described drain electrode step of contact hole of a part of exposing the barrier metal layer of the part of described drain electrode and below with formation is undertaken by the photo-mask process that uses diffracting mask.
10. method according to claim 9, wherein said diffracting mask comprises half-tone mask and slit mask.
11. method according to claim 10 wherein may further comprise the steps by the step of using described half-tone mask to form described contact hole:
The photosensitive film on the formed described passivating film carries out composition on described source electrode and drain electrode and the described data wire to being coated in for exposure by using half-tone mask and etching work procedure, to form the photosensitive film pattern, the regional corresponding photosensitive film part with corresponding to the part of described drain electrode of described photosensitive film pattern is removed fully, and described photosensitive film is removed at the segment thickness corresponding to the zone in described halftoning district;
By using described photosensitive film pattern sequentially to remove the part of the drain electrode of the part of described passivating film and below, expose first contact hole of the upper surface of described barrier metal layer with formation as mask;
Described photosensitive film pattern is carried out the described photosensitive film of ashing until the zone corresponding with described halftoning district partly to be removed; And
Come the described passivating film of etching by the photosensitive film pattern that uses ashing as mask, expose the upper surface of described drain electrode and comprise second contact hole of described first contact hole with formation.
CN200910150955A 2008-12-18 2009-06-29 Array substrate for display device and method for fabricating the same Withdrawn CN101752361A (en)

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