CN100570864C - Dot structure and preparation method thereof - Google Patents
Dot structure and preparation method thereof Download PDFInfo
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- CN100570864C CN100570864C CNB200610162703XA CN200610162703A CN100570864C CN 100570864 C CN100570864 C CN 100570864C CN B200610162703X A CNB200610162703X A CN B200610162703XA CN 200610162703 A CN200610162703 A CN 200610162703A CN 100570864 C CN100570864 C CN 100570864C
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Abstract
The invention discloses a kind of one pixel structure process method, the method at first forms a patterning first conductive layer on substrate, it comprise a grid and with the one scan distribution of its electric connection; Afterwards, on substrate, form a gate insulation layer; On the gate insulation layer of grid top, form a channel layer and an ohmic contact layer; Then, on substrate, form a protective layer, and in protective layer, form source electrode contact hole and drain contact hole, to expose ohmic contact layer; At last; on protective layer, form a patterned transparent conductive layer; it comprises one source pole and a drain electrode, a data wiring and a pixel electrode; source electrode sees through source electrode contact hole and drain contact hole and ohmic contact layer respectively with drain electrode and electrically connects; and source electrode and data wiring electrically connect, and drain electrode and pixel electrode electric connection.
Description
Technical field
The present invention is particularly to dot structure of a kind of use four road photomask (four-photomask) processing procedures and preparation method thereof relevant for a kind of dot structure and preparation method thereof.
Background technology
Thin Film Transistor-LCD (thin film transistor liquid crystal display, TFT-LCD) mainly constituted by thin-film transistor array base-plate, colorful filter array substrate and liquid crystal layer, wherein thin-film transistor array base-plate is the thin-film transistor of being arranged with the array pattern by a plurality of, and a pixel electrode (pixel electrode) of corresponding configuration with each thin-film transistor is formed.And above-mentioned thin-film transistor comprises grid, channel layer, drain electrode and source electrode, and thin-film transistor and pixel electrode constitute a dot structure.Wherein, thin-film transistor is used as the switch element of liquid crystal display.
In the existing thin-film transistor processing procedure, five road photomask processing procedures more commonly.Wherein, the first road photomask processing procedure is to be used for defining first conductive layer, to form the members such as grid of scan wiring and thin-film transistor.The second road photomask processing procedure is channel layer and the ohmic contact layer that defines thin-film transistor.The 3rd road photomask processing procedure is to be used for defining second conductive layer, with members such as the source electrode that forms data wiring and thin-film transistor and drain electrodes.The 4th road photomask processing procedure is to be used for the protective layer patterning.And the 5th road photomask processing procedure is to be used for the transparency conducting layer patterning, and forms pixel electrode.
Yet along with the development trend that Thin Film Transistor-LCD is made towards large scale, the making of thin-film transistor array base-plate will face many problems and challenge, and for example yield reduces and production capacity descends or the like.If therefore can reduce the photomask number of thin-film transistor processing procedure, promptly reduce the exposure manufacture process number of times that thin-film transistor element is made, promptly can reduce manufacturing time, increase production capacity, and then reduce manufacturing cost and can improve the making yield.
Summary of the invention
A purpose of the present invention provides a kind of production method of pixel structure, with employed number of optical mask in the reduction dot structure processing procedure, and then reduces its cost of manufacture.
Another object of the present invention provides a kind of dot structure, and this dot structure is to form a data wiring auxiliary patterns in the conductive layer of data wiring below, and makes it in parallel with data wiring, to reduce the resistance value of data wiring.Similarly, this dot structure also can dispose a scan wiring auxiliary patterns in parallel with it in the scan wiring top, to reach the purpose of the resistance value that reduces scan wiring.
For reaching above-mentioned or other purposes, the present invention proposes a kind of production method of pixel structure, and it comprises the following step.At first, form a patterning first conductive layer on a substrate, this patterning first conductive layer comprises a grid and one scan distribution.Wherein, this grid and scan wiring electrically connect.Afterwards, on substrate, form a gate insulation layer, a channel material layer, an ohmic contact material layer and a photoresist layer in regular turn.Then, utilize a GTG photomask that above-mentioned photoresist layer is exposed and developing manufacture process, and be that mask carries out a back of the body channel-etch processing procedure to channel material layer and ohmic contact material layer with the patterned light blockage layer, to define a channel layer and an ohmic contact layer in the grid top.Come again, on substrate, form a protective layer, and in protective layer, form an one source pole contact hole and a drain contact hole, to expose above-mentioned ohmic contact layer.At last, form a patterned transparent conductive layer on protective layer, this patterned transparent conductive layer comprises one source pole and a drain electrode, a data wiring and a pixel electrode.Wherein, source electrode and drain electrode see through source electrode contact hole and drain contact hole and ohmic contact layer respectively and electrically connect, and source electrode and data wiring electrically connect, and drain electrode and pixel electrode electric connection.
In one embodiment of this invention, patterning first conductive layer comprises a metal material.
In one embodiment of this invention, patterning first conductive layer also comprises a shared distribution, and this shared distribution is the bottom electrode as a pixel storage capacitor, and the follow-up pixel electrode that is formed at shared distribution top is promptly as the top electrode of pixel storage capacitor.Further, shared distribution can be the H type.
In one embodiment of this invention, when forming source electrode contact hole and drain contact hole in protective layer, also be included in and form at least one contact hole in the protective layer, this contact hole is the below that is positioned at the data wiring of follow-up formation.
In one embodiment of this invention, patterning first conductive layer also comprises at least one data wiring auxiliary patterns, and it is in parallel with data wiring that this data wiring auxiliary patterns sees through above-mentioned contact hole.
In one embodiment of this invention, when forming source electrode contact hole and drain contact hole in protective layer, also be included in and form at least one contact hole in the protective layer, this contact hole is the top that is positioned at scan wiring.
In one embodiment of this invention, patterned transparent conductive layer also comprises at least one scan wiring auxiliary patterns, and this scan wiring auxiliary patterns is in parallel with scan wiring through above-mentioned contact hole.
In one embodiment of this invention, the GTG photomask comprises a halftoning photomask.
In one embodiment of this invention, patterned transparent conductive layer comprises a transparent conductive material.Further, this transparent conductive material comprises indium tin oxide or indium-zinc oxide.
For reaching above-mentioned or other purposes, the present invention proposes a kind of dot structure in addition, and it comprises a substrate, a patterning first conductive layer, a gate insulation layer, a channel layer, an ohmic contact layer, a protective layer and a patterned transparent conductive layer.This patterning first conductive layer is to be disposed on the substrate, and it comprises that a grid reaches and the one scan distribution of its electric connection.Gate insulation layer is to be disposed on the substrate, and covers above-mentioned patterning first conductive layer.Channel layer is to be disposed on the gate insulation layer of grid top.Ohmic contact layer is to be disposed on the channel layer.Protective layer is to be disposed on the gate insulation layer, and it has an one source pole contact hole and a drain contact hole, to expose ohmic contact layer.Patterned transparent conductive layer is to be disposed on the protective layer, and it comprises one source pole and a drain electrode, a data wiring and a pixel electrode.Wherein, source electrode sees through the source electrode contact hole respectively with drain electrode and drain contact hole electrically connects with ohmic contact layer, and source electrode electrically connects with data wiring, and the pixel electrode and the electric connection that drains.
In one embodiment of this invention, patterning first conductive layer also comprises a shared distribution.This shared distribution is the bottom electrode as a pixel storage capacitor, and the follow-up pixel electrode that is formed at shared distribution top is promptly as the top electrode of pixel storage capacitor.Further, shared distribution can be the H type.
In one embodiment of this invention, protective layer also has at least one contact hole, and this contact hole is the below that is positioned at data wiring.
In one embodiment of this invention, patterning first conductive layer also comprises at least one data wiring auxiliary patterns, and it is in parallel with data wiring that this data wiring auxiliary patterns sees through above-mentioned contact hole.
In one embodiment of this invention, also have at least one contact hole in the protective layer, this contact hole is the top that is positioned at scan wiring.
In one embodiment of this invention, patterned transparent conductive layer also comprises at least one scan wiring auxiliary patterns, and it is in parallel with scan wiring that this scan wiring auxiliary patterns sees through above-mentioned contact hole.
In one embodiment of this invention, patterned transparent conductive layer is made up of a transparent conductive material.Further, transparent conductive material comprises indium tin oxide or indium-zinc oxide.
In sum, in disclosed production method of pixel structure, be in transparency conducting layer (transparency conducting layer), to define source electrode, drain electrode, data wiring and pixel electrode simultaneously, so, do not need as utilizing second metal level in the processing procedure of traditional dot structure to form source electrode and drain electrode, to reduce its cost of manufacture effectively.
In addition, because the present invention disposes a data wiring auxiliary patterns in parallel with it below data wiring, reduce the resistance value of data wiring with configuration by the data wiring auxiliary patterns.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. is described in detail below.
Description of drawings
Figure 1A～1D is according to looking schematic diagram on the wherein production method of pixel structure of a kind of thin-film transistor array base-plate of a preferred embodiment of the present invention.
Fig. 2 A～2D is respectively the generalized section that I-I ' hatching is painted in Figure 1A～1D.
Embodiment
Figure 1A～1D is according to looking schematic diagram on the wherein production method of pixel structure of a kind of thin-film transistor array base-plate of a preferred embodiment of the present invention; Fig. 2 A～2D is respectively the generalized section that I-I ' hatching is painted in Figure 1A～1D.At first, please also refer to Figure 1A and 2A, on a substrate 110, form a first metal layer (Metal 1) (not shown), and carry out the first road photomask processing procedure, to form a patterning first conductive layer 120, this patterning first conductive layer 120 mainly comprises a grid 121 and coupled one scan distribution 122.Except above-mentioned grid 121 and scan wiring 122, patterning first conductive layer 120 also can comprise a shared distribution 123 and at least one data wiring auxiliary patterns 124.This shared distribution 123 is the bottom electrodes as a pixel storage capacitor; In this embodiment, shared distribution 123 is to be the H type, yet the present invention does not impose any restrictions for the kenel of shared distribution 123.In addition, data wiring auxiliary patterns 124 is the belows that are formed at the data wiring of follow-up formation, reduces the resistance value of data wiring with the configuration by data wiring auxiliary patterns 124.Moreover, be to be electrically insulated each other between data wiring auxiliary patterns 124, shared distribution 123 and scan wiring 122 threes.In a preferred embodiment, patterning first conductive layer 120 comprises a metal material, for example chromium (Cr), tungsten (W), tantalum (Ta), titanium (Ti), molybdenum (Mo), aluminium (Al) or its alloy.
Next, please also refer to Figure 1B and 2B, on substrate 110, form a gate insulation layer 130 in regular turn, to cover above-mentioned patterning first conductive layer 120.In a preferred embodiment, the material of gate insulation layer 130 can be silicon nitride, silica, silicon oxynitride or other insulating material.Afterwards, on gate insulation layer 130, form a channel material layer (not shown), an ohmic contact material layer (not shown) and a photoresist layer (not shown) in regular turn, and utilize a GTG photomask (not shown) that photoresist layer is carried out the second road photomask processing procedure, to form a patterned light blockage layer, afterwards, with the patterned light blockage layer is that mask carries out a back of the body channel-etch (Back Channel Etching to channel material layer and ohmic contact material layer, BCE) processing procedure is to define a channel layer 142 and an ohmic contact layer 144 in grid 121 tops.The material of this channel layer 142 can be amorphous silicon (amorphoussilicon), and the material of ohmic contact layer 144 can be the n+ doped amorphous silicon.In addition, employed GTG photomask can be a halftoning photomask (Half tone mask) in the second road photomask processing procedure.
Afterwards, please also refer to Fig. 1 C and 2C, on substrate 110, form a protective layer 150, and carry out the 3rd road photomask processing procedure, in protective layer 150, to form one source pole contact hole 152, a drain contact hole 154 and at least one contact hole 156.Wherein, source electrode contact hole 152 and drain contact hole 154 are to expose above-mentioned ohmic contact layer 144, and this contact hole 156 is to expose data wiring auxiliary patterns 124 partly.In this embodiment, the material of protective layer 150 can be silica, silicon nitride, silicon oxynitride or organic material.
At last; on protective layer 150, form a transparency conducting layer (not shown); and carry out the 4th road photomask processing procedure, to form a patterned transparent conductive layer 160, this patterned transparent conductive layer 160 comprises one source pole 161 and drain electrode 162, one data wiring 163 and a pixel electrode 164.This patterned transparent conductive layer 160 comprises transparent conductive material, for example indium tin oxide, indium-zinc oxide or other suitable transparent conductive materials.Wherein, source electrode 161 sees through source electrode contact hole 152 respectively with drain electrode 162 and drain contact hole 154 electrically connects with ohmic contact layer 144, and source electrode 161 can and data wiring 163 electrically connect, and drain and 162 electrically connect with pixel electrode 164.In addition; the contact hole 156 that data wiring 163 can see through in the protective layer 150 electrically connects with data wiring auxiliary patterns 124; so, the data wiring 163 with high impedance can form structure in parallel with data wiring auxiliary patterns 124, to help the resistance value with low data wiring 163.So, promptly finish the making flow process of a dot structure.
In addition; previous formed shared distribution 123 is the bottom electrodes as pixel storage capacitor; and the pixel electrode 164 that is formed at shared distribution 123 tops is the top electrodes as pixel storage capacitor, and the gate insulation layer 130 that is formed between shared distribution 123 and the pixel electrode 164 promptly uses as capacitance dielectric layer with protective layer 150.
In the above-described embodiments, be below data wiring, to dispose a data wiring auxiliary patterns in parallel with it, reduce the resistance value of data wiring with configuration by the data wiring auxiliary patterns.Similarly; the user also can form one scan distribution auxiliary patterns in the transparency conducting layer of scan wiring top; and in protective layer, form corresponding contact hole; the contact hole that scan wiring can be seen through in the protective layer is in parallel with the scan wiring auxiliary patterns; can reach the purpose of the resistance value that reduces scan wiring so, equally.
In sum, in disclosed one pixel structure process method, only need use four road photomask processing procedures, can form required dot structure.Wherein, first photomask is to be used for defining first conductive layer of being made up of metal material, to form grid, scan wiring, shared distribution and data wiring auxiliary patterns.The second road photomask processing procedure is in order to definition channel layer and ohmic contact layer.The 3rd road photomask processing procedure is the contact hole that is used for defining in the protective layer, exposes the source electrode contact hole and the drain contact hole of ohmic contact layer and the contact hole that exposes the data wiring auxiliary patterns with formation.And the 4th road photomask is the transparency conducting layer of being made up of transparent conductive material in order to definition, to form source electrode and drain electrode, data wiring and pixel electrode.So, do not need as utilizing second metal level in the processing procedure of traditional dot structure to form source electrode and drain electrode, to reduce its cost of manufacture effectively.
In addition, because the present invention disposes a data wiring auxiliary patterns in parallel with it below data wiring, reduce the resistance value of data wiring with configuration by the data wiring auxiliary patterns.Similarly, the present invention also can form a scan wiring auxiliary patterns in parallel with it in the scan wiring top, reduce the resistance value of scan wiring with the configuration by the scan wiring auxiliary patterns.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those of ordinary skills, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when with being as the criterion that claim was defined.
Claims (17)
1. production method of pixel structure comprises:
Carry out the first road photomask processing procedure, to form a patterning first conductive layer on a substrate, this patterning first conductive layer comprises a grid and one scan distribution, and wherein this grid and this scan wiring electrically connect;
Form a gate insulation layer, a channel material layer, an ohmic contact material layer and a photoresist layer in regular turn on this substrate, wherein this gate insulation layer covers this patterning first conductive layer;
Carry out the second road photomask processing procedure: utilize this photoresist layer of a photomask patternization, and to be mask with this patterned light blockage layer carry out a back of the body channel-etch processing procedure to this channel material layer and this ohmic contact material layer, to define a channel layer and an ohmic contact layer in this grid top;
Form a protective layer on this substrate, and carry out the 3rd road photomask processing procedure, to form an one source pole contact hole and a drain contact hole, to expose this ohmic contact layer in this protective layer; And
Carry out the 4th road photomask processing procedure; on this protective layer, to form a patterned transparent conductive layer; this patterned transparent conductive layer comprises one source pole and a drain electrode, a data wiring and a pixel electrode; wherein this source electrode and this drain electrode see through the electric connection of this source electrode contact hole and this drain contact hole and this ohmic contact layer respectively; this source electrode and this data wiring electrically connect, and should drain electrode electrically connect with this pixel electrode.
2. production method of pixel structure as claimed in claim 1 is characterized in that, the material of this patterning first conductive layer comprises a metal material.
3. production method of pixel structure as claimed in claim 1 is characterized in that, this patterning first conductive layer also comprises the shared distribution of a H type.
4. production method of pixel structure as claimed in claim 1 is characterized in that, the step of this photoresist layer of patterning is to utilize a GTG photomask that this photoresist layer is exposed and developing manufacture process, to form this photoresist layer of patterning.
5. production method of pixel structure as claimed in claim 1 is characterized in that, also comprises forming at least one contact hole simultaneously in this protective layer, and this contact hole is the below that is positioned at this data wiring.
6. production method of pixel structure as claimed in claim 5 is characterized in that, this patterning first conductive layer also comprises at least one data wiring auxiliary patterns, and it is in parallel with this data wiring that this data wiring auxiliary patterns sees through this contact hole.
7. production method of pixel structure as claimed in claim 1 is characterized in that, also comprises forming at least one contact hole simultaneously in this protective layer, and this contact hole is the top that is positioned at this scan wiring.
8. production method of pixel structure as claimed in claim 7 is characterized in that, this patterned transparent conductive layer also comprises at least one scan wiring auxiliary patterns, and it is in parallel with this scan wiring that this scan wiring auxiliary patterns sees through this contact hole.
9. production method of pixel structure as claimed in claim 4 is characterized in that, this GTG photomask comprises a halftoning photomask.
10. production method of pixel structure as claimed in claim 1 is characterized in that the material of this patterned transparent conductive layer comprises indium tin oxide or indium-zinc oxide.
11. a dot structure comprises:
One substrate;
One patterning, first conductive layer is disposed on this substrate, and this patterning first conductive layer comprises a grid and one scan distribution, and wherein this grid and this scan wiring electrically connect;
One gate insulation layer is disposed on this substrate, and covers this patterning first conductive layer;
One channel layer is disposed on this gate insulation layer of this grid top;
One ohmic contact layer is disposed on this channel layer;
One protective layer is disposed on this gate insulation layer, and this protective layer has an one source pole contact hole and a drain contact hole, to expose this ohmic contact layer; And
One patterned transparent conductive layer; be disposed on this protective layer; this patterned transparent conductive layer comprises one source pole and a drain electrode, a data wiring and a pixel electrode; wherein this source electrode and this drain electrode see through the electric connection of this source electrode contact hole and this drain contact hole and this ohmic contact layer respectively; and this source electrode and this data wiring electrically connect, and this pixel electrode and this drain electrode electric connection.
12. dot structure as claimed in claim 11 is characterized in that, this patterning first conductive layer also comprises the shared distribution of a H type.
13. dot structure as claimed in claim 11 is characterized in that, this protective layer also has at least one contact hole, and this contact hole is the below that is positioned at this data wiring.
14. dot structure as claimed in claim 13 is characterized in that, this patterning first conductive layer also comprises at least one data wiring auxiliary patterns, and it is in parallel with this data wiring that this data wiring auxiliary patterns sees through this contact hole.
15. dot structure as claimed in claim 11 is characterized in that, also has at least one contact hole in this protective layer, this contact hole is the top that is positioned at this scan wiring.
16. dot structure as claimed in claim 15 is characterized in that, this patterned transparent conductive layer also comprises at least one scan wiring auxiliary patterns, and it is in parallel with this scan wiring that this scan wiring auxiliary patterns sees through this contact hole.
17. dot structure as claimed in claim 11 is characterized in that, the material of this patterned transparent conductive layer comprises indium tin oxide or indium-zinc oxide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200610162703XA CN100570864C (en) | 2006-11-23 | 2006-11-23 | Dot structure and preparation method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200610162703XA CN100570864C (en) | 2006-11-23 | 2006-11-23 | Dot structure and preparation method thereof |
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| CN101192578A CN101192578A (en) | 2008-06-04 |
| CN100570864C true CN100570864C (en) | 2009-12-16 |
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| CNB200610162703XA Expired - Fee Related CN100570864C (en) | 2006-11-23 | 2006-11-23 | Dot structure and preparation method thereof |
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| CN102938394B (en) | 2012-11-16 | 2015-01-07 | 京东方科技集团股份有限公司 | Display device, transflective type thin film transistor array substrate and manufacture method thereof |
| CN106057828A (en) * | 2016-08-12 | 2016-10-26 | 京东方科技集团股份有限公司 | Substrate, preparation method therefor, and display panel |
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