CN100570863C - Dot structure and manufacture method thereof - Google Patents
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- CN100570863C CN100570863C CNB2006100009904A CN200610000990A CN100570863C CN 100570863 C CN100570863 C CN 100570863C CN B2006100009904 A CNB2006100009904 A CN B2006100009904A CN 200610000990 A CN200610000990 A CN 200610000990A CN 100570863 C CN100570863 C CN 100570863C
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Abstract
A kind of one pixel structure process method, it forms earlier grid, the scan line that is electrically connected with grid and is electrically connected with scan line in the edge of substrate on substrate the first terminal portion.On substrate, form gate insulation layer with cover gate, scan line and the first terminal portion.On the gate insulation layer above the grid, define semiconductor layer.The patterned gate insulating barrier is to expose the first terminal portion.On substrate, form transparency conducting layer.On transparency conducting layer, form the patterning photoresist layer.Afterwards, utilize the patterning photoresist layer to be the mask patterned transparent conductive layer, to define source electrode, drain electrode, the data wire that is electrically connected with source electrode, the pixel electrode, second portion of terminal that is electrically connected with data wire that are electrically connected with drain electrode and the contact mat that is electrically connected with the first terminal portion.Because above-mentioned one pixel structure process method only need be used four road photo etched masks, therefore can reduce manufacturing cost.
Description
Technical field
The present invention relates to a kind of dot structure (pixel structure) and manufacture method thereof, and be particularly related to a kind of one pixel structure process method of utilizing four road photo etched masks (four-photomask).
Background technology
Thin Film Transistor-LCD (thin film transistor liquid crystal display, TFT-LCD) constituted by thin-film transistor array base-plate (thin film transistor arraysubstrate), colorful filter array substrate (color filter array substrate) and liquid crystal layer (liquidcrystal layer), wherein thin-film transistor array base-plate is by a plurality of thin-film transistors with arrayed (TFT), and forms with the pixel electrode (pixelelectrode) of the corresponding setting of each thin-film transistor.Above-mentioned thin-film transistor comprises grid (gate), semiconductor layer (semiconductor layer), source electrode (source) and drain electrode (drain), and thin-film transistor and pixel electrode formation dot structure (pixel structure).Wherein, thin-film transistor is used as the switch element of liquid crystal display.
When making thin-film transistor, one of most important consideration is exactly the number that reduces technology, and then reduces the cost of manufacturing.Particularly, then can effectively reduce manufacturing cost if can reduce the required photo etched mask number of technology.
Figure 1A～1G is the steps flow chart generalized section of known one pixel structure process method.Please refer to Figure 1A, at first, utilize the first road photo etched mask (not shown) on substrate 100, to define grid 110.Then, please refer to Figure 1B, on substrate 100, form gate insulation layer 120 with cover gate 110.
Then, please refer to Fig. 1 C, utilize the second road photo etched mask (not shown) to define semiconductor layer 130 on the gate insulation layer above the grid 110 120, this semiconductor layer 130 comprises channel layer 132 and ohmic contact layer 134.Then, please refer to Fig. 1 D, on substrate 100, form the metal level (not shown), and utilize the 3rd road photo etched mask (not shown) to define source electrode 142 and drain electrode 144.Particularly, can carry out again this moment etch back process (back channel etching, BCE), to remove source electrode 142 and the ohmic contact layer 134 that drains between 144, shown in Fig. 1 E.
Then, please refer to Fig. 1 F, form protective layer 150 on substrate 100, and utilize the 4th road photo etched mask technology (not shown) and this protective layer 150 of patterning, this protective layer 150 has opening 152 and exposes drain electrode 144.Afterwards, on substrate 100, form the transparency conducting layer (not shown), and utilize the 5th road photo etched mask (not shown) to define pixel electrode 160, and pixel electrode 160 can be electrically connected with drain electrode 144 by opening 152.So far, finish the manufacturing of dot structure 200.
Generally speaking, because known dot structure 200 need utilize five road photo etched masks to carry out the manufacturing of pattern.Therefore, the manufacture method of above-mentioned known pixel structure will be unfavorable for reducing the required photo etched mask number of technology, and just manufacturing cost can't reduce effectively.
Summary of the invention
In view of the foregoing, the present invention's purpose provides a kind of one pixel structure process method, and it can reduce required photo etched mask number, and then reduces manufacturing cost.
Another object of the present invention provides a kind of dot structure, and it has lower manufacturing cost.
For reaching above-mentioned or other purpose, the present invention proposes a kind of one pixel structure process method, comprises the following steps.At first, the first terminal portion that on substrate, forms grid, the scan line that is electrically connected with grid and be electrically connected with scan line in the edge of substrate.Then, on substrate, form gate insulation layer with cover gate, scan line and the first terminal portion.Then, on the gate insulation layer above the grid, define semiconductor layer.Then, the patterned gate insulating barrier is to expose the first terminal portion.Then, on substrate, form transparency conducting layer.Subsequently, on transparency conducting layer, form the patterning photoresist layer.Afterwards, utilize the patterning photoresist layer to be the mask patterned transparent conductive layer, to define source electrode, drain electrode, the data wire that is electrically connected with source electrode, the pixel electrode, second portion of terminal that is electrically connected with data wire that are electrically connected with drain electrode and the contact mat that is electrically connected with the first terminal portion, wherein, utilize the different photo etched mask technology of twice to expose this first terminal portion and this semiconductor layer of definition respectively; And this source electrode, this drain electrode, this data wire, this pixel electrode, this second portion of terminal and all be this transparency conducting layer with forming simultaneously in the photo etched mask technology with this contact mat that this first terminal portion is electrically connected.
In one of the present invention embodiment, above-mentioned semiconductor layer comprises channel layer and ohmic contact layer.
In one of the present invention embodiment, above-mentioned after patterned transparent conductive layer, also comprise the ohmic contact layer that removes between source electrode and the drain electrode.
In one of the present invention embodiment, above-mentioned after the ohmic contact layer that removes between source electrode and the drain electrode, also be included in and form protective layer on the substrate.
In one of the present invention embodiment, the material of above-mentioned protective layer comprises silica, silicon nitride or silicon oxynitride.
In one of the present invention embodiment, above-mentioned formation on substrate after the protective layer also comprises removing patterning photoresist layer and the protective layer that covers on the patterning photoresist layer simultaneously.
In one of the present invention embodiment, the above-mentioned method that forms grid, scan line and the first terminal portion on substrate comprises the following steps.At first, on substrate, form metal level.Then, on metal level, form the first patterning photoresist layer.Afterwards, utilize the first patterning photoresist layer to be mask, carry out etch process to define grid, scan line and the first terminal portion.
In one of the present invention embodiment, the material of above-mentioned metal level is to be selected from a kind of in chromium (Cr), tungsten (W), tantalum (Ta), titanium (Ti), molybdenum (Mo), aluminium (Al) and the combination thereof.
In one of the present invention embodiment, the above-mentioned method that forms gate insulation layer on substrate comprises chemical vapour deposition technique.
In one of the present invention embodiment, the material of above-mentioned gate insulation layer comprises silica, silicon nitride or silicon oxynitride.
In one of the present invention embodiment, the method that defines semiconductor layer on the above-mentioned gate insulation layer above grid comprises the following steps.On gate insulation layer, form channel material layer and ohmic contact material layer at first, successively.Then, form channel material layer and ohmic contact material layer on the gate insulation layer that the second patterning photoresist layer is covered in the grid top.Afterwards, utilize the second patterning photoresist layer to be mask, remove not by the ohmic contact material layer of the second patterning photoresist layer covering and channel material layer.
In one of the present invention embodiment, above-mentioned not removing comprised wet etching or dry-etching method by the method for the ohmic contact material layer of the second patterning photoresist layer covering and channel material layer.
In one of the present invention embodiment, this gate insulation layer of above-mentioned patterning comprises the following steps with the method that exposes the first terminal portion.At first, form the 3rd patterning photoresist layer on substrate, this 3rd patterning photoresist layer has opening, and this opening exposes the gate insulation layer of the first terminal portion top.Afterwards, be mask with the 3rd patterning photoresist layer, remove opening institute exposed portions gate insulation layer.
In one of the present invention embodiment, the above-mentioned method that forms transparency conducting layer on substrate comprises vapour deposition method or sputtering method.
In one of the present invention embodiment, the material of above-mentioned transparency conducting layer comprises indium tin oxide or indium-zinc oxide.
In one of the present invention embodiment, above-mentioned when forming grid, scan line and the first terminal portion, also be included in and form bridging line on the substrate, in order to as electrode under the pixel storage capacitor device, and the follow-up pixel electrode of bridging line top that is formed at is promptly as electrode on the pixel storage capacitor device.
For reaching above-mentioned or other purpose, the present invention reintroduces a kind of dot structure, and it comprises substrate, grid, scan line, the first terminal portion, gate insulation layer, semiconductor layer, source electrode and drain electrode, data wire, pixel electrode, second portion of terminal and contact mat.The first terminal portion that has been formed with grid, the scan line that is electrically connected with grid on the substrate and has been electrically connected with scan line in the edge of substrate.Gate insulation layer is covered on the substrate.Semiconductor layer is arranged on the gate insulation layer of grid top.Source electrode and drain electrode are arranged at the gate insulation layer top, and are electrically connected with semiconductor layer.Data wire is arranged at the gate insulation layer top, and is electrically connected with source electrode.Pixel electrode is arranged at the gate insulation layer top, and is electrically connected with drain electrode.Second portion of terminal is arranged at the gate insulation layer top, and is electrically connected with data wire.Contact mat is arranged at the gate insulation layer top, and is electrically connected with the first terminal portion.Wherein, source electrode, drain electrode, data wire, pixel electrode, second portion of terminal and contact mat are same retes, and the material of this source electrode, this drain electrode, this data wire, this pixel electrode, this second portion of terminal and this contact mat is the electrically conducting transparent material.
In one of the present invention embodiment, above-mentioned dot structure also comprises layer protective layer at least, and it is arranged on the gate insulation layer top.
In one of the present invention embodiment, above-mentioned dot structure also comprises bridging line, and it is arranged on the substrate, and this bridging line is in order to as electrode under the pixel storage capacitor device, and the pixel electrode that is positioned at the bridging line top is promptly as electrode on the pixel storage capacitor device.
The present invention adopts the technology of four road photo etched masks, its utilization forms source electrode, drain electrode simultaneously and reduces photo etched mask with the practice of pixel electrode, with known five road photo etched mask technologies comparatively speaking, the present invention not only can save the cost of photo etched mask, its processing step is also comparatively simple.
For above and other objects of the present invention, feature and advantage can be become apparent, the present invention's cited below particularly preferred embodiment, and conjunction with figs. are described in detail below.
Description of drawings
Figure 1A～1G is the steps flow chart generalized section of known one pixel structure process method.
Fig. 2 is the schematic top plan view of a kind of dot structure of a preferred embodiment of the present invention.
Fig. 3 A～3N is the steps flow chart generalized section according to a kind of one pixel structure process method of a preferred embodiment of the present invention, and it is by the generalized section of I-I ' line among Fig. 2.
The main element description of symbols
100,300: substrate
110,310 ': grid
120,350: gate insulation layer
130,360: semiconductor layer
132,362 ': channel layer
134,364 ': ohmic contact layer
142,390: source electrode
144,391: drain electrode
150,400: protective layer
152,370: opening
160,393: pixel electrode
200,500: dot structure
310: metal level
320: scan line
320a: the first terminal portion
330: bridging line
340: the pixel storage capacitor device
362: the channel material layer
364: the ohmic contact material layer
380: transparency conducting layer
392: data wire
394: the second portion of terminal
395: contact mat
I-I ': hatching
R1, R2, R3, R4: patterning photoresist layer
E1, E2, E3, E4: etch process
Embodiment
Fig. 2 is the schematic top plan view of a kind of dot structure of a preferred embodiment of the present invention.Fig. 3 A～3N is the steps flow chart generalized section according to a kind of one pixel structure process method of a preferred embodiment of the present invention, and it is by the generalized section of I-I ' line among Fig. 2.
At first, the 320a of the first terminal portion that forms grid 310 ', the scan line 320 that is electrically connected with grid 310 ' and be electrically connected with scan line 320 in the edge of substrate 300 on substrate 300 is shown in Fig. 2 and Fig. 3 C.In a preferred embodiment, the method for formation grid 310 ', scan line 320 and the 320a of the first terminal portion comprises the step as Fig. 3 A～3C on substrate 300.
Please refer to Fig. 3 A, on substrate 300, form metal level 310.This substrate 300 for example is glass substrate, quartz base plate or plastic base.The method that forms metal level 310 for example is vapour deposition method or sputtering method, and the material of metal level 310 for example is to be selected from a kind of in chromium (Cr), tungsten (W), tantalum (Ta), titanium (Ti), molybdenum (Mo), aluminium (Al) and the combination thereof.Then, please refer to Fig. 3 B, form the first patterning photoresist layer R1 on metal level 310, the technology that forms R1 for example is known photoetching process, is not given unnecessary details at this.Afterwards, the first patterning photoresist layer R1 of utilization shown in Fig. 3 B is mask, carry out etch process E1 to define grid 310 ', the scan line 320 and the 320a of the first terminal portion shown in Fig. 2 and Fig. 3 C, the 320a of this first terminal portion is that follow-up being used for is electrically connected with drive circuit.
Please continue with reference to Fig. 2, in a preferred embodiment, in above-mentioned formation grid 310 ', scan line 320 and the 320a of the first terminal portion, can on substrate 300, form bridging line 330 again, in order to as electrode under the pixel storage capacitor device 340, and the follow-up pixel electrode 393 of bridging line 330 tops that is formed at is promptly as electrode on the pixel storage capacitor device 340.
Then, on substrate 300, form gate insulation layer 350 with cover gate 310 ', scan line 320 (as shown in Figure 2) and the 320a of the first terminal portion, shown in Fig. 3 D.In one of the present invention embodiment, the method that forms gate insulation layer 350 on substrate 300 comprises that (chemical vapor deposition, CVD), and the material of gate insulation layer 350 for example is silica, silicon nitride or silicon oxynitride to chemical vapour deposition technique.
Then, on the gate insulation layer 350 of grid 310 ' top, define semiconductor layer 360, shown in Fig. 2 and Fig. 3 G.In one of the present invention embodiment, semiconductor layer 360 comprises channel layer 362 ' and ohmic contact layer 364 ', and the method that defines semiconductor layer 360 on the gate insulation layer 350 of grid 310 ' top comprises the step as Fig. 3 E～3G.
Please refer to Fig. 3 E, on gate insulation layer 350, form channel material layer 362 and ohmic contact material layer 364 successively.The material of channel material layer 362 for example is an amorphous silicon, and the material of ohmic contact material layer 364 for example is through doped amorphous silicon.And the method that forms channel material layer 362 and ohmic contact material layer 364 for example is a chemical vapour deposition technique.
Then, please refer to Fig. 3 F, form channel material layer 362 and ohmic contact material layer 364 on the gate insulation layer 350 that the second patterning photoresist layer R2 is covered in grid 310 ' top.Afterwards, utilize the second patterning photoresist layer R2 to be mask, carry out etch process E2 and remove not, and define semiconductor layer 360 shown in Fig. 3 G by the ohmic contact material layer 364 and channel material layer 362 of the second patterning photoresist layer R2 covering.In one embodiment, do not remove by the method (being etch process E2) of the ohmic contact material layer 364 of the second patterning photoresist layer R2 covering and channel material layer 362 and comprise wet etching or dry-etching method.
Subsequently, patterned gate insulating barrier 350 is to expose the 320a of the first terminal portion, shown in Fig. 3 I.In one of the present invention embodiment, this gate insulation layer 350 of patterning comprises step as Fig. 3 H～3I with the method that exposes the 320a of the first terminal portion.
At first, please refer to Fig. 3 H, form the 3rd patterning photoresist layer R3 on substrate 300, this 3rd patterning photoresist layer R3 has opening 370, and this opening 370 exposes the gate insulation layer 350 of the first terminal portion 320a top.Afterwards, be mask with the 3rd patterning photoresist layer R3, carry out etch process E3 and remove 370 exposed portions gate insulation layers 350 of opening, and then form structure shown in Fig. 3 I.Afterwards, remove the 3rd patterning photoresist layer R3.
Then, on substrate 300, form transparency conducting layer 380, shown in Fig. 3 J.In one of the present invention embodiment, the method that forms transparency conducting layer 380 on substrate 300 comprises vapour deposition method or sputtering method, and the material of transparency conducting layer 380 for example be indium tin oxide (Indium Tin Oxide, ITO) or indium-zinc oxide (Indium Zinc Oxide, IZO).Particularly, the transparency conducting layer shown in Fig. 3 J 380 can be electrically connected with the 320a of the first terminal portion.
Then, on transparency conducting layer 380, form patterning photoresist layer R4, shown in Fig. 3 K.Subsequently, please be simultaneously with reference to Fig. 2 and Fig. 3 K, utilize this patterning photoresist layer R4 to be mask, carry out etch process E4 and patterned transparent conductive layer 380, with define source electrode 390, drain electrode 391, the data wire 392 that is electrically connected with source electrode 390, with the contact mat 395 that drains 391 pixel electrodes that are electrically connected 393, second portion of terminal 394 that is electrically connected with data wire 392 and be electrically connected with the 320a of the first terminal portion.
In addition, in one of the present invention embodiment, also comprise the step of carrying out as Fig. 3 L～3N.Shown in Fig. 3 L, after patterned transparent conductive layer 380, also comprise the ohmic contact layer 364 that removes between source electrode 390 and the drain electrode 391, thus, thin-film transistor will have the function of switch.Simultaneously, remove not exclusively for preventing ohmic contact layer 364, (back channel etching BCE) removes channel layer 362 ' partly also can to carry out the passage etch back process usually.
Then, shown in Fig. 3 M, after the ohmic contact layer 364 that removes between source electrode 390 and the drain electrode 391, also be included in and form protective layer 400 on the substrate 300.In one embodiment, the method that forms protective layer 400 comprises chemical vapour deposition technique, and the material of protective layer 400 comprises silica, silicon nitride or silicon oxynitride.What deserves to be mentioned is; the protective layer 400 of part can cover on source electrode 390 and the channel layer 362 ' that drains between 391; and the effect of performance protection channel layer 362 ' can be formed on patterning photoresist layer R4 and the gate insulation layer 350 as for the protective layer 400 of other parts.
, on substrate 300, form after the protective layer 400 thereupon, also comprise removing patterning photoresist layer R4 and the protective layer 400 that covers on the patterning photoresist layer R4 simultaneously, shown in Fig. 3 N.It should be noted that when removing patterning photoresist layer R4 that the protective layer 400 that is positioned on the patterning photoresist layer R4 also can remove thereupon.In one embodiment, the method that removes patterning photoresist layer R4 for example is to utilize organic solvent to divest this photoresist.
In sum, in above-mentioned one pixel structure process method, only need use four road photo etched mask technologies, wherein first photo etched mask is to be used for defining metal level 310, to form grid 310 ', scan line 320, bridging line 330 and the 320a of the first terminal portion (shown in Fig. 3 C).The second road photo etched mask technology is definition semiconductor layer 360 (shown in Fig. 3 G).The 3rd road photo etched mask technology is to be used for patterned gate insulating barrier 350, so that gate insulation layer 350 exposes the 320a of the first terminal portion (shown in Fig. 3 I).The 4th road photo etched mask technology is to be used for patterned transparent conductive layer 380, to define source electrode 390, drain electrode 391, data wire 392, pixel electrode 393, second portion of terminal 394 and contact mat 395 (shown in Fig. 3 K).Because source electrode 390, drain electrode 391, pixel electrode 393 is to form simultaneously, so and known five road photo etched mask technologies comparatively speaking, the photo etched mask negligible amounts of the present invention's one pixel structure process method use, and then can reduce manufacturing cost.Utilize above-mentioned one pixel structure process method, can make the dot structure 500 shown in Fig. 2 and Fig. 3 N.
Please be simultaneously with reference to Fig. 2 and Fig. 3 N, the present invention's dot structure 500 comprises substrate 300, grid 310 ', scan line 320, the 320a of the first terminal portion, gate insulation layer 350, semiconductor layer 360, source electrode 390 and drain electrode 391, data wire 392, pixel electrode 393, second portion of terminal 394 and contact mat 395.The 320a of the first terminal portion that has been formed with grid 310 ', the scan line 320 that is electrically connected with grid 310 ' on this substrate 300 and has been electrically connected with scan line 320 in the edge of substrate 300.Gate insulation layer 350 is covered on the substrate 300.Semiconductor layer 360 is arranged on the gate insulation layer 350 of grid 310 ' top.Source electrode 390 is arranged at gate insulation layer 350 tops with drain electrode 391, and is electrically connected with semiconductor layer 360.Data wire 392 is arranged at gate insulation layer 350 tops, and is electrically connected with source electrode 390.Pixel electrode 393 is arranged at gate insulation layer 350 tops, and is electrically connected with drain electrode 391.Second portion of terminal 394 is arranged at gate insulation layer 350 tops, and is electrically connected with data wire 392.Contact mat 395 is arranged at gate insulation layer 350 tops, and is electrically connected with the 320a of the first terminal portion.Wherein, source electrode 390, drain electrode 391, data wire 392, pixel electrode 393, second portion of terminal 394 are same retes with contact mat 395.It should be noted that grid 310 ', source electrode 390, drain electrode 391, semiconductor layer 360 common formation thin-film transistors.
From the above, in one of the present invention embodiment, source electrode 390, drain electrode 391, data wire 392, pixel electrode 393, second portion of terminal 394 comprise the electrically conducting transparent material with the material of contact mat 395, it for example is indium tin oxide or indium-zinc oxide, because elements such as source electrode 390, drain electrode 391, data wire 392, pixel electrode 393, second portion of terminal 394 and contact mat 395 are same retes, therefore, the use of material can be reduced, and photo etched mask technology can be reduced one.Thus, can reduce the manufacturing cost of the present invention's dot structure 500.
In addition, shown in Fig. 3 N, the present invention's dot structure 500 can also comprise layer protective layer 400 at least, and it is arranged on gate insulation layer 350 tops.Particularly, on the protective layer 400 meeting covering source electrodes 390 and the channel layer 362 ' between the drain electrode 391 of part, and the effect of performance protection channel layer 362 '.In one embodiment, the material of this protective layer 400 for example is a transparent material.
Please continue with reference to Fig. 2, in one of the present invention embodiment, dot structure 500 can also comprise bridging line 330, it is arranged on the substrate 300, this bridging line 330 is in order to as electrode under the pixel storage capacitor device 340, and the pixel electrode 393 that is positioned at bridging line 330 tops is promptly as electrode on the pixel storage capacitor device 340.Thus, can further improve the operation usefulness of dot structure 500.
In sum, the present invention's one pixel structure process method and dot structure have following advantage:
(1) the present invention adopts the technology of four road photo etched masks, wherein when the 4th road photo etched mask technology elements such as source electrode, drain electrode, pixel electrode is formed simultaneously.With known five road photo etched mask technologies comparatively speaking, the present invention's one pixel structure process method not only can be saved one photo etched mask, and its processing step is also comparatively simple.
(2) elements such as source electrode of the present invention, drain electrode, data wire, pixel electrode, second portion of terminal and contact mat are same retes.So, the use that can save material, and then reduce manufacturing cost.
(3) owing to being the manufacturing of under the situation that the patterning photoresist layer still exists, carrying out protective layer, so the protective layer of part can be formed on the patterning photoresist layer.Therefore, when removing the patterning photoresist layer, can remove the protective layer that is formed on the patterning photoresist layer follow-up simultaneously.
(4) protective layer can cover source electrode and the drain electrode between channel layer on, thereby protective layer can bring into play the protection channel layer effect.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any person of ordinary skill in the field; without departing from the spirit and scope of the present invention; when can doing a little change and improvement, so protection scope of the present invention is as the criterion when looking the claim person of defining.
Claims (19)
1. one pixel structure process method is characterized in that comprising:
The first terminal portion that on substrate, forms grid, the scan line that is electrically connected with this grid and be electrically connected with this scan line in the edge of this substrate;
On this substrate, form gate insulation layer, to cover this grid, this scan line and this first terminal portion;
On this gate insulation layer above this grid, define semiconductor layer;
This gate insulation layer of patterning is to expose this first terminal portion;
On this substrate, form transparency conducting layer;
On this transparency conducting layer, form the patterning photoresist layer;
Utilize this patterning photoresist layer to be this transparency conducting layer of mask patterning, with the contact mat that defines source electrode, drain electrode, the data wire that is electrically connected with this source electrode, the pixel electrode that is electrically connected with this drain electrode, second portion of terminal that is electrically connected with this data wire and be electrically connected with this first terminal portion;
Wherein, utilize the different photo etched mask technology of twice to expose this first terminal portion and this semiconductor layer of definition respectively; And
This source electrode, this drain electrode, this data wire, this pixel electrode, this second portion of terminal and all be this transparency conducting layer with forming simultaneously in the photo etched mask technology with this contact mat that this first terminal portion is electrically connected.
2. the one pixel structure process method according to claim 1 is characterized in that this semiconductor layer comprises channel layer and ohmic contact layer.
3. the one pixel structure process method according to claim 2 is characterized in that also comprising this ohmic contact layer that removes between this source electrode and this drain electrode after this transparency conducting layer of patterning.
4. the one pixel structure process method according to claim 3 is characterized in that also being included on this substrate and forming protective layer after this ohmic contact layer that removes between this source electrode and this drain electrode.
5. the one pixel structure process method according to claim 4 is characterized in that the material of this protective layer comprises silica, silicon nitride or silicon oxynitride.
6. the one pixel structure process method according to claim 4 is characterized in that forming after this protective layer on this substrate, also comprises removing this patterning photoresist layer and this protective layer that covers on this patterning photoresist layer simultaneously.
7. the one pixel structure process method according to claim 1 is characterized in that the method that forms this grid, this scan line and this first terminal portion on this substrate comprises:
On this substrate, form metal level;
On this metal level, form the first patterning photoresist layer; And
Utilize this first patterning photoresist layer to be mask, carry out etch process to define this grid, this scan line and this first terminal portion.
8. the one pixel structure process method according to claim 7, the material that it is characterized in that this metal level are to be selected from a kind of in chromium, tungsten, tantalum, titanium, molybdenum, aluminium and the combination thereof.
9. the one pixel structure process method according to claim 1 is characterized in that the method that forms this gate insulation layer on this substrate comprises chemical vapour deposition technique.
10. the one pixel structure process method according to claim 1 is characterized in that the material of this gate insulation layer comprises silica, silicon nitride or silicon oxynitride.
11. the one pixel structure process method according to claim 1 is characterized in that the method that defines semiconductor layer on this gate insulation layer above this grid comprises:
On this gate insulation layer, form channel material layer and ohmic contact material layer successively;
Form this channel material layer and this ohmic contact material layer on this gate insulation layer that the second patterning photoresist layer is covered in this grid top; And
Utilize this second patterning photoresist layer to be mask, remove not by this ohmic contact material layer of this second patterning photoresist layer covering and this channel material layer.
12. the one pixel structure process method according to claim 11 not is characterized in that removing and comprised wet etching or dry-etching method by the method for this ohmic contact material layer of this second patterning photoresist layer covering and this channel material layer.
13. the one pixel structure process method according to claim 1 is characterized in that this gate insulation layer of patterning, comprises with the method that exposes this first terminal portion:
Form the 3rd patterning photoresist layer on this substrate, the 3rd patterning photoresist layer has opening, and this opening exposes this gate insulation layer of this first terminal portion top; And
With the 3rd patterning photoresist layer is mask, removes this opening institute this gate insulation layer of exposed portions.
14. the one pixel structure process method according to claim 1 is characterized in that the method that forms this transparency conducting layer on this substrate comprises vapour deposition method or sputtering method.
15. the one pixel structure process method according to claim 1 is characterized in that the material of this transparency conducting layer comprises indium tin oxide or indium-zinc oxide.
16. the one pixel structure process method according to claim 1, it is characterized in that when forming this grid, this scan line and this first terminal portion, also be included on this substrate and form bridging line, in order to as electrode under the pixel storage capacitor device, and follow-up this pixel electrode of this bridging line top that is formed at is promptly as electrode on this pixel storage capacitor device.
17. a dot structure is characterized in that comprising:
Substrate, the first terminal portion that has been formed with grid, the scan line that is electrically connected with this grid on this substrate and has been electrically connected with this scan line in the edge of this substrate;
Gate insulation layer is covered on this substrate;
Semiconductor layer is arranged on this gate insulation layer of this grid top;
Source electrode and drain electrode are arranged at this gate insulation layer top, and are electrically connected with this semiconductor layer;
Data wire is arranged at this gate insulation layer top, and is electrically connected with this source electrode;
Pixel electrode is arranged at this gate insulation layer top, and is electrically connected with this drain electrode;
Second portion of terminal is arranged at this gate insulation layer top, and is electrically connected with this data wire;
Contact mat is arranged at this gate insulation layer top, and is electrically connected with this first terminal portion;
Wherein, this source electrode, this drain electrode, this data wire, this pixel electrode, this second portion of terminal and this contact mat are same retes, and the material of this source electrode, this drain electrode, this data wire, this pixel electrode, this second portion of terminal and this contact mat is the electrically conducting transparent material.
18. the dot structure according to claim 17 is characterized in that also comprising layer protective layer at least, is arranged on this gate insulation layer top.
19. the dot structure according to claim 17, it is characterized in that also comprising bridging line, be arranged on this substrate, this bridging line is in order to as electrode under the pixel storage capacitor device, and this pixel electrode that is positioned at this bridging line top is promptly as electrode on this pixel storage capacitor device.
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| CNB2006100009904A CN100570863C (en) | 2006-01-13 | 2006-01-13 | Dot structure and manufacture method thereof |
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| CNB2006100009904A CN100570863C (en) | 2006-01-13 | 2006-01-13 | Dot structure and manufacture method thereof |
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| WO2011070981A1 (en) * | 2009-12-09 | 2011-06-16 | シャープ株式会社 | Semiconductor device and method for producing same |
| CN102692771B (en) | 2011-05-09 | 2014-12-17 | 京东方科技集团股份有限公司 | Liquid crystal display, thin-film transistor array substrate and manufacturing method thereof |
| CN102637635B (en) * | 2011-08-16 | 2015-04-29 | 京东方科技集团股份有限公司 | Display device, liquid crystal display panel, array substrate and manufacturing method of array substrate |
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| JP2019091835A (en) * | 2017-11-16 | 2019-06-13 | シャープ株式会社 | Tft substrate, scanning antenna comprising the same, and method of manufacturing tft substrate |
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| CN111367130A (en) * | 2020-04-27 | 2020-07-03 | Tcl华星光电技术有限公司 | Array substrate, display panel and display device |
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2006
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