CN102637684B - Array substrate used for display equipment and manufacturing method thereof - Google Patents

Abstract

The invention discloses an array substrate used for display equipment, which comprises a substrate with a pixel part, a signal line, an oxide semiconductor layer, an insulation layer and a scanning line metal layer, wherein the signal line and the oxide semiconductor layer are positioned on the substrate; a first part of the oxide semiconductor layer serves as the pixel part; a second part of the oxide semiconductor layer serves as a terminal part of the scanning line; a third part of the oxide semiconductor layer serves as a terminal part of the signal line; the insulation layer is positioned on the signal line and the oxide semiconductor layer; the insulation layer is provided with the terminal part exposed out of the scanning line, the terminal part of the signal line, the single line and a source electrode contact hole; the scanning line metal layer is positioned on the insulation layer; a first part of the scanning line metal layer is connected with a source electrode and the signal line by the contact hole; a second part of the scanning line metal layer serves as the scanning line and a grid electrode; the scanning line and the signal line are intersected to define the pixel part; the scanning line is connected with the grid electrode and the terminal part of the scanning line; a third part of the scanning line metal layer is connected with the signal line and the terminal part of the signal line; and the oxide semiconductor layer exposed in an ion implantation or annealing processing mode becomes a transparent electrode with conductor characteristics.

Description

For array base palte and the manufacture method thereof of display device

Technical field

The present invention relates to the array base palte for display device, particularly comprise the array base palte of the thin-film transistor with oxide semiconductor layer, and the manufacture method of this array base palte.

Background technology

Metal current oxide semiconductor TFT(thin-film transistor) processing procedure with existing amorphous silicon processing procedure similar, except traditional BCE(Back Channel Etching, back of the body passage etching)) outside structure, consider characteristic of semiconductor and have ESL(Etch Stop Layer, etching barrier layer) and the coplanar framework of Co-Planar, required processing procedure needs five roads or six road light shields, and processing procedure is comparatively complicated, and manufacturing cost is higher.Fig. 1 adopts IGZO(Indium Gallium Zinc Oxide at present; indium gallium zinc oxide) the main ESL structure of making thin-film transistor; with a-Si(amorphous silicon) the BCE structure of thin-film transistor is similar, and main difference is adding that ESL dielectric protection layer semiconductor layer is to maintain good TFT characteristic.

Summary of the invention

Goal of the invention: for the problem and shortage of above-mentioned prior art existence, the object of this invention is to provide a kind of manufacture method of array base palte and this array base palte for display device, can simplify processing procedure, reduce manufacturing cost.

Technical scheme: for achieving the above object, the first technical scheme that the present invention adopts is a kind of array base palte for display device, comprising:

There is the substrate of pixel portion;

Be positioned at holding wire and oxide semiconductor layer on described substrate, the Part I of described oxide semiconductor layer is as pixel portion, the Part II of described oxide semiconductor layer is as the portion of terminal of scan line, and the Part III of described oxide semiconductor layer is as the portion of terminal of holding wire;

Be positioned at the insulating barrier on described holding wire and oxide semiconductor layer, this insulating barrier has the contact hole of portion of terminal, holding wire and the source electrode of the portion of terminal, the holding wire that expose described scan line;

Be positioned at the scan line metal level on described insulating barrier, the Part I of described scan line metal level connects source electrode and holding wire by described contact hole, the Part II of described scan line metal level is as scan line and grid, described scan line and holding wire intersect to limit described pixel portion, described scan line connects respectively grid and connects the portion of terminal of scan line by described contact hole, and the Part III of described scan line metal level connects the portion of terminal of holding wire and holding wire by described contact hole;

Adopt the mode of Implantation or annealing in process to make the oxide semiconductor layer exposing become the transparency electrode with conductor characteristics.

The preferred indium gallium of the material zinc oxide of described oxide semiconductor layer.

The preferred silicon dioxide of material of described insulating barrier or the combination of silicon nitride or silicon dioxide and silicon nitride.

The second technical scheme that the present invention adopts is a kind of method of manufacturing array substrate, comprises the steps:

(1) first light shield: form holding wire on the array base palte with pixel portion;

(2) second light shield: form oxide semiconductor layer on the array base palte with pixel portion, the Part I of described oxide semiconductor layer is as pixel portion, the Part II of described oxide semiconductor layer is as the portion of terminal of scan line, and the Part III of described oxide semiconductor layer is as the portion of terminal of holding wire;

(3) on described holding wire and oxide semiconductor layer, form insulating barrier;

(4) San road light shield: the contact hole that forms portion of terminal, holding wire and the source electrode of the portion of terminal, the holding wire that expose described scan line on described insulating barrier;

(5) adopt the mode of Implantation or annealing in process to make the oxide semiconductor layer exposing become the transparency electrode with conductor characteristics;

(6) Si road light shield: form scan line metal level on described insulating barrier, the Part I of described scan line metal level connects source electrode and holding wire by described contact hole, the Part II of described scan line metal level is as scan line and grid, described scan line and holding wire intersect to limit described pixel portion, described scan line connects respectively grid and connects the portion of terminal of scan line by described contact hole, and the Part III of described scan line metal level connects the portion of terminal of holding wire and holding wire by described contact hole.

The preferred indium gallium of the material zinc oxide of described oxide semiconductor layer.

The preferred silicon dioxide of material of described insulating barrier or the combination of silicon nitride or silicon dioxide and silicon nitride.

Beneficial effect: the present invention can simplify the processing procedure of IGZO semiconductor TFT, is reduced to four road light shields by original Wu Zhi six road light shields, effectively reduces manufacturing cost.

Brief description of the drawings

Fig. 1 is the transistorized ESL schematic cross-section of prior art metal oxide semiconductor films;

Fig. 2 (A) forms the schematic diagram of bottom layer signal line metallic pattern for the present invention; Fig. 2 (B) is the A-A ' profile of Fig. 2 (A);

Fig. 3 (A) forms the structural representation of IGZO layer for the present invention; Fig. 3 (B) is the B-B ' profile of Fig. 3 (A);

Fig. 4 (A) forms the structural representation of insulating barrier and contact hole for the present invention; Fig. 4 (B) is the C-C ' profile of Fig. 4 (A);

Fig. 5 (A) forms the structural representation of scan line metal level for the present invention, and Fig. 5 (B) is the D-D ' profile of Fig. 5 (A).

Embodiment

Below in conjunction with the drawings and specific embodiments, further illustrate the present invention, should understand these embodiment is only not used in and limits the scope of the invention for the present invention is described, after having read the present invention, those skilled in the art all fall within the application's claims limited range to the amendment of the various equivalent form of values of the present invention.

As shown in Fig. 2 (A) and Fig. 2 (B), on the array base palte with pixel portion, utilize underlying metal to form the holding wire of vertical direction.

As shown in Fig. 3 (A) and Fig. 3 (B), on the array base palte with pixel portion, form IGZO layer, the Part I of this IGZO layer is as pixel portion, between two adjacent signals lines, the Part II of this IGZO layer is as the portion of terminal of scan line, be arranged in the lower left of figure holding wire, the Part III of this IGZO layer, as the portion of terminal of holding wire, is positioned at the top of each signal line.

As shown in Fig. 4 (A) and Fig. 4 (B), first on holding wire and IGZO layer, form the insulating barrier of earth silicon material, on this insulating barrier, form again the contact hole that exposes the portion of terminal of scan line, portion of terminal, holding wire and the source electrode of holding wire (be actually subsequent step and form the position that is connected source electrode), then adopt the mode of Implantation to make the IGZO layer exposing become the transparency electrode with conductor characteristics.

As shown in Fig. 5 (A) and Fig. 5 (B), on insulating barrier, form scan line metal level, the Part I of this scan line metal level connects source electrode and holding wire by contact hole, the Part II of scan line metal level is as scan line and the grid of horizontal direction, this scan line intersects to limit pixel portion with holding wire, this scan line connects respectively grid and connects the portion of terminal of scan line by contact hole, and the Part III of this scan line metal level connects the portion of terminal of holding wire and holding wire by contact hole.The IGZO layer on the insulating barrier right side of grid below is connected to the IGZO layer (being pixel electrode) that is positioned at pixel portion as drain electrode.Due to the protection of the insulating barrier of grid below, the IGZO layer under this insulating barrier still keeps semi-conductive attribute, ensures that between the source electrode in its left side and the drain electrode on its right side be opening circuit in electricity.

Claims (4)

1. for an array base palte for display device, comprising:

There is the substrate of pixel portion;

Be positioned at holding wire and oxide semiconductor layer on described substrate, the material of described oxide semiconductor layer is indium gallium zinc oxide, the Part I of described oxide semiconductor layer is as pixel portion, the Part II of described oxide semiconductor layer is as the portion of terminal of scan line, and the Part III of described oxide semiconductor layer is as the portion of terminal of holding wire;

Be positioned at the insulating barrier on described holding wire and oxide semiconductor layer, this insulating barrier has the contact hole of portion of terminal, holding wire and the source electrode of the portion of terminal, the holding wire that expose described scan line;

Be positioned at the scan line metal level on described insulating barrier, the Part I of described scan line metal level connects source electrode and holding wire by described contact hole, the Part II of described scan line metal level is as scan line and grid, described scan line and holding wire intersect to limit described pixel portion, described scan line connects respectively grid and connects the portion of terminal of scan line by described contact hole, and the Part III of described scan line metal level connects the portion of terminal of holding wire and holding wire by described contact hole;

Adopt the mode of Implantation or annealing in process to make the oxide semiconductor layer exposing become the transparency electrode with conductor characteristics.

2. according to claim 1 for the array base palte of display device, it is characterized in that: the material of described insulating barrier is the combination of silicon dioxide or silicon nitride or silicon dioxide and silicon nitride.

3. a method for manufacturing array substrate, comprises the steps:

(1) first light shield: form holding wire on the array base palte with pixel portion;

(2) second light shield: form oxide semiconductor layer on the array base palte with pixel portion, the material of described oxide semiconductor layer is indium gallium zinc oxide, the Part I of described oxide semiconductor layer is as pixel portion, the Part II of described oxide semiconductor layer is as the portion of terminal of scan line, and the Part III of described oxide semiconductor layer is as the portion of terminal of holding wire;

(3) on described holding wire and oxide semiconductor layer, form insulating barrier;

(4) San road light shield: the contact hole that forms portion of terminal, holding wire and the source electrode of the portion of terminal, the holding wire that expose described scan line on described insulating barrier;

(5) adopt the mode of Implantation or annealing in process to make the oxide semiconductor layer exposing become the transparency electrode with conductor characteristics;

(6) Si road light shield: form scan line metal level on described insulating barrier, the Part I of described scan line metal level connects source electrode and holding wire by described contact hole, the Part II of described scan line metal level is as scan line and grid, described scan line and holding wire intersect to limit described pixel portion, described scan line connects respectively grid and connects the portion of terminal of scan line by described contact hole, and the Part III of described scan line metal level connects the portion of terminal of holding wire and holding wire by described contact hole.

4. the method for manufacturing array substrate according to claim 3, is characterized in that: the material of described insulating barrier is the combination of silicon dioxide or silicon nitride or silicon dioxide and silicon nitride.