CN101609236A - Method for manufacturing thin film transistor array substrate - Google Patents
Method for manufacturing thin film transistor array substrate Download PDFInfo
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- CN101609236A CN101609236A CNA2009100548424A CN200910054842A CN101609236A CN 101609236 A CN101609236 A CN 101609236A CN A2009100548424 A CNA2009100548424 A CN A2009100548424A CN 200910054842 A CN200910054842 A CN 200910054842A CN 101609236 A CN101609236 A CN 101609236A
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Abstract
The present invention relates to a kind of method for manufacturing thin film transistor array substrate, this manufacture method utilizes the first road light shield to form continuous controlling grid scan line and interrupted data line simultaneously at the first metal layer; Utilize the second road light shield to carry out that carve on the island and carve in the hole at gate insulation layer, semiconductor layer and ohmic contact layer; Utilize the 3rd road light shield to form source electrode, drain electrode, pixel electrode and cross-over electrode at transparency conducting layer at last, described pixel electrode links to each other with described drain electrode, described cross-over electrode links to each other with described source electrode, and described cross-over electrode links to each other adjacent two segment data lines by contact hole; Thereby saved the making of second metal level and passivation layer and the light shield number has been reduced to three roads, shortened the processing procedure time, reduced cost.
Description
Technical field
The present invention relates to a kind of manufacturing method of array base plate, particularly relate to a kind of method for manufacturing thin film transistor array substrate.
Background technology
Thin Film Transistor-LCD (TFT LCD) is a kind of flat-panel screens that is widely used most at present, has low-power consumption, external form is thin, in light weight and feature such as low driving voltage.TFT LCD mainly by thin-film transistor array base-plate, colored optical filtering substrates and between liquid crystal layer constitute.Generally speaking, array base palte comprises a plurality of sub-pixels.Fig. 1 is the planimetric map of existing thin-film transistor array base-plate dot structure, comprise the parallel public electrode wire of a controlling grid scan line 1, and controlling grid scan line 12, a data line 3 and a transparent pixels electrode 5, the position that intersects at controlling grid scan line 1 and data line 3 is provided with thin film transistor (TFT) 4, and thin film transistor (TFT) 4 serves as on-off element.
Usually tft array substrate comprises a plurality of thin layers such as grid layer, gate insulator, semiconductor layer, source-drain electrode layer and passivation layer etc., and uses the method for optical mask plate by photoetching separately that film is formed pattern respectively.Generally speaking, the manufacturing of amorphous silicon film transistor array base palte needs three magnetron sputterings (sputter) deposit film, three PECVD deposit films, 4～5 photoetching processes just can finish.Therefore, in order to reduce manufacturing time and to save cost, need a kind of structure and the method that can simplify the tft array substrate manufacturing process.
Summary of the invention
Technical matters to be solved by this invention provides a kind of method for manufacturing thin film transistor array substrate, can effectively reduce light shield number of times and sputtering technology, thereby simplified manufacturing technique, reduces manufacturing cost.
The present invention solves the problems of the technologies described above the technical scheme that adopts to provide a kind of method for manufacturing thin film transistor array substrate, said method comprising the steps of:
One substrate is provided, and on this substrate deposition the first metal layer and one first photoresist layer, utilize first light shield to form grid, controlling grid scan line, data line, and described grid and controlling grid scan line be electrically connected, described data line is separated by controlling grid scan line and is multistage;
Continue deposition gate insulation layer, semiconductor layer, ohmic contact layer and one second photoresist layer on substrate, utilize second light shield to form source area, drain region, raceway groove, every segment data line top is formed with a contact hole at least;
On substrate, continue the deposit transparent conductive layer at last, utilize the 3rd light shield to form pixel electrode and cross-over electrode, and in described source area, drain region formation source electrode and drain electrode, described pixel electrode links to each other with described drain electrode, described cross-over electrode links to each other with described source electrode, and described cross-over electrode links to each other adjacent two segment data lines by contact hole.
Above-mentioned method for manufacturing thin film transistor array substrate, described second light shield is many gray-level masks, and the light shield at corresponding contact hole place has the maximum transmission degree, and after mask exposure, second photoresist layer at contact hole place is removed fully, forms contact hole after the etching.
Above-mentioned method for manufacturing thin film transistor array substrate, when utilizing second light shield to form contact hole, the light shield at respective pixel electrode district place has the maximum transmission degree, after mask exposure, second photoresist layer at place, pixel electrode district is removed fully, and the gate insulation layer after the etching on the pixel electrode district, semiconductor layer, ohmic contact layer are removed in the lump.The present invention contrasts prior art following beneficial effect: method for manufacturing thin film transistor array substrate provided by the invention, utilize the first road light shield to form continuous controlling grid scan line and interrupted data line simultaneously at the first metal layer; Utilize the second road light shield to carry out that carve on the island and carve in the hole at gate insulation layer, semiconductor layer and ohmic contact layer; Utilize the 3rd road light shield to form pixel electrode and cross-over electrode at transparency conducting layer at last, interrupted data line is linked up; Thereby saved the making of second metal level and passivation layer and the light shield number has been reduced to three roads, shortened the processing procedure time, reduced cost.In addition, the array base palte that adopts the present invention to make, pixel electrode is no gate insulation layer and passivation layer down, can improve the light transmission degree.
Description of drawings
Fig. 1 is the planimetric map of existing thin-film transistor array base-plate dot structure;
Fig. 2 is a dot structure planimetric map of the present invention;
Fig. 3 A is a kind of production process cut-open view of the present invention to Fig. 3 C;
Fig. 4 A is an another kind of production process cut-open view of the present invention to Fig. 4 B.
Among the figure:
1: controlling grid scan line 2: public electrode wire
3: data line 4: thin film transistor (TFT)
5: pixel electrode 6: contact hole
7: cross-over electrode
11: transparency carrier 12: gate insulator
13: semiconductor layer 14: ohmic contact layer
4A: grid 4B: source area
4C: drain region 4D: channel region
Embodiment
The invention will be further described below in conjunction with accompanying drawing and exemplary embodiments.
Fig. 2 is a dot structure planimetric map of the present invention; Fig. 3 A is a kind of production process cut-open view of the present invention to Fig. 3 C.
Please refer to Fig. 2, this dot structure comprises many controlling grid scan line 1, the public electrode wires 2 that extend along first direction, many data lines 3 that extend along second direction, and controlling grid scan line 1 and data line 3 intersect to form pixel region; And be arranged on thin film transistor (TFT) 4 and pixel electrode 5 in the pixel region.
Introduce making flow process of the present invention below in detail.
Please refer to Fig. 3 A, one transparency carrier 11 at first is provided, the deposition the first metal layer and first photoresist layer on transparency carrier 11, by the first mask process patterning the first metal layer, the TFT grid 4A, public electrode wire 2, the data line 3 that form controlling grid scan line 1, be electrically connected with controlling grid scan line 1, data line 3 is separated by controlling grid scan line 1 and public electrode wire 2 and is multistage, thus data line 3 not with controlling grid scan line 1 and public electrode wire 2 short circuits.
Please refer to Fig. 3 B, on the first metal layer pattern, continue to deposit successively gate insulation layer 12, amorphous silicon semiconductor layer 13, N+ doped amorphous silicon ohmic contact layer 14 and second photoresist layer.Utilization etches source area 4B, drain region 4C, the channel region 4D of TFT based on second mask process of HTM or GTM technology, and contact hole 6.
Described second light shield is many gray-level masks, the second mask process embodiment is: used HTM or GTM light shield have different penetrabilitys, the light shield at wherein corresponding contact hole 6 places has the maximum transmission degree, after mask exposure, second photoresist layer is removed fully herein, so contact hole 6 is carved at first; Part has second penetrability beyond contact hole 6, the TFT4, residue gate insulator 12 after the etching; Carry out the etching of TFT channel region 4D then; Peel off the photoresist at TFT source area 4B and drain region 4C place at last.
With reference to Fig. 3 C, on substrate, continue the deposit transparent conductive layer at last, utilize the 3rd light shield to form pixel electrode 5 and cross-over electrode 7, and form the drain region 4C formation drain electrode of source electrode, TFT at the source area 4B place of TFT.Wherein, cross-over electrode 7 links to each other with described source electrode, and described cross-over electrode 7 links to each other adjacent two segment data lines 4 by contact hole 6, and pixel electrode 5 links to each other with described drain electrode, and forms memory capacitance with public electrode wire 2 and gate insulator therebetween 12.
Through above-mentioned steps, adopt three road light shield numbers promptly to finish the array base palte processing procedure, and saved the making of second metal level and passivation layer, shortened the processing procedure time, reduced cost.Through the array base palte that said method is made, pixel electrode is no passivation layer down, improves the light transmission degree.
Fig. 4 A is an another kind of production process cut-open view of the present invention to Fig. 4 B.
Please refer to Fig. 4 A, in second mask process, have identical penetrability corresponding to the light shield at pixel electrode 5 places, so the gate insulator 12 in pixel electrode district is etched away in the lump with contact hole 6 places based on HTM or GTM.
Please refer to Fig. 4 B, behind the 3rd mask process, below the pixel electrode 5 except with public electrode 2 overlapping places, other local non-grid insulation courses 12 cover.Through the array base palte that said method is made, non-grid insulation course and passivation layer under the pixel electrode further improve the light transmission degree.
In sum, method for manufacturing thin film transistor array substrate of the present invention is made controlling grid scan line and data line simultaneously at the first metal layer, and at transparency conducting layer formation source electrode, drain electrode, pixel electrode and cross-over electrode, thereby saved the making of second metal level and passivation layer and the light shield number has been reduced to three roads, shorten the processing procedure time, reduced cost.
In addition, above embodiment is data line and is separated form for multistage by controlling grid scan line and public electrode wire, and the present invention also can adopt controlling grid scan line and public electrode wire to be separated form for multistage by data line.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can doing a little modification and perfect, so protection scope of the present invention is when with being as the criterion that claims were defined.
Claims (3)
1, a kind of method for manufacturing thin film transistor array substrate is characterized in that, said method comprising the steps of:
One substrate is provided, and on this substrate deposition the first metal layer and one first photoresist layer, utilize first light shield to form grid, controlling grid scan line, data line, and described grid and controlling grid scan line be electrically connected, described data line is separated by controlling grid scan line and is multistage;
Continue deposition gate insulation layer, semiconductor layer, ohmic contact layer and one second photoresist layer on substrate, utilize second light shield to form source area, drain region, raceway groove, every segment data line top is formed with a contact hole at least;
On substrate, continue the deposit transparent conductive layer at last, utilize the 3rd light shield to form pixel electrode and cross-over electrode, and in described source area, drain region formation source electrode and drain electrode, described pixel electrode links to each other with described drain electrode, described cross-over electrode links to each other with described source electrode, and described cross-over electrode links to each other adjacent two segment data lines by contact hole.
2, method for manufacturing thin film transistor array substrate as claimed in claim 1, it is characterized in that, described second light shield is many gray-level masks, the light shield at corresponding contact hole place has the maximum transmission degree, after mask exposure, second photoresist layer at contact hole place is removed fully, forms contact hole after the etching.
3, method for manufacturing thin film transistor array substrate as claimed in claim 2, it is characterized in that, when utilizing second light shield to form contact hole, the light shield at respective pixel electrode district place has the maximum transmission degree, after mask exposure, second photoresist layer at place, pixel electrode district is removed fully, and the gate insulation layer after the etching on the pixel electrode district, semiconductor layer, ohmic contact layer are removed in the lump.
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| CNA2009100548424A CN101609236A (en) | 2009-07-15 | 2009-07-15 | Method for manufacturing thin film transistor array substrate |
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| CNA2009100548424A CN101609236A (en) | 2009-07-15 | 2009-07-15 | Method for manufacturing thin film transistor array substrate |
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| CN102723334A (en) * | 2012-06-07 | 2012-10-10 | 南京中电熊猫液晶显示科技有限公司 | Metal oxide thin-film transistor substrate, manufacture method thereof and liquid crystal display |
| WO2013007066A1 (en) * | 2011-07-14 | 2013-01-17 | 深圳市华星光电技术有限公司 | Thin film transistor manufacturing method and thin film transistor |
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| CN104966721A (en) * | 2015-07-15 | 2015-10-07 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof, display panel and display apparatus |
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Open date: 20091223 |