CN101625492B - Manufacturing method of array base plate of film transistor - Google Patents
Manufacturing method of array base plate of film transistor Download PDFInfo
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- CN101625492B CN101625492B CN200910056493XA CN200910056493A CN101625492B CN 101625492 B CN101625492 B CN 101625492B CN 200910056493X A CN200910056493X A CN 200910056493XA CN 200910056493 A CN200910056493 A CN 200910056493A CN 101625492 B CN101625492 B CN 101625492B
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Abstract
The invention relates to a manufacturing method of an array base plate of a film transistor. The manufacturing method adopts three paths of photomasks to form photoresist layers with different heights respectively to a first metal layer, a second metal layer and a third metal layer, directly forms the third metal layer on the second metal layer firstly, and then forms a passivating layer by settlement, thus reducing a photomask procedure, being capable of simplifying manufacturing process, reducing cost and improving yield.
Description
Technical field
The present invention relates to a kind of manufacture method of semiconductor element, relate in particular to method for manufacturing thin film transistor array substrate.
Background technology
Present LCD is a main flow with Thin Film Transistor-LCD (TFT LCD) mainly, the general structure of TFT LCD (Thin Film Transistor Liquid Crystal Display) is to have thin-film transistor array base-plate respect to one another and color membrane substrates, wadding is set keeping the box gap between two substrates, and between this box gap filling liquid crystal.
The tft array substrate of volume production needs four-wheel light shield operation mostly at least at present.Fig. 1 is the planimetric map of the prior art tft array substrate of employing four road light shield operations manufacturings, and Fig. 2 is the sectional view along the A-A ' of Fig. 1 and B-B ' line drawing.Shown in seeing figures.1.and.2, the array base palte of prior art is formed with grid line intersected with each other 11 and data line 52 on substrate 1, and grid line 11 forms TFT 91 with the zone of intersection of data line 52.TFT 91 comprises grid 10, source electrode 51 and drains 50.Described grid 10 is formed on the first metal layer that directly contacts with substrate 1, is coated with gate insulation layer 20, semiconductor layer 30, Ohmic contact 40, source electrode 51, drain electrode 50 and passivation layer 60 on grid 10 successively.Grid 10 is connected to grid line 11, and source electrode 51 is connected to data line 52.Form pixel electrode 78 in the pixel region that is limited by grid 10 and data line 52 intersections, described pixel electrode 78 links to each other by the drain electrode 50 of contact hole 70 and TFT 91.
Describe the manufacture method of the tft array substrate of the liquid crystal panel that adopts four road light shield operations in detail hereinafter with reference to Fig. 3 A～3D.
With reference to Fig. 3 A, adopt the first road light shield on substrate, to form first conductive pattern group that comprises grid line 11 (with reference to Fig. 1), grid 10 and grid pad 12.
With reference to Fig. 3 B, earlier deposit gate insulation layer 20, active layer 30 and ohmic contact layer 40 on the substrate of gate pattern successively being formed with, again deposition second conductive metal layer 50 on ohmic contact layer 40.Utilize the second road light shield on gate insulation layer 20, to form the pattern that comprises active layer 30 and ohmic contact layer 40 then, and second conductive pattern layer that comprises data line 52 (with reference to Fig. 1), source electrode 51, drain electrode 50 and data pads 53 (with reference to Fig. 1).
With reference to Fig. 3 C, after second conductive layer pattern forms, then on substrate, use PECVD deposit passivation layer 60, after forming passivation layer,, form contact hole 61 by photoetching and the etching work procedure that adopts the 3rd road light shield.
With reference to Fig. 3 D, after contact hole 61 formed, deposition last layer transparency conducting layer 70 formed the 3rd conductive pattern group that comprises pixel electrode 78, grid pad top electrode 72 and data pads top electrode 73 on passivation layer by the 4th road light shield.
In LCD, because tft array substrate needs semiconductor process and many wheel light shield operations, therefore its manufacturing process is very complicated and manufacturing cost is than higher, and main cause is that one takes turns the light shield operation and comprises such as a plurality of operations such as thin film deposition operation, matting, photo-mask process, etching work procedure, photoresist lift off and inspection operations.
In order to address this problem, hope can provide a kind of manufacture method that can reduce the tft array substrate of light shield operation quantity.
Summary of the invention
Technical matters to be solved by this invention provides and a kind ofly adopts many gray-level masks and reduce the method for manufacturing thin film transistor array substrate of light shield operation quantity.
The present invention solves the problems of the technologies described above the technical scheme that adopts to provide a kind of method for manufacturing thin film transistor array substrate, may further comprise the steps:
One substrate is provided, and form a first metal layer and one first photoresist layer on this substrate, utilize one first light shield on this first metal layer, to form one first photoresist pattern, it has grid line district, gate regions and grid pad area, the photoresist layer that wherein covers this grid line and gate regions has second height, the photoresist layer that covers this grid pad area has first height, and this second height is less than this first height;
With this first photoresist pattern is mask, removes the part the first metal layer, to form first conductive pattern layer that comprises grid line, grid and grid pad bottom electrode;
Remove the second height photoresist layer, simultaneously attenuate the photoresist layer of first height;
On substrate, deposit a gate insulation layer, semi-conductor layer and an ohmic contact layer successively;
Remove the photoresist layer of remaining first height, also the gate insulation layer on it, semiconductor layer and ohmic contact layer are together removed simultaneously, to expose the grid pad bottom electrode that photoresist layer covered that is had first height by this;
On this substrate, continue to deposit successively one second metal level and one second photoresist layer, utilize one second light shield on this second metal level, to form one second photoresist pattern, it has a channel region, a data line and source area and a drain electrode and data pads, grid pad area, the photoresist layer that covers this channel region has the 4th height, the photoresist layer that covers this data line, source area, drain region, data pads district and grid pad area has the 3rd height, and the 3rd height＞the 4th height;
With this second photoresist pattern is mask, after removal does not have second conductive metal layer, semiconductor layer and the ohmic contact layer of photoresist part, removal has the photoresist pattern of the 4th height, attenuate has the photoresist pattern of the 3rd height simultaneously, in the process etching, to form source electrode, drain electrode, raceway groove and data line bottom electrode and data pads bottom electrode;
On this substrate, continue deposition one transparency conducting layer and one the 3rd photoresist layer, utilize one the 3rd road light shield to form one the 3rd photoresist pattern, the photoresist layer of cover data pad area, grid pad area and pixel region has the 6th height, the photoresist layer of cover data line and source area, drain region has the 5th height, other regional no third photoresist layer, and the 5th height is less than the 6th height;
With the 3rd photoresist pattern is mask, forms pixel electrode, source electrode top electrode, drain electrode top electrode and data line top electrode and data pads, grid pad top electrode;
Remove the 5th height the 3rd photoresist layer, simultaneously attenuate the 3rd photoresist layer of the 6th height, continue deposit passivation layer, remove the 3rd photoresist layer of remaining the 6th height, also the passivation layer on it is together removed simultaneously, to expose the pixel electrode that photoresist layer covered, data pads and the grid pad top electrode that is had the 6th height by this.
In the said method, described first light shield, second light shield and the 3rd light shield all are many gray-level masks.
In the said method, the method for described attenuate photoresist layer segment thickness comprises the plasma ashing operation.
In the said method, the method for described removal remaining photoresist layer comprises stripping process.
The manufacture method that the present invention contrasts the thin-film transistor array base-plate of existing four road light shield operations has following beneficial effect: the present invention adopts three road light shields to form the photoresist layer with differing heights respectively to the first metal layer, second metal level and the 3rd metal level, and on second metal level, directly form the 3rd metal level earlier, deposit passivation layer then, thereby reduced the light shield operation one, simplify manufacture process, reduce cost, improve output.
Description of drawings
Fig. 1 is the planimetric map that adopts the tft array substrate of prior art four road light shield operations.
Fig. 2 is the sectional view along the A-A ' of Fig. 1 and B-B ' line drawing.
Fig. 3 A～3D is the making flow process cut-open view of the tft array substrate of prior art.
The floor map of Fig. 4 A first road light shield operation of the present invention.
Fig. 4 B～4D is the flow process cut-open view of the present invention's first road light shield operation and subsequent handling.
Fig. 5 A is the floor map of the second road light shield operation of the present invention.
Fig. 5 B is the present invention's second road light shield process flow cut-open view.
Fig. 6 is the floor map of the 3rd road light shield operation of the present invention.
Fig. 7 A～7C is the flow process cut-open view of the 3rd road light shield operation of the present invention and subsequent handling.
Embodiment
The invention will be further described below in conjunction with accompanying drawing and exemplary embodiments.
The floor map of Fig. 4 A first road light shield operation of the present invention, Fig. 4 B～4D is the flow process cut-open view of the present invention's first road light shield operation and subsequent handling, Fig. 4 B～4D is the sectional view along C-C among Fig. 4 A and D-D line.
Please refer to Fig. 4 A, adopt the first road light shield operation on substrate 1, to form first conductive pattern layer with grid line 101, grid 100 and grid pad bottom electrode 102.Idiographic flow shown in figure Fig. 4 B～4D, at first, shown in Fig. 4 B, one substrate 1 is provided, and on substrate 1, form the first metal layer by method such as sputter or other depositions, then, utilize first light shield (figure does not show) on the first metal layer, to form the first photoresist pattern.The first road light shield is many gray-level masks (HTM), and it has the light shield substrate that is made of transparent material, is formed on lightproof area and half lightproof area on the light shield substrate.After adopting the first road light shield exposure imaging, on photoresist, has predetermined stair step patterns respectively corresponding to the shading light part of first light shield and the position formation of half shading light part.The photoresist layer 805 that wherein covers this grid line and gate regions (with reference to the position that forms grid line 101 and grid 100 shown in Fig. 4 A) has second height, and the photoresist layer 806 of covering gate pad area (with reference to the position that forms grid pad bottom electrode 102 shown in Fig. 4 A) has first height, and second height is less than this first height.Photoresist both can be the eurymeric photoresist, can be negative photoresist also, can adjust the position in each different shading amounts zone of many gray-level masks in processing procedure according to the material of photoresist.
Then, be mask with the first photoresist pattern, remove the part the first metal layer, to form first conductive pattern layer (as Fig. 4 A) that comprises grid line 101, grid 102 and grid pad bottom electrode 102.
Afterwards, remove the segment thickness of this first photoresist pattern, thereby remove photoresist pattern 805, and reduce photoresist pattern 806, to expose grid line 101 and the grid 100 that is covered by photoresist layer 805 with first height with second height.The method of removing the segment thickness of this first photoresist pattern for example can adopt oxygen plasma to carry out the ashing operation.
Afterwards, shown in Fig. 4 C, on substrate, deposit a gate insulation layer 200, semi-conductor layer 300 and an ohmic contact layer 400 successively, remove remaining first photoresist layer 806 by stripping process, gate insulation layer 200, semiconductor layer 300 and the ohmic contact layer 400 that also will be deposited on simultaneously on the residue photoresist 806 are removed, to expose the grid pad bottom electrode 102 that it covers down, promptly grid pad bottom electrode 102 runs through gate insulation layer 200, semiconductor layer 300 and ohmic contact layer 400.
Fig. 5 A is the floor map of the second road light shield operation of the present invention, and Fig. 5 B is the present invention's second road light shield process flow cut-open view, and Fig. 5 B is the sectional view along E-E among Fig. 5 A and F-F line.
Please refer to Fig. 5 A and 5B, sputter second metal level 500 on first conductive layer that forms before please, to cover these grid lines, grid, grid pad etc., second metal level 500 and grid pad bottom electrode 102 directly electrically contact.Pass through the photo-mask process and the etching work procedure of the second road HTM light shield thereafter, this metal level 500 and semiconductor layer 300 are patterned into predetermined structure, the shading amount that this second road light shield has the light shield substrate that is made of transparent material, be formed on the lightproof area of light shield substrate and be formed at the light shield substrate is 1/2nd zone, thereby adopts behind the second road light shield exposure imaging this photoresist corresponding respectively to the second light shield shading light part and 1/2nd exposed portion burn-outs partly form the photoresist pattern with predetermined step.Make the photoresist that covers raceway groove place 400 have the 4th height (figure does not show), on cover data line bottom electrode 502, data pads bottom electrode 503, drain electrode bottom electrode 500 and the source electrode bottom electrode 501 and the photoresist 800 of gate pads have the 3rd height (figure does not show), all the other positions do not have photoresist, and the 3rd height is greater than the 4th height.
After getting rid of second conductive metal layer and semiconductor layer and ohmic contact layer that does not have the photoresist part by the etching first time then, thereby adopt oxygen gas plasma to carry out the ashing operation and remove photoresist pattern, and reduce photoresist pattern with the 3rd height with the 4th height.Through etching for the second time, second conductive metal layer 500 and the ohmic contact layer 400 at raceway groove place 400 are got rid of.Thereby stay second metal level 504 on data line bottom electrode 502, data pads bottom electrode 503, drain electrode bottom electrode 500 and source electrode bottom electrode 501, the grid pad 102.
Fig. 6 is the floor map of the 3rd road light shield operation of the present invention, and Fig. 7 A～7C is the flow process cut-open view of the 3rd road light shield operation of the present invention and subsequent handling, and Fig. 7 A～7C is the sectional view along G-G among Fig. 6 and H-H line.
Shown in Fig. 7 A, adopt and on the second conductive layer array base palte, directly coat transparency conducting layer such as sputtering method or other deposition processs.
This transparency conducting layer is formed by tin indium oxide (ITO), tin oxide (TO), tin indium oxide zinc (ITZO) or indium zinc oxide (IZO).
Behind the 3rd road HTM light shield, form the photoresist pattern 808 of the 6th height at grid pad and data pads place, data line top electrode, drain electrode top electrode 700 and source electrode top electrode 703 transparent conductive patterns form the 5th height photoresist pattern 807, the photoresist pattern 809 that forms on the pixel electrode 708 also is the 6th height, other places do not have photoresist, and the 5th height is less than the 6th height, with reference to Fig. 7 A.By etching, formation pixel electrode 708, the data line top electrode that extends to data pads top electrode 702, drain electrode top electrode 700 and source electrode top electrode 703 transparent conductive patterns and data pads top electrode 702, grid pad top electrode 701.Remove the 5th height photoresist 807 by ashing, reduce the 6th height photoresist pattern 808,809 simultaneously, as Fig. 7 B.
At last shown in Fig. 7 C; be formed with deposit passivation layer 600 on the array base palte of transparent conductive patterns; by stripping process the photoresist pattern 808 on grid pad 701, the data pads top electrode 702 is peeled off afterwards; photoresist glue pattern 809 on the pixel electrode 708 is peeled off; the passivation layer that also just will be deposited on these photoresists has simultaneously also peeled off together; except grid pad, data pads and pixel electrode, other places particularly semiconductor layer at raceway groove place are well protected thus.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can doing a little modification and perfect, so protection scope of the present invention is when with being as the criterion that claims were defined.
Claims (4)
1. a method for manufacturing thin film transistor array substrate is characterized in that, said method comprising the steps of:
One substrate is provided, and form a first metal layer and one first photoresist layer on this substrate, utilize one first light shield on this first metal layer, to form one first photoresist pattern, it has grid line district, gate regions and grid pad area, the photoresist layer that wherein covers this grid line and gate regions has second height, the photoresist layer that covers this grid pad area has first height, and this second height is less than this first height;
With this first photoresist pattern is mask, removes the part the first metal layer, to form first conductive pattern layer that comprises grid line, grid and grid pad bottom electrode;
Remove the second height photoresist layer, simultaneously attenuate the photoresist layer of first height;
On substrate, deposit a gate insulation layer, semi-conductor layer and an ohmic contact layer successively;
Remove the photoresist layer of remaining first height, also the gate insulation layer on it, semiconductor layer and ohmic contact layer are together removed simultaneously, to expose the grid pad bottom electrode that photoresist layer covered that is had first height by this;
On this substrate, continue to deposit successively one second metal level and one second photoresist layer, utilize one second light shield on this second metal level, to form one second photoresist pattern, it has a channel region, a data line and source area and a drain electrode and data pads, grid pad area, the photoresist layer that covers this channel region has the 4th height, the photoresist layer that covers this data line, source area, drain region, data pads district and grid pad area has the 3rd height, and the 3rd height＞the 4th height;
With this second photoresist pattern is mask, after removal does not have second conductive metal layer, semiconductor layer and the ohmic contact layer of photoresist part, removal has the photoresist pattern of the 4th height, attenuate has the photoresist pattern of the 3rd height simultaneously, in the process etching, to form source electrode, drain electrode, raceway groove and data line bottom electrode and data pads bottom electrode;
On this substrate, continue deposition one transparency conducting layer and one the 3rd photoresist layer, utilize one the 3rd road light shield to form one the 3rd photoresist pattern, the photoresist layer of cover data pad area, grid pad area and pixel region has the 6th height, the photoresist layer of cover data line and source area, drain region has the 5th height, other regional no third photoresist layer, and the 5th height is less than the 6th height;
With the 3rd photoresist pattern is mask, forms pixel electrode, source electrode top electrode, drain electrode top electrode and data line top electrode and data pads top electrode, grid pad top electrode;
Remove the 5th height the 3rd photoresist layer, simultaneously attenuate the 3rd photoresist layer of the 6th height, continue deposit passivation layer, remove the 3rd photoresist layer of remaining the 6th height, also the passivation layer on it is together removed simultaneously, to expose the pixel electrode that photoresist layer covered, data pads and the grid pad top electrode that is had the 6th height by this.
2. method for manufacturing thin film transistor array substrate as claimed in claim 1 is characterized in that, described first light shield, second light shield and the 3rd light shield all are many gray-level masks.
3. method for manufacturing thin film transistor array substrate as claimed in claim 1 is characterized in that, the method for described attenuate photoresist layer segment thickness comprises the plasma ashing operation.
4. method for manufacturing thin film transistor array substrate as claimed in claim 1 is characterized in that the method for described removal remaining photoresist layer comprises stripping process.
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| CN200910056493XA CN101625492B (en) | 2009-08-14 | 2009-08-14 | Manufacturing method of array base plate of film transistor |
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| CN200910056493XA CN101625492B (en) | 2009-08-14 | 2009-08-14 | Manufacturing method of array base plate of film transistor |
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| CN101625492B true CN101625492B (en) | 2011-03-23 |
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| CN102779783B (en) * | 2012-06-04 | 2014-09-17 | 北京京东方光电科技有限公司 | Pixel structure, as well as manufacturing method and display device thereof |
| CN107068615B (en) * | 2017-05-23 | 2019-09-17 | 深圳市华星光电技术有限公司 | The production method of TFT substrate |
| CN109638079A (en) * | 2018-11-30 | 2019-04-16 | 武汉华星光电技术有限公司 | A kind of array substrate and display panel |
| CN109935516B (en) * | 2019-04-01 | 2021-01-22 | 京东方科技集团股份有限公司 | Array substrate, preparation method thereof and display device |
| CN113917784A (en) * | 2021-10-11 | 2022-01-11 | 桂林理工大学 | Top gate structure all-solid-state memory transistor multivariable mask plate based on overlay technology |
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Effective date of registration: 20110617 Address after: 210038 Nanjing economic and Technological Development Zone, Jiangsu Province, Hengyi Road, No. 9, No. Patentee after: Nanjing CEC Panda LCD Technology Co., Ltd. Address before: 200233, Shanghai, Yishan Road, No. 757, third floor, Xuhui District Patentee before: SVA (Group) Co., Ltd. |