CN101645418A - Method for manufacturing basal plate of film transistor array - Google Patents
Method for manufacturing basal plate of film transistor array Download PDFInfo
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- CN101645418A CN101645418A CN200910195231A CN200910195231A CN101645418A CN 101645418 A CN101645418 A CN 101645418A CN 200910195231 A CN200910195231 A CN 200910195231A CN 200910195231 A CN200910195231 A CN 200910195231A CN 101645418 A CN101645418 A CN 101645418A
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Abstract
The invention relates to a method for manufacturing a basal plate of a film transistor array, which comprises the following steps: after a grid electrode and an insulation layer of the grid electrodeare formed, a pixel electrode is firstly formed, a semiconductor layer and a drain electrode metal layer are secondly formed by using different heights of photo-resist layers and a stripping method, and a film of a passivation layer is formed at last. A pixel electrode does not need to penetrate the film of the passivation layer to be connected with the drain electrode, thus, the invention saves alight shield procedure, simplifies the production process, reduces the cost and increases the output.
Description
Technical field
The present invention relates to a kind of manufacture method of semiconductor element, relate in particular to method for manufacturing thin film transistor array substrate.
Background technology
Present LCD is a main flow with Thin Film Transistor-LCD (TFT LCD) mainly, the general structure of TFT LCD (Thin Film Transistor Liquid Crystal Display) is to have thin-film transistor array base-plate respect to one another and color membrane substrates, wadding is set keeping the box gap between two substrates, and between this box gap filling liquid crystal.
The tft array substrate of volume production needs four-wheel light shield operation mostly at least at present.Fig. 1 is the plane graph of the prior art tft array substrate of employing four road light shield operations manufacturings, and Fig. 2 is the sectional view along the A-A ' of Fig. 1 and B-B ' line drawing.Shown in seeing figures.1.and.2, the array base palte of prior art is formed with grid line intersected with each other 11 and data wire 52 on substrate 1, and grid line 11 forms TFT 91 with the zone of intersection of data wire 52.TFT 91 comprises grid 10, source electrode 51 and drains 50.Described grid 10 is formed on the first metal layer that directly contacts with substrate 1, is coated with gate insulation layer 20, semiconductor layer 30, ohmic contact 40, source electrode 51, drain electrode 50 and passivation layer 60 on grid 10 successively.Grid 10 is connected to grid line 11, and source electrode 51 is connected to data wire 52.Form pixel electrode 78 in the pixel region that is limited by grid 10 and data wire 52 intersections, described pixel electrode 78 links to each other by the drain electrode 50 of contact hole 70 and TFT 91.
Describe the manufacture method of the tft array substrate of the liquid crystal panel that adopts four road light shield operations in detail hereinafter with reference to Fig. 3 A～3D.
With reference to Fig. 3 A, adopt the first road light shield on substrate, to form first conductive pattern group that comprises grid line 11 (with reference to Fig. 1), grid 10 and grid pad 12.
With reference to Fig. 3 B, earlier deposit gate insulation layer 20, active layer 30 and ohmic contact layer 40 on the substrate of gate pattern successively being formed with, again deposition second conductive metal layer 50 on ohmic contact layer 40.Utilize the second road light shield on gate insulation layer 20, to form the pattern that comprises active layer 30 and ohmic contact layer 40 then, and second conductive pattern layer that comprises data wire 52 (with reference to Fig. 1), source electrode 51, drain electrode 50 and data pads 53 (with reference to Fig. 1).
With reference to Fig. 3 C, after second conductive layer pattern forms, then on substrate, use PECVD deposit passivation layer 60, after forming passivation layer,, form contact hole 61 by photoetching and the etching work procedure that adopts the 3rd road light shield.
With reference to Fig. 3 D, after contact hole 61 formed, deposition last layer transparency conducting layer 70 formed the 3rd conductive pattern group that comprises pixel electrode 78, grid pad top electrode 72 and data pads top electrode 73 on passivation layer by the 4th road light shield.
In LCD, because tft array substrate needs semiconductor process and many wheel light shield operations, therefore its manufacturing process is very complicated and manufacturing cost is than higher, and main cause is that one takes turns the light shield operation and comprises such as a plurality of operations such as thin film deposition operation, matting, photo-mask process, etching work procedure, photoresist lift off and inspection operations.
In order to address this problem, hope can provide a kind of manufacture method that can reduce the tft array substrate of light shield operation quantity.
Summary of the invention
Technical problem to be solved by this invention provides a kind of method for manufacturing thin film transistor array substrate of employing 3 road light shield operation quantity.
The present invention solves the problems of the technologies described above the technical scheme that adopts to provide a kind of method for manufacturing thin film transistor array substrate, may further comprise the steps:
Substrate is provided; Form the first metal layer and first photoresist layer on this substrate, utilize the first road photoetching to form grid, grid pad; Form gate insulator on this substrate, to cover this grid;
Form the transparency conducting layer and second photoresist layer on this gate insulator, utilize the second road photoetching to form pixel electrode, source electrode bottom electrode and data pads bottom electrode, this pixel electrode, source electrode bottom electrode are positioned at the grid both sides, keep second photoresist layer on pixel electrode, the source electrode bottom electrode, this second photoresist layer forms raceway groove above grid;
Continue to form semiconductor layer on this substrate, peel off second photoresist layer and on semiconductor layer, this raceway groove place forms semiconductor layer, exposes this pixel electrode, source electrode bottom electrode;
Continue to form the 3rd metal level and the 3rd photoresist layer on this substrate, utilize the 3rd road photoetching to form drain electrode, source electrode top electrode and data pads top electrode, this drain electrode and this pixel electrode contact, this source electrode top electrode and this source electrode bottom electrode contact, and wherein this grid, this drain electrode, this semiconductor layer, this source electrode bottom electrode and this source electrode top electrode constitute thin-film transistor; Form the passivation layer film on this pixel electrode, this thin-film transistor.
In the said method, described continuation forms semiconductor layer and comprise deposited amorphous silicon layer and ohmic contact layer on this substrate.
In the said method, described formation passivation layer film comprises: keep this pixel electrode, this thin-film transistor, this grid pad and this data pads the 3rd photoresist layer in all the other zones in addition; Continue to form passivation layer on this substrate, peel off the 3rd photoresist layer and on passivation layer, form the passivation layer film on this pixel electrode, this thin-film transistor, expose the 3rd metal level in all the other zones, wet the 3rd metal level of removing all the other zones of carving is carved, and does to carve and removes all the other regional amorphous silicon semiconductor layers.
The manufacture method that the present invention contrasts the thin-film transistor array base-plate of existing four road light shield operations has following beneficial effect: after manufacture method provided by the invention forms grid and gate insulator, form pixel electrode earlier, utilize different photoresist layer height and stripping means to form semiconductor layer then, form the passivation layer film at last, because pixel electrode does not need to run through the passivation layer film and drain electrode is wanted to connect, thereby has reduced the light shield operation one, simplifies manufacture process, reduce cost, improve output.
Description of drawings
Fig. 1 is the plane graph that adopts the tft array substrate of prior art four road light shield operations.
Fig. 2 is the sectional view along the A-A ' of Fig. 1 and B-B ' line drawing.
Fig. 3 A～3D is the making flow process cutaway view of the tft array substrate of prior art.
The floor map of Fig. 4 A first road light shield operation of the present invention.
Fig. 4 B～4D is the flow process cutaway view of the present invention's first road light shield operation and subsequent handling.
Fig. 5 A is the floor map of the second road light shield operation of the present invention.
Fig. 5 B～5D is the present invention's second road light shield process flow cutaway view.
Fig. 6 is the floor map of the 3rd road light shield operation of the present invention.
Fig. 7 A～7C is the flow process cutaway view of the 3rd road light shield operation of the present invention and subsequent handling.
Embodiment
The invention will be further described below in conjunction with accompanying drawing and exemplary embodiments.
The floor map of Fig. 4 A first road light shield operation of the present invention, Fig. 4 B～4D is the flow process cutaway view of the present invention's first road light shield operation and subsequent handling, wherein, Fig. 4 B～4D is the profile along C-C among Fig. 4 A and D-D line.
Please refer to Fig. 4 A, adopt the first road light shield operation on substrate 1, to form first conductive pattern layer with grid line 101, grid 100 and grid pad bottom electrode 102.Idiographic flow shown in figure Fig. 4 B～4D, at first, shown in Fig. 4 B, one substrate 1 is provided, and on substrate 1, form the first metal layer by method such as sputter or other depositions, then, utilize first light shield (figure does not show) on the first metal layer, to form the first photoresist pattern.The first road light shield is many gray-level masks (HTM), and it has the light shield substrate that is made of transparent material, is formed on lightproof area and half lightproof area on the light shield substrate.After adopting the first road light shield exposure imaging, on photoresist, has predetermined stair step patterns respectively corresponding to the shading light part of first light shield and the position formation of half shading light part.The photoresist layer 805 that wherein covers this grid line and gate regions (with reference to the position that forms grid line 101 and grid 100 shown in Fig. 4 A) has second height, and the photoresist layer 806 of covering gate pad area (with reference to the position that forms grid pad bottom electrode 102 shown in Fig. 4 A) has first height, and second height is less than this first height.Photoresist both can be the eurymeric photoresist, can be negative photoresist also, can adjust the position in each different shading amounts zone of many gray-level masks in processing procedure according to the material of photoresist.
Then, be mask with the first photoresist pattern, remove the part the first metal layer, to form first conductive pattern layer (as Fig. 4 A) that comprises grid line 101, grid 102 and grid pad bottom electrode 102.
Afterwards, remove the segment thickness of this first photoresist pattern, thereby remove photoresist pattern 805, and reduce photoresist pattern 806, to expose grid line 101 and the grid 100 that is covered by photoresist layer 805 with first height with second height.The method of removing the segment thickness of this first photoresist pattern for example can adopt oxygen plasma to carry out the ashing operation.
Afterwards, shown in Fig. 4 C, on substrate, continue deposition one gate insulation layer 200, remove remaining first photoresist layer 806 by stripping process, the gate insulation layer 200 that also will be deposited on simultaneously on the residue photoresist 806 is removed, to expose the grid pad bottom electrode 102 that it covers down, shown in Fig. 4 D.
Fig. 5 A is the floor map of the second road light shield operation of the present invention, and Fig. 5 B～5D is the present invention's second road light shield process flow cutaway view, and wherein Fig. 5 B～5D is the profile along E-E among Fig. 5 A and F-F line.
Please refer to Fig. 5 A and Fig. 5 B, the sputter sputter transparency conducting layer and second photoresist layer 800 on first conductive layer that forms before.This transparency conducting layer is formed by tin indium oxide (ITO), tin oxide (TO), tin indium oxide zinc (ITZO) or indium zinc oxide (IZO).Adopt the photo-mask process and the etching work procedure of common light shield then, form the transparent conductive patterns of pixel electrode 708, grid pad top electrode 701, data pads electrode 702, drain electrode bottom electrode 700, source electrode bottom electrode 703 and data wire bottom electrode 704.Pixel electrode 708 and source electrode bottom electrode 703 are positioned at the both sides of grid 100, and second photoresist layer 800 forms raceway groove above grid 100.
Afterwards, shown in Fig. 5 C, before second photoresist layer 800 is peeled off, depositing semiconductor layers 300, semiconductor layer 300 can be amorphous silicon layer and ohmic contact layer, makes the raceway groove place deposit semiconductor layer.Peel off second photoresist layer 800 then, together peel off together with the semiconductor layer on it.Like this, on source drain region, pixel region, grid pad and data pads, all there is not semiconductor layer, shown in Fig. 5 D.
Fig. 6 is the floor map of the 3rd road light shield operation of the present invention, and Fig. 7 A～7C is the flow process cutaway view of the 3rd road light shield operation of the present invention and subsequent handling, and wherein Fig. 7 A～7C is the profile along G-G among Fig. 6 and H-H line.
See also Fig. 6 and Fig. 7 A, sputter the 3rd metal level (data metal layer) and the 3rd photoresist layer on the substrate of Fig. 5 D, by behind the 3rd road HTM light shield, do not have photoresist at pixel electrode, raceway groove place then, gate pads and data pads periphery do not have photoresist yet; Source-drain electrode place the 3rd photoresist layer 801 is thinner, is the 4th height photoresist; Grid pad and data pads and other local photoresists 803,802 are the 3rd height, and the 3rd height photoresist is thicker than the 4th height photoresist.Remove the 3rd electric metal layer that does not have the 3rd photoresist layer to cover by wet the quarter, form drain electrode 500, source electrode top electrode 501 and data wire top electrode 502.Then, remove photoresist pattern thereby adopt oxygen gas plasma to carry out the ashing operation, and reduce photoresist pattern, expose the 3rd conductive layer metal at source-drain electrode place so again with first height with second height.
Afterwards; shown in Fig. 7 B; deposit passivation layer on aforesaid substrate (PA) 600; and peel off the passivation layer that remaining the 3rd photoresist layer is extremely gone up; form the passivation layer film; like this, all protected by PA near pixel region, source-drain electrode, raceway groove place and the pad, all the other zones then do not have the passivation layer film.In order to reduce parasitic capacitance, the present invention can also append once wet the quarter and dried the quarter after above-mentioned operation, to remove unnecessary the 3rd metal level and semiconductor layer.Because the present invention does not then have the passivation layer film by all the other zones of the substrate that above-mentioned operation is made, promptly exposes the 3rd metal level under grid pad, data pads and the 3rd photoresist layer 802, as Fig. 7 B.Carve by wet like this, remove the 3rd metal level that exposes.At once fall the 3rd metal level on grid pad top electrode 701, grid pad bottom electrode 102, the data pads 702, make data-signal be transferred in data wire bottom electrode 704 and the data wire top electrode 502 by data pads 702.Simultaneously, after the 3rd metal level under the photoresist 802 is carved, expose following semiconductor layer, etch away this part semiconductor layer by doing again, form pattern at last as Fig. 7 C.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can doing a little modification and perfect, so protection scope of the present invention is when with being as the criterion that claims were defined.
Claims (3)
1. the manufacture method of a thin-film transistor array base-plate comprises:
Substrate is provided;
Form the first metal layer and first photoresist layer on this substrate, utilize the first road photoetching to form grid, grid pad;
Form gate insulator on this substrate, to cover this grid;
Form the transparency conducting layer and second photoresist layer on this gate insulator, utilize the second road photoetching to form pixel electrode, source electrode bottom electrode and data pads bottom electrode, this pixel electrode, source electrode bottom electrode are positioned at the grid both sides, keep second photoresist layer on pixel electrode, the source electrode bottom electrode, this second photoresist layer forms raceway groove above grid;
Continue to form semiconductor layer on this substrate, peel off second photoresist layer and on semiconductor layer, this raceway groove place forms semiconductor layer, exposes this pixel electrode, source electrode bottom electrode;
Continue to form the 3rd metal level and the 3rd photoresist layer on this substrate, utilize the 3rd road photoetching to form drain electrode, source electrode top electrode and data pads top electrode, this drain electrode and this pixel electrode contact, this source electrode top electrode and this source electrode bottom electrode contact, and wherein this grid, this drain electrode, this semiconductor layer, this source electrode bottom electrode and this source electrode top electrode constitute thin-film transistor;
Form the passivation layer film on this pixel electrode, this thin-film transistor.
2. method for manufacturing thin film transistor array substrate as claimed in claim 1 is characterized in that, described continuation forms semiconductor layer and comprise deposited amorphous silicon layer and ohmic contact layer on this substrate.
3. method for manufacturing thin film transistor array substrate as claimed in claim 1 is characterized in that, described formation passivation layer film comprises:
Keep this pixel electrode, this thin-film transistor, this grid pad and this data pads the 3rd photoresist layer in all the other zones in addition;
Continue to form passivation layer on this substrate, peel off the 3rd photoresist layer and on passivation layer, form the passivation layer film on this pixel electrode, this thin-film transistor, expose the 3rd metal level in all the other zones, wet the 3rd metal level of removing all the other zones of carving is carved, and does to carve and removes all the other regional amorphous silicon semiconductor layers.
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| Application Number | Priority Date | Filing Date | Title |
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| CN200910195231A CN101645418A (en) | 2009-09-07 | 2009-09-07 | Method for manufacturing basal plate of film transistor array |
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| CN200910195231A CN101645418A (en) | 2009-09-07 | 2009-09-07 | Method for manufacturing basal plate of film transistor array |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106229260A (en) * | 2016-08-31 | 2016-12-14 | 深圳市华星光电技术有限公司 | A kind of thin film transistor (TFT) and manufacture method thereof |
| CN108646487A (en) * | 2018-05-15 | 2018-10-12 | 深圳市华星光电技术有限公司 | The production method and FFS type array substrates of FFS type array substrates |
| CN108735787A (en) * | 2018-05-29 | 2018-11-02 | 武汉华星光电半导体显示技术有限公司 | Display panel and preparation method thereof |
-
2009
- 2009-09-07 CN CN200910195231A patent/CN101645418A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106229260A (en) * | 2016-08-31 | 2016-12-14 | 深圳市华星光电技术有限公司 | A kind of thin film transistor (TFT) and manufacture method thereof |
| WO2018040475A1 (en) * | 2016-08-31 | 2018-03-08 | 深圳市华星光电技术有限公司 | Thin film transistor and manufacturing method therefor |
| US10367066B2 (en) | 2016-08-31 | 2019-07-30 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Thin film transistor and method for manufacturing the same |
| CN108646487A (en) * | 2018-05-15 | 2018-10-12 | 深圳市华星光电技术有限公司 | The production method and FFS type array substrates of FFS type array substrates |
| CN108646487B (en) * | 2018-05-15 | 2020-12-25 | Tcl华星光电技术有限公司 | FFS (fringe field switching) type array substrate and manufacturing method thereof |
| CN108735787A (en) * | 2018-05-29 | 2018-11-02 | 武汉华星光电半导体显示技术有限公司 | Display panel and preparation method thereof |
| CN108735787B (en) * | 2018-05-29 | 2020-11-06 | 武汉华星光电半导体显示技术有限公司 | Display panel and manufacturing method thereof |
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Open date: 20100210 |