CN101236932A - Thin film transistor array base plate making method - Google Patents
Thin film transistor array base plate making method Download PDFInfo
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- CN101236932A CN101236932A CNA2008100343858A CN200810034385A CN101236932A CN 101236932 A CN101236932 A CN 101236932A CN A2008100343858 A CNA2008100343858 A CN A2008100343858A CN 200810034385 A CN200810034385 A CN 200810034385A CN 101236932 A CN101236932 A CN 101236932A
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Abstract
The invention relates to a method for manufacturing a thin film transistor array substrate. In the method, a gate insulation layer deposited on a storage electrode is removed by a stripping technology. The manufacturing method of the invention can decrease the distance between a storage capacitor electrode and a pixel electrode thereby improving a storage capacitance value effectively. At the prerequisite that the storage capacitance value is fulfilled, the width of a storage capacitor line can be reduced and the aperture ratio of pixel can be improved.
Description
Technical field
The present invention relates to a kind of manufacture method of thin-film transistor array base-plate, relate in particular to a kind of method for manufacturing thin film transistor array substrate that can effectively improve storage capacitance.
Background technology
Present LCD is a main flow with Thin Film Transistor-LCD (TFT LCD) mainly, the general structure of TFT LCD (ThinFilm Transistor Liquid Crystal Display) is to have thin-film transistor array base-plate respect to one another and color membrane substrates, wadding is set keeping the box gap between two substrates, and between this box gap filling liquid crystal.Fig. 1 is the dot structure figure on the existing array base palte, and Fig. 2 is A-A ' sectional view of Fig. 1.Shown in seeing figures.1.and.2, the array base palte of prior art comprises a substrate 10, is formed with grid line intersected with each other 12 and data wire 14 on the substrate 10, and grid line 12 forms TFT 13 with the infall of data wire 14.TFT 13 comprises grid 112, source electrode 141 and drains 142.Described grid 112 is formed on the first metal layer that directly contacts with substrate 10, is coated with gate insulation layer 121, semiconductor layer 131, ohmic contact 132, source electrode 141, drain electrode 142 and passivation layer 122 on grid 112 successively.Grid 112 is connected to gate line 12, and source electrode 141 is connected to data wire 14.Form pixel electrode 15 in the pixel region that is limited by grid 112 and data wire 14 intersections, described pixel electrode 15 links to each other by the drain electrode 142 of contact hole 123 and TFT 13.
The plane-parallel capacitor that thin-film transistor array base-plate and color membrane substrates form, its capacitance size is about 0.1pF, when can't remaining to voltage next time the frame update data again, this electric capacity (, needs to keep the time of about 16ms) with the frame updating frequency of general 60Hz.So, variation has taken place in pixel voltage, and shown GTG will be incorrect.Therefore generally in the design of array base palte, can add a storage capacitance Cs again, so that when allowing charged pixel voltage can remain to next time frame update.With reference to figure 2, also be formed with storage capacitance line 111 on the first metal layer, on storage capacitance line 111, be coated with gate insulation layer 121, passivation layer 122 and pixel electrode 15 successively.Storage capacitance line 111 is as a utmost point of storage capacitance, and itself and grid complete simultaneously.Because storage capacitance line 111 is light tight zone, therefore reduced aperture ratio of pixels.Aperture opening ratio is exactly the permeable effective coverage of light ratio simply.When light emitted via backlight, not all light can both pass panel, as signal lead, and storage capacitance, and TFT itself or the like.These places are except incomplete printing opacity, owing to be not subjected to the control of voltage through these local light yet, and can't show correct GTG, thus all need utilize black matrix (black matrix) to be covered, in order to avoid interfere with the correct brightness of other transmission region.Effective transmission region after covering just is referred to as aperture opening ratio with the ratio of entire area.Aperture opening ratio is the most important factor of decision LCD brightness, therefore in the design of TFT LCD, improve aperture opening ratio as far as possible.As long as improve aperture opening ratio, just brightness can be increased, and the brightness of backlight can be reduced simultaneously, save energy and reduce cost.
According to storage capacitance Cs computing formula:
Cs＝ε
0ε
rS/d
In the formula, ε
0Be permittivity of vacuum, equal 8.85e-12F/m;
ε
rBe relative dielectric constant;
S be between two battery lead plates over against area;
D is the vertical range between two battery lead plates;
Therefore, in order to keep certain storage capacitance value, improve pixel aperture ratio simultaneously, the distance that reduces between storage capacitor electrode and the pixel electrode is a kind of effective method.
In order to address this problem, hope can work out a kind of manufacture method that can effectively improve the thin-film transistor array base-plate of storage capacitance.
Summary of the invention
Technical problem to be solved by this invention provides a kind of manufacture method that can effectively improve the thin-film transistor array base-plate of storage capacitance.
The present invention solves the problems of the technologies described above the manufacture method that the technical scheme that adopts provides a kind of thin-film transistor array base-plate may further comprise the steps: a substrate is provided, and on this substrate, forming a first metal layer, it has gate regions and storage capacitor electrode district; Utilize a semi-transparent mask on this first metal layer, to form one first photoresist pattern, the photoresist layer that wherein covers this gate regions has second height, the photoresist layer that covers this storage capacitor electrode district has first height, and this second height is less than this first height; With this first photoresist pattern is mask, removes the part the first metal layer, to form first conductive pattern layer that comprises grid and storage capacitor electrode; Remove the segment thickness of this first photoresist pattern, to expose the grid that photoresist layer covered that is had second height by this; On substrate, deposit a gate insulation layer, semi-conductor layer and an ohmic contact layer successively; On substrate, continue deposition one second metal level, form source electrode, drain electrode and semiconductor figure respectively, make the TFT switch element; Remove gate insulation layer and remaining this first photoresist pattern on this storage capacitor electrode, to expose the storage capacitor electrode that photoresist layer covered that is had first height by this; Deposition one passivation layer forms contact hole on source, drain electrode and storage capacitor electrode; Sputter layer of transparent film on passivation layer forms pixel electrode at last.
In the said method, the method for removing the segment thickness of this first photoresist pattern comprises the plasma ashing operation.
In the said method, the method that forms source electrode, drain electrode and semiconductor figure comprises the coating photoresist, uses the exposure of GTM technology, develops etching and stripping process.
In the said method, gate insulation layer and remaining this first photoresist pattern method of removing on the storage capacitor electrode comprise lift-off technology technology.
Therefore, the manufacture method of thin-film transistor array base-plate of the present invention, compare with present manufacturing method of array base plate, when having made storage capacitor electrode, keep the photoresist on it, by the time after having made semiconductor layer, utilize lift-off technology, the photoresist that keeps on the storage electrode is removed, also the gate insulation layer of deposition on it has been removed simultaneously, therefore reduce the distance between storage capacitor electrode and the pixel electrode, effectively improved storage capacitance value, satisfying under the prerequisite of storage capacitance value, can reduce the width of storage capacitance line, improve aperture ratio of pixels.
Description of drawings
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, below in conjunction with accompanying drawing the specific embodiment of the present invention is elaborated, wherein:
Fig. 1 is the dot structure figure on the existing array base palte.
Fig. 2 is A-A ' sectional view of Fig. 1.
Fig. 3 A～3G is the manufacturing process schematic diagram of array base palte of the present invention.
Embodiment
Fig. 3 A～3G is the manufacturing process schematic diagram of array base palte of the present invention.
Please refer to Fig. 3 A, one substrate 10 is provided, substrate 10 is an insulated substrate, ground floor metal film on substrate 10 surface sputterings of cleaning (figure does not show), for example aluminium (Al) or aluminium alloy (AlNd), or metal multilayer film (AlNd/MoNb) is coated with photoresist then as grid material on this metal film, utilizes halftone mask (semi-transparent mask) to form the figure with different photoresist thickness.Wherein the photoresist layer 114 of covering gate polar region (with reference to the position that forms grid 112 shown in Fig. 3 A) has second height, and the photoresist layer 113 that covers storage capacitor electrode district (with reference to the position that forms storage capacitor electrode 111 shown in Fig. 3 A) has first height, and second height is less than this first height.Then, be mask with this photoresist pattern, remove the part the first metal layer by etching, form grid 112 and storage capacitor electrode 111.
Afterwards, please refer to Fig. 3 B, utilize the plasma ashing reaction, the photoresist on the grid 112 is all removed, and storage capacitor electrode 111 reserve part photoresists.
Afterwards, please refer to Fig. 3 C, pass through PECVD (plasma-reinforced chemical vapor deposition) process deposits one deck gate insulation layer 121, for example SiNx or SiO at grid 112 and storage capacitor electrode 111
2Gate insulating film, wherein the gate insulation layer 121 on the storage capacitor electrode 111 is positioned on the photoresist 113.
Afterwards, please refer to Fig. 3 D, by CVD technology, deposited semiconductor material a-Si and N+Si thin layer (figure does not show) adopt the sputter sputter on gate insulation layer 121, continue deposition second layer metal film (figure does not show), for example Cr or Al and alloy material thereof.By GTM (Gray Tone Mask) technology, after employing exposure and the etching, define source electrode 141, drain electrode 142 and semiconductor figure 131 and ohmic contact 132 respectively, make the TFT switch element.
Afterwards, please refer to Fig. 3 E, utilize lift-off technology technology, the photoresist that storage capacitor electrode 111 keeps is removed, simultaneously the gate insulation layer on it 121 is removed.
Afterwards, please refer to Fig. 3 F,, expose then, develop and do and carve, obtain the pattern 123 of contact hole, as the passage that connects source electrode and pixel electrode by PECVD technology deposition one deck passivation layer 122 on source electrode 141, drain electrode 142 and storage capacitor electrode 111.
At last, please refer to Fig. 3 G, sputter last layer transparent membrane on passivation layer 122 (figure do not show) as ITO, carries out obtaining pixel electrode 15 after the operation such as graphical then.So just finish the manufacturing of active array base plate.
The array base palte that prior art is made, between storage capacitor electrode and the pixel electrode across gate insulation layer and passivation layer, and the array base palte that the present invention makes, between storage capacitor electrode and the pixel electrode only across passivation layer.Therefore, the array base palte that adopts the present invention to make reduces the distance between storage capacitor electrode and the pixel electrode, has effectively improved storage capacitance.As seen from Table 1, array base palte provided by the invention, storage capacitance line can have original 10um to reduce to 5um, and aperture opening ratio increases by 4.48%.
Table 1 adopts the result of different pixels structure and parameter to compare
| Existing dot structure | The dot structure that the inventive method is made | |
| The Cs live width | 10um | 5um |
| The shading live width | 5um | 4um |
| The Cs size | 0.259pF | 0.418pF |
| Aperture opening ratio | 64.44％ | 68.92％ |
| Aperture opening ratio increases | 4.48％ | |
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can doing a little modification and perfect, so protection scope of the present invention is when with being as the criterion that claims were defined.
Claims (4)
1. the manufacture method of a thin-film transistor array base-plate may further comprise the steps:
One substrate is provided, and forms a first metal layer on this substrate, it has gate regions and storage capacitor electrode district;
Utilize a semi-transparent mask on this first metal layer, to form one first photoresist pattern, the photoresist layer that wherein covers this gate regions has second height, the photoresist layer that covers this storage capacitor electrode district has first height, and this second height is less than this first height;
With this first photoresist pattern is mask, removes the part the first metal layer, to form first conductive pattern layer that comprises grid and storage capacitor electrode;
Remove the segment thickness of this first photoresist pattern, to expose the grid that photoresist layer covered that is had second height by this;
On substrate, deposit a gate insulation layer, semi-conductor layer and an ohmic contact layer successively;
On substrate, continue deposition one second metal level, form source electrode, drain electrode and semiconductor figure respectively, make the TFT switch element;
Remove gate insulation layer and remaining this first photoresist pattern on this storage capacitor electrode, to expose the storage capacitor electrode that photoresist layer covered that is had first height by this;
Deposition one passivation layer forms contact hole on source, drain electrode and storage capacitor electrode;
Sputter last layer transparent membrane on passivation layer forms pixel electrode at last.
2. the manufacture method of thin-film transistor array base-plate as claimed in claim 1 is characterized in that, the method for removing the segment thickness of this first photoresist pattern comprises the plasma ashing operation.
3. the manufacture method of thin-film transistor array base-plate as claimed in claim 1 is characterized in that, the method that forms source electrode, drain electrode and semiconductor figure comprises the coating photoresist, uses the exposure of GTM technology, develops etching and stripping process.
4. the manufacture method of thin-film transistor array base-plate as claimed in claim 1 is characterized in that, gate insulation layer and remaining this first photoresist pattern method of removing on the storage capacitor electrode comprise lift-off technology technology.
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| CNA2008100343858A CN101236932A (en) | 2008-03-07 | 2008-03-07 | Thin film transistor array base plate making method |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103117284A (en) * | 2013-02-01 | 2013-05-22 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof and display device |
| WO2016078134A1 (en) * | 2014-11-20 | 2016-05-26 | 深圳市华星光电技术有限公司 | Method for manufacturing thin film transistor |
| CN106896603A (en) * | 2017-03-22 | 2017-06-27 | 南京中电熊猫平板显示科技有限公司 | Dot structure and its manufacture method |
| CN107085334A (en) * | 2017-03-22 | 2017-08-22 | 南京中电熊猫平板显示科技有限公司 | A kind of dot structure and its manufacture method |
| CN108227327A (en) * | 2018-02-28 | 2018-06-29 | 上海中航光电子有限公司 | A kind of array substrate, display panel and display device |
| WO2019205702A1 (en) * | 2018-04-25 | 2019-10-31 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, and manufacturing method thereof |
| CN108649016B (en) * | 2018-05-09 | 2020-11-24 | 深圳市华星光电技术有限公司 | Manufacturing method of array substrate |
| CN116676571A (en) * | 2023-04-26 | 2023-09-01 | 武汉敏芯半导体股份有限公司 | Electrode manufacturing method, electrode and semiconductor device |
-
2008
- 2008-03-07 CN CNA2008100343858A patent/CN101236932A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103117284A (en) * | 2013-02-01 | 2013-05-22 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof and display device |
| US9576989B2 (en) | 2013-02-01 | 2017-02-21 | Boe Technology Group Co., Ltd. | Array substrate and the method for making the same, and display device |
| WO2016078134A1 (en) * | 2014-11-20 | 2016-05-26 | 深圳市华星光电技术有限公司 | Method for manufacturing thin film transistor |
| CN106896603A (en) * | 2017-03-22 | 2017-06-27 | 南京中电熊猫平板显示科技有限公司 | Dot structure and its manufacture method |
| CN107085334A (en) * | 2017-03-22 | 2017-08-22 | 南京中电熊猫平板显示科技有限公司 | A kind of dot structure and its manufacture method |
| CN108227327A (en) * | 2018-02-28 | 2018-06-29 | 上海中航光电子有限公司 | A kind of array substrate, display panel and display device |
| WO2019205702A1 (en) * | 2018-04-25 | 2019-10-31 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, and manufacturing method thereof |
| CN108649016B (en) * | 2018-05-09 | 2020-11-24 | 深圳市华星光电技术有限公司 | Manufacturing method of array substrate |
| CN116676571A (en) * | 2023-04-26 | 2023-09-01 | 武汉敏芯半导体股份有限公司 | Electrode manufacturing method, electrode and semiconductor device |
| CN116676571B (en) * | 2023-04-26 | 2024-01-19 | 武汉敏芯半导体股份有限公司 | Electrode manufacturing method, electrode and semiconductor device |
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