CN106896603A - Dot structure and its manufacture method - Google Patents

Dot structure and its manufacture method Download PDF

Info

Publication number
CN106896603A
CN106896603A CN201710172821.7A CN201710172821A CN106896603A CN 106896603 A CN106896603 A CN 106896603A CN 201710172821 A CN201710172821 A CN 201710172821A CN 106896603 A CN106896603 A CN 106896603A
Authority
CN
China
Prior art keywords
insulating barrier
hole
layer
metal layer
dot structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201710172821.7A
Other languages
Chinese (zh)
Inventor
黄威
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nanjing CEC Panda LCD Technology Co Ltd
Nanjing CEC Panda FPD Technology Co Ltd
TPV Technology Co Ltd
Original Assignee
Nanjing CEC Panda LCD Technology Co Ltd
Nanjing Huadong Electronics Information and Technology Co Ltd
Nanjing CEC Panda FPD Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nanjing CEC Panda LCD Technology Co Ltd, Nanjing Huadong Electronics Information and Technology Co Ltd, Nanjing CEC Panda FPD Technology Co Ltd filed Critical Nanjing CEC Panda LCD Technology Co Ltd
Priority to CN201710172821.7A priority Critical patent/CN106896603A/en
Publication of CN106896603A publication Critical patent/CN106896603A/en
Priority to PCT/CN2018/072781 priority patent/WO2018171311A1/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136213Storage capacitors associated with the pixel electrode
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136227Through-hole connection of the pixel electrode to the active element through an insulation layer

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

The invention discloses a kind of dot structure and its manufacture method, dot structure includes substrate, the first metal layer being from bottom to top sequentially distributed on the substrate, the first insulating barrier, semiconductor layer, second metal layer, the second insulating barrier, pixel electrode layer, the first metal layer etches to form grid and public electrode wire, second metal layer etches to form source electrode and drain electrode, the first hole above public electrode wire is offered on first insulating barrier, there is the first insulating barrier between the first hole and public electrode wire;The second hole above drain electrode is offered on second insulating barrier, pixel electrode layer material is formed and is entered in the first hole and the second hole.The present invention can reduce gate-source capacitance Cgs, and storage capacitance Cst can be increased again, so as to solve flicker(flicker)Problem, simple structure, technique easily realizes, has a good application prospect.

Description

Dot structure and its manufacture method
Technical field
The present invention relates to technical field of liquid crystal display, and in particular to a kind of dot structure and its manufacture method.
Background technology
In the conventional pixel designs of available liquid crystal product, gate-source capacitance Cgs is larger, for convenience of description, with most simple TN pattern a-Si 5Mask techniques as a example by, as shown in figure 1, first layer metal layer 101 and the overlapping face of second layer metal layer 102 Product can cause leaping voltage than larger and in small distance(feed through)Voltage △ Vp can be than larger, △ Vp ≈ [Cgs/ (Cst+Clc)]*(Vgh-Vgl), wherein, Cst be storage capacitance, Clc be liquid crystal capacitance, Vgh and Vgl be grid level high voltage and Grid low-voltage, in the case that vacuum electrode voltage △ Vp are larger, can increase LCD screen and flicker occur(flicker)Wind Danger, influences the normal display of LCD screen.
At present, △ Vp can be reduced by reducing gate-source capacitance Cgs, but often storage capacitance Cst also can and then reduce, △ Vp can not be effectively reduced, then how while gate-source capacitance Cgs is reduced, it is ensured that storage capacitance Cst is constant or even increases Greatly, it is current urgent problem.
The content of the invention
The purpose of the present invention is to overcome LCD screen in the prior art to exist to occur flashing(flicker)Risk.This hair The dot structure and its manufacture method of bright offer, the thickness of the first insulating barrier are not less than 3000 angstroms, can increase the first metal layer, the The distance between two metal levels, reduce gate-source capacitance Cgs, and first above public electrode wire is offered on the first insulating barrier The second hole above drain electrode is offered on hole, the second insulating barrier, the part of pixel electrode layer enters the first hole and the second hole It is interior, by increasing capacitance it is possible to increase storage capacitance Cst, gate-source capacitance Cgs can be reduced, storage capacitance Cst can be increased again, so as to solve flicker (flicker)Problem, simple structure, technique easily realizes, has a good application prospect.
In order to achieve the above object, the technical solution adopted in the present invention is:
A kind of dot structure, including substrate, the first metal layer being from bottom to top sequentially distributed on the substrate, the first insulation Layer, semiconductor layer, second metal layer, the second insulating barrier, pixel electrode layer, the first metal layer etch to form grid and public Electrode wires, the second metal layer etches to form source electrode and drain electrode, is offered positioned at the common electrical on first insulating barrier , there is the first insulating barrier between first hole and the public electrode wire in the first hole above polar curve;Second insulating barrier On offer the second hole above the drain electrode, the material for forming the pixel electrode layer enters first hole and second In hole.
A kind of foregoing dot structure, the pixel electrode layer is made of ITO materials.
A kind of foregoing dot structure, the thickness of first insulating barrier is not less than 3000 angstroms.
A kind of foregoing dot structure, the thickness of the thickness more than second insulating barrier of first insulating barrier.
A kind of foregoing dot structure, the depth in first hole is more than the 80% of first thickness of insulating layer.
Foregoing dot structure, first insulating barrier is single layer structure.
Based on the manufacture method of above-mentioned dot structure, comprise the following steps,
Step(A):The first metal layer is deposited on substrate, and etches to form grid and public electrode wire in the first metal layer;
Step(B):Form the first insulating barrier of the covering the first metal layer;
Step(C):The first hole above public electrode wire is opened up on the first insulating barrier, first hole and the common electrical There is the first insulating barrier between polar curve;
Step(D):Semiconductor layer is formed on first insulating barrier;
Step(E):Depositing second metal layer on the semiconductor layer, and etch to form source electrode and drain electrode in the second metal layer;
Step(F):Form the second insulating barrier of covering second metal layer;
Step(G):The second hole above drain electrode is opened up over the second dielectric;
Step(H):The pixel electrode layer that deposition is made up of ITO materials, and ITO materials enter first hole, the second hole, ITO Material is electrically connected with pixel electrode layer and drain electrode.
The manufacture method of foregoing dot structure, step(B), the thickness of first insulating barrier is not less than 3000 angstroms.
The manufacture method of foregoing dot structure, step(B), first insulating barrier is single layer structure.
The manufacture method of foregoing dot structure, step(C), first hole depth is first thickness of insulating layer More than 80%.
The beneficial effects of the invention are as follows:Dot structure and its manufacture method that the present invention is provided, the thickness of the first insulating barrier Not less than 3000 angstroms, the distance between the first metal layer, second metal layer can be increased, reduce gate-source capacitance Cgs;First insulating barrier On offer the first hole above public electrode wire, the second hole above drain electrode offered on the second insulating barrier, as The part of plain electrode layer enters in the first hole and the second hole, by increasing capacitance it is possible to increase storage capacitance Cst, can reduce gate-source capacitance Cgs, and Storage capacitance Cst can be increased, so as to solve flicker(flicker)Problem, simple structure, technique is easily realized, with good Application prospect.
Brief description of the drawings
Fig. 1 is the schematic diagram of existing TN patterns a-Si 5Mask technique dot structures;
Fig. 2 is the structural representation of dot structure of the invention.
Fig. 3 is the top view of the second hole of the invention position.
The implication marked in accompanying drawing is as follows:
101:First layer metal layer;102:Second layer metal layer;201:Substrate;202:The first metal layer;2021:Grid;2022: Public electrode wire;203:First insulating barrier;204:Semiconductor layer;205:Second metal layer;2051:Source electrode;2052:Drain electrode; 206:Second insulating barrier;207:Pixel electrode layer;208:First hole;209:Second hole.
Specific embodiment
Below in conjunction with Figure of description, the present invention is further illustrated.
As shown in Figures 2 and 3, dot structure of the invention, including substrate 201, on the substrate 201 from bottom to top The first metal layer 202, the first insulating barrier 203, semiconductor layer 204, second metal layer 205, the second insulating barrier being sequentially distributed 206th, pixel electrode layer 207, the etching of the first metal layer 202 forms grid 2021 and public electrode wire 2022, second metal layer 205 Etching forms source electrode 2051 and drain electrode 2052, and first positioned at the top of public electrode wire 2022 is offered on the first insulating barrier 203 , there is the first insulating barrier 203 between the first hole 208 and public electrode wire 2022 in hole 208,
More than the thickness of the second insulating barrier 206, the depth in the first hole 208 is first exhausted to the thickness of preferred first insulating barrier 203 More than the 80% of the thickness of edge layer 203, makes the first hole 208 be located in the first insulating barrier 203, and not upper with public electrode wire 2022 Surface UNICOM, makes to leave the first insulating barrier 203 of part between the first hole 208 and public electrode wire 2022;
The thickness of preferred first insulating barrier 203 be not less than 3000 angstroms, angstrom be long measure, 1 angstrom=10^ (- 10) rice can Increase the distance between the first metal layer 202, second metal layer 205, so as to gate-source capacitance Cgs can be reduced;
The second hole 209 positioned at the top of drain electrode 2052 is offered on second insulating barrier 206, pixel electrode layer 207 is formed Material enters in the first hole 208 and the second hole 209, and the second hole 209 can increase storage capacitance Cst, according to vacuum electrode voltage △Vp≈Cgs/(Cst+Clc), vacuum electrode voltage △ Vp can be reduced, so that reducing LCD screen flicker occurs (flicker)Risk, it is ensured that the normal display of LCD screen.
Preferred pixel electrode layer 207 is made of ITO materials.
Preferred first insulating barrier 203 is single layer structure.
The manufacture method of above-mentioned dot structure, comprises the following steps,
Step(A):The first metal layer 202 is deposited on substrate 201, and grid 2021 is formed in the first metal layer 202 etching With public electrode wire 2022;
Step(B):Form the first insulating barrier 203 of covering the first metal layer 202, the first insulating barrier 203 is single layer structure, and thick Degree 203 is not less than 3000 angstroms;
Step(C):The first hole 208 positioned at the top of public electrode wire 2022, first hole are opened up on the first insulating barrier 203 There is the first insulating barrier between 208 and public electrode wire 2022, the depth in preferred first hole 208 is the thickness of the first insulating barrier 203 More than the 80% of degree so that the first hole 208 is located on the first insulating barrier 203, and not with the upper surface phase of public electrode wire 2022 UNICOM;
Step(D):Semiconductor layer 204 is formed on the first insulating barrier 203;
Step(E):The depositing second metal layer 205 on semiconductor layer 204, and form source electrode in the second metal layer 205 etching 2051 and drain electrode 2052;
Step(F):Form the second insulating barrier 206 of covering second metal layer 205;
Step(G):The second hole 209 positioned at the top of drain electrode 2052 is opened up on the second insulating barrier 206;
Step(H):The pixel electrode layer 207 that deposition is made up of ITO materials, and ITO materials enter the first hole 208, the second hole 209, ITO materials are electrically connected with pixel electrode layer 207 and drain electrode 2052.
In manufacture method of the invention, all layers of making will experience " film forming, the coating of photoresistance glue, using mask exposures, The operations such as development, etching, the stripping of photoresistance glue ", the present invention is only referred to two operations of film forming and etching to briefly explain, And other several normal process steps are eliminated, it is essentially all what is had.Such as depth hole has etched, using mask(Or halftone mask)The first hole or the second hole are etched, wherein, mask is light shield or mask plate etching mode, halftone Mask is many contrast mask plates or pellicle mask plate etching mode, and specific steps should after depth hole has been carved, be coated with photoresistance glue, (Here no film forming and be directly coated with photoresistance glue because film is before into good), using mask(Or halftone mask)Expose the figure in the first or second hole on photoresistance glue, then develop, then it is developed to photoresistance glue fall do not have Film at protection is performed etching, and the first or second hole is formed, and then photoresistance glue is peeled off, and then does next layer(Such as pixel electrode Layer), the present invention needs etching depth hole due to the second insulating barrier, if so being not inserted into other metal levels does the scheme for stopping If, the second hole cannot just etch together with depth hole, and must be another to do the using a mask is special after depth hole has been carved Two holes, perform above-mentioned operation, only save film forming, so-called second hole, are for relatively deep, shallow bore hole, simply to express depth not Together, and not it is really poroid figure, but it is a sheet of, the purpose in the second hole is used to increase storage capacitance Cst.
In sum, the present invention is provided dot structure and its manufacture method, the thickness of the first insulating barrier are not less than 3000 Angstrom, the distance between the first metal layer, second metal layer can be increased, reduce gate-source capacitance Cgs;Position is offered on first insulating barrier The second hole above drain electrode is offered on the first hole, the second insulating barrier above public electrode wire, pixel electrode layer Part enters in the first hole and the second hole, by increasing capacitance it is possible to increase storage capacitance Cst, can reduce gate-source capacitance Cgs, and can increase storage Electric capacity Cst, so as to solve flicker(flicker)Problem, simple structure, technique easily realizes, has a good application prospect.
General principle of the invention, principal character and advantage has been shown and described above.The technical staff of the industry should Understand, the present invention is not limited to the above embodiments, simply original of the invention is illustrated described in above-described embodiment and specification Reason, without departing from the spirit and scope of the present invention, various changes and modifications of the present invention are possible, these changes and improvements All fall within the protetion scope of the claimed invention.The claimed scope of the invention is by appending claims and its equivalent circle. It is fixed.

Claims (10)

1. it is a kind of dot structure, including substrate, the first metal layer being from bottom to top sequentially distributed on the substrate, first exhausted Edge layer, semiconductor layer, second metal layer, the second insulating barrier, pixel electrode layer, the first metal layer etch to form grid and public affairs Common-battery polar curve, the second metal layer etches to form source electrode and drain electrode, it is characterised in that:Position is offered on first insulating barrier , there is the first insulating barrier between first hole and the public electrode wire in the first hole above the public electrode wire;Institute The second hole offered on the second insulating barrier above the drain electrode is stated, the material for forming the pixel electrode layer enters described In first hole and the second hole.
2. a kind of dot structure according to claim 1, it is characterised in that:The pixel electrode layer uses ITO material systems Into.
3. a kind of dot structure according to claim 1, it is characterised in that:The thickness of first insulating barrier is not less than 3000 angstroms.
4. a kind of dot structure according to claim 1 or 3, it is characterised in that:The thickness of first insulating barrier is more than The thickness of second insulating barrier.
5. a kind of dot structure according to claim 1 or 3, it is characterised in that:The depth in first hole is described the More than the 80% of one thickness of insulating layer.
6. the dot structure according to claim 1 or 3, it is characterised in that:First insulating barrier is single layer structure.
7. the manufacture method of dot structure described in claim any one of 1-6 is based on, it is characterised in that:Comprise the following steps,
Step(A):The first metal layer is deposited on substrate, and etches to form grid and public electrode wire in the first metal layer;
Step(B):Form the first insulating barrier of the covering the first metal layer;
Step(C):The first hole above public electrode wire is opened up on the first insulating barrier, first hole and the common electrical There is the first insulating barrier between polar curve;
Step(D):Semiconductor layer is formed on first insulating barrier;
Step(E):Depositing second metal layer on the semiconductor layer, and etch to form source electrode and drain electrode in the second metal layer;
Step(F):Form the second insulating barrier of covering second metal layer;
Step(G):The second hole above drain electrode is opened up over the second dielectric;
Step(H):The pixel electrode layer that deposition is made up of ITO materials, and ITO materials enter first hole, the second hole, ITO Material is electrically connected with pixel electrode layer and drain electrode.
8. the manufacture method of dot structure according to claim 7, it is characterised in that:Step(B), first insulating barrier Thickness be not less than 3000 angstroms.
9. the manufacture method of the dot structure according to claim 7 or 8, it is characterised in that:Step(B), described first is exhausted Edge layer is single layer structure.
10. the manufacture method of the dot structure according to claim 7 or 8, it is characterised in that:Step(C), first hole Depth is more than the 80% of first thickness of insulating layer.
CN201710172821.7A 2017-03-22 2017-03-22 Dot structure and its manufacture method Pending CN106896603A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201710172821.7A CN106896603A (en) 2017-03-22 2017-03-22 Dot structure and its manufacture method
PCT/CN2018/072781 WO2018171311A1 (en) 2017-03-22 2018-01-16 Pixel structure and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710172821.7A CN106896603A (en) 2017-03-22 2017-03-22 Dot structure and its manufacture method

Publications (1)

Publication Number Publication Date
CN106896603A true CN106896603A (en) 2017-06-27

Family

ID=59193084

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710172821.7A Pending CN106896603A (en) 2017-03-22 2017-03-22 Dot structure and its manufacture method

Country Status (1)

Country Link
CN (1) CN106896603A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018171311A1 (en) * 2017-03-22 2018-09-27 南京中电熊猫平板显示科技有限公司 Pixel structure and manufacturing method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1183570A (en) * 1996-11-26 1998-06-03 三星电子株式会社 Liquid crystal display using organic insulating material and manufacturing methods thereof
US20060006385A1 (en) * 2004-06-30 2006-01-12 Lg. Philips Lcd Co., Ltd. Liquid crystal display device and method of manufacturing liquid crystal display device with color filter layer on thin film transistor
CN101236932A (en) * 2008-03-07 2008-08-06 上海广电光电子有限公司 Thin film transistor array base plate making method
EP2354839A1 (en) * 2009-12-17 2011-08-10 AU Optronics Corporation Liquid crystal display
CN105051596A (en) * 2013-03-27 2015-11-11 株式会社半导体能源研究所 Display device and electronic device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1183570A (en) * 1996-11-26 1998-06-03 三星电子株式会社 Liquid crystal display using organic insulating material and manufacturing methods thereof
US20060006385A1 (en) * 2004-06-30 2006-01-12 Lg. Philips Lcd Co., Ltd. Liquid crystal display device and method of manufacturing liquid crystal display device with color filter layer on thin film transistor
CN101236932A (en) * 2008-03-07 2008-08-06 上海广电光电子有限公司 Thin film transistor array base plate making method
EP2354839A1 (en) * 2009-12-17 2011-08-10 AU Optronics Corporation Liquid crystal display
CN105051596A (en) * 2013-03-27 2015-11-11 株式会社半导体能源研究所 Display device and electronic device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018171311A1 (en) * 2017-03-22 2018-09-27 南京中电熊猫平板显示科技有限公司 Pixel structure and manufacturing method thereof

Similar Documents

Publication Publication Date Title
CN105304649B (en) Array substrate and preparation method thereof, display panel, display device
CN104393000B (en) Array substrate, manufacturing method thereof and display device
CN101630640B (en) Photoresist burr edge-forming method and TFT-LCD array substrate-manufacturing method
CN103489922A (en) Thin film transistor and preparation method thereof, array substrate and preparation method thereof and display device
CN107230661A (en) A kind of array base palte and preparation method thereof, display device
CN106932990A (en) The preparation method of display panel, display device and display panel
CN105702687A (en) TFT (Thin Film Transistor) substrate and manufacturing method thereof
CN104317097A (en) COA (color filter on array) substrate, production method thereof and display device
CN107132710A (en) A kind of array base palte and preparation method thereof, display panel
CN104576523A (en) Array substrate, production method of array substrate and display device
CN103235458B (en) TFT-LCD array substrate and manufacture method thereof
CN106935546B (en) Preparation method, array substrate, display panel and the display device of array substrate
CN105070765B (en) Thin film transistor (TFT), array substrate, display device and manufacturing method
CN107369715A (en) A kind of manufacture method of thin film transistor (TFT)
CN103048840B (en) Array substrate, manufacture method of array substrate, liquid crystal display panel and display device
CN106887379A (en) A kind of semi-transparent mask patterning process and array base palte, display device
CN104133313A (en) Array substrate, manufacturing method thereof and liquid crystal display device
CN104882450B (en) A kind of array substrate and preparation method thereof, display device
CN106898616A (en) The preparation method and TFT substrate of TFT substrate
CN110828476B (en) Array substrate, preparation method thereof and display device
CN106354319A (en) Method for preparing touch screen and method for preparing touch display device
CN204129400U (en) A kind of COA substrate and display device
CN1350326A (en) Thin film transistor planar display
WO2017012292A1 (en) Array substrate, preparation method thereof, display panel and display device
CN103915380A (en) Manufacturing method of array substrate, array substrate and display device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20170627

RJ01 Rejection of invention patent application after publication