WO2018171311A1

WO2018171311A1 - Pixel structure and manufacturing method thereof

Info

Publication number: WO2018171311A1
Application number: PCT/CN2018/072781
Authority: WO
Inventors: 黄威
Original assignee: 南京中电熊猫平板显示科技有限公司; 南京中电熊猫液晶显示科技有限公司; 南京华东电子信息科技股份有限公司
Priority date: 2017-03-22
Filing date: 2018-01-16
Publication date: 2018-09-27

Abstract

A pixel structure and a manufacturing method thereof. The pixel structure comprises a substrate (201), and a first metal layer (202), a first insulation layer (203), a semiconductor layer (204), a second metal layer (205), a second insulation layer (206), and a pixel electrode layer (207) sequentially disposed from bottom to top on the substrate (201). The first metal layer (202) is etched to form a gate (2021) and a common electrode line (2022). The second metal layer (205) is etched to form a source (2051) and a drain (2052). The first insulation layer (203) is provided with a first hole (209) located above the common electrode line (2022). An insulation material layer is disposed between the first hole (209) and the common electrode line (2022). The second insulation layer (206) is provided with a second hole (210) located above the drain (2052). A material forming the pixel electrode layer (207) enters into the first hole (209) and the second hole (210). Gate source capacitance (Cgs) is reduced and storage capacitance (Cst) is increased, thereby solving the problem of flicker. The structure is simple, the process is easily implemented, and application prospects are favorable.

Description

Pixel structure and manufacturing method thereof

This application is required to be submitted to the China Patent Office on March 22, 2017, the application number is 201710172813.2, the invention name is “a pixel structure and its manufacturing method”, and it is submitted to the Chinese Patent Office on March 22, 2017, and the application number is 201710172821.7. The invention is entitled "Pixel Structure and Method of Manufacture", the entire disclosure of which is incorporated herein by reference.

Technical field

The present application relates to the field of liquid crystal display technology, and in particular, to a pixel structure and a method of fabricating the same. .

Background technique

In the conventional pixel design of the existing liquid crystal product, the gate source capacitance Cgs is large. For convenience of explanation, the simplest TN mode a-Si 5Mask process is taken as an example, as shown in FIG. 1, the first metal layer 101 and the first layer. The overlapping area of the two-layer metal layer 102 is relatively large, and the distance is small, which causes the feed through voltage ΔVp to be relatively large, ΔVp ≈ [Cgs / (Cst + Clc)] * (Vgh - Vgl) Where Cst is the storage capacitor, Clc is the liquid crystal capacitor, Vgh and Vgl are the gate high voltage and the gate low voltage, and the vacuum electrode voltage ΔVp is large, which increases the risk of flicker on the liquid crystal screen. Affects the normal display of the LCD screen.

At present, ΔVp can be reduced by reducing the gate-source capacitance Cgs, but the storage capacitor Cst is also reduced, and ΔVp cannot be effectively reduced. Therefore, how to reduce the gate-source capacitance Cgs while ensuring the storage capacitor Cst is not Changing or even increasing is an urgent problem to be solved.

Summary of the invention

The invention provides a pixel structure and a manufacturing method thereof, aiming at overcoming the risk of occurrence of flicker in a liquid crystal screen in the prior art.

In order to achieve the above object, the present invention adopts the following technical solutions:

A pixel structure includes a substrate, a first metal layer, a first insulating layer, a semiconductor layer, a second metal layer, a second insulating layer, and a pixel electrode layer, which are sequentially arranged from bottom to top on the substrate, a metal layer is etched to form a gate electrode and a common electrode line, the second metal layer is etched to form a source and a drain, and the first insulating layer is provided with a first hole above the common electrode line. An insulating material layer is disposed between the first hole and the common electrode line; a second hole above the drain is opened on the second insulating layer, and a material forming the pixel electrode layer enters the first hole One hole and two holes.

Optionally, the layer of insulating material is formed by a second insulating layer.

Optionally, a third metal layer is further disposed between the first hole and the insulating material layer.

Optionally, the first insulating layer is a two-layer structure, including a first lower insulating layer on the first metal layer and a first upper insulating layer on the first lower insulating layer, the first upper layer The thickness of the insulating layer is greater than the thickness of the first lower insulating layer, and the insulating material layer is formed of the first lower insulating layer.

Optionally, the third metal layer is located between the first lower insulating layer and the first upper insulating layer, and the first hole is opened in the first upper insulating layer.

Optionally, the first hole is formed in the first insulating layer, and the insulating material layer is a first insulating layer having a partial thickness.

Optionally, the depth of the first hole is more than 80% of the thickness of the first insulating layer.

Optionally, the first insulating layer is a single layer structure.

Optionally, the material of the pixel electrode layer is an ITO material.

Optionally, the first insulating layer has a thickness of not less than 3000 angstroms.

Optionally, the thickness of the second insulating layer is smaller than the thickness of the first insulating layer.

A method of fabricating a pixel structure, comprising the steps of:

Step (A): depositing a first metal layer on the substrate, and etching the first metal layer to form a gate electrode and a common electrode line;

Step (B): forming a first insulating layer covering the first metal layer;

Step (C): opening a first hole above the common electrode line on the first insulating layer;

Step (D): forming a semiconductor layer on the first insulating layer;

Step (E): depositing a second metal layer on the semiconductor layer, and etching the second metal layer to form a source and a drain;

Step (F): forming a second insulating layer covering the second metal layer, and a portion of the second insulating layer enters the first hole;

Step (G): opening a second hole on the drain in the second insulating layer;

Step (H): depositing a pixel electrode layer, and a material of the pixel electrode layer enters the first hole and the second hole.

A method of fabricating a pixel structure, comprising the steps of:

Step (B): forming a first lower insulating layer covering the first metal layer, forming a third metal layer on the first lower insulating layer and above the common electrode line, forming the first lower insulating layer and the third a first upper insulating layer on the metal layer;

Step (C): opening a first hole above the common electrode line on the first upper insulating layer;

Step (D): forming a semiconductor layer on the first upper insulating layer;

Step (F): forming a second insulating layer covering the second metal layer;

Step (G): opening a second hole above the drain on the second insulating layer;

A method of fabricating a pixel structure, comprising the steps of:

Step (B): forming a first insulating layer covering the first metal layer;

Step (C): opening a first hole above the common electrode line on the first insulating layer, and a first insulating layer exists between the first hole and the common electrode line;

Step (D): forming a semiconductor layer on the first insulating layer;

Step (F): forming a second insulating layer covering the second metal layer;

Step (G): opening a second hole above the drain on the second insulating layer;

Step (H): depositing a pixel electrode layer, and the material of the pixel electrode layer enters the first hole and the second hole.

The pixel structure and the manufacturing method thereof are provided in the embodiment, the first insulating layer is provided with a first hole above the common electrode line, and the second insulating layer is provided with a second hole above the drain, the pixel electrode layer Partially entering the first hole and the second hole; further, the thickness of the first insulating layer is not less than 3000 angstroms, the distance between the first metal layer and the second metal layer may be increased, and the gate source capacitance Cgs may be decreased; The storage capacitor Cst can reduce the gate-source capacitance Cgs and increase the storage capacitor Cst, thereby solving the problem of flicker. The structure is simple, the process is easy to implement, and has a good application prospect.

DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below. Obviously, the drawings in the following description are only It is an embodiment of the present invention, and those skilled in the art can obtain other drawings according to the provided drawings without any creative work.

1 is a schematic diagram of a conventional TN mode a-Si 5Mask process pixel structure;

2 is a cross-sectional structural view showing a first embodiment of a pixel structure of the present invention;

Figure 3 is a plan view showing the position of the first hole in the first embodiment of the present invention;

4 is a cross-sectional structural view showing a second embodiment of the pixel structure of the present invention;

Figure 5 is a plan view of a third metal layer in a second embodiment of the present invention;

6 is a cross-sectional structural view showing a third embodiment of a pixel structure of the present invention;

Figure 7 is a plan view showing the position of the second hole in the third embodiment of the present invention.

The meanings of the marks in the drawings are as follows:

101: first metal layer; 102: second metal layer; 201: substrate; 202: first metal layer; 2021: gate; 2022: common electrode line; 203: first insulating layer; 2031: first Insulating layer; 2032: first upper insulating layer; 204: semiconductor layer; 205: second metal layer; 2051: source; 2052: drain; 206: second insulating layer; 207: pixel electrode layer; 208: third Metal layer; 209: first hole; 210: second hole.

detailed description

The invention will now be further described with reference to the drawings of the specification.

As shown in FIG. 2 and FIG. 3, the pixel structure of the first embodiment of the present invention includes a substrate 201, a first metal layer 202, a first insulating layer 203, and a semiconductor layer, which are sequentially arranged from bottom to top on the substrate 201. 204, the second metal layer 205, the second insulating layer 206, the pixel electrode layer 207, the first metal layer 202 is etched to form the gate electrode 2021 and the common electrode line 2022, and the second metal layer 205 is etched to form the source electrode 2051 and the drain electrode. The first insulating layer 203 is provided with a first hole 209 above the common electrode line 2022. A portion of the second insulating layer enters the first hole 209. The second insulating layer 206 is disposed above the drain electrode 2052. The second hole 210, the ITO material forming the pixel electrode layer 207 enters the first hole 209 and the second hole 210, and the ITO material enables the pixel electrode layer 207 and the drain electrode 2052 to be electrically connected.

The thickness of the first insulating layer 203 is not less than 3000 angstroms, the angstrom is a unit of length, 1 angstrom = 10^(-10) meters, and the thickness of the second insulating layer 206 is smaller than the thickness of the first insulating layer 203. The first insulating layer 203 having a thickness of not less than 3000 angstroms can increase the distance between the first metal layer 202 and the second metal layer 205, thereby reducing the gate-source capacitance Cgs, and the first insulating layer 203 is opened on the common electrode A second hole 210 above the drain electrode 2052 is opened on the first hole 209 and the second insulating layer 206 above the line 2022, and the storage capacitor Cst can be increased. According to the vacuum electrode voltage ΔVp ≈ Cgs / (Cst + Clc), The vacuum electrode voltage ΔVp is reduced, thereby reducing the risk of flicker on the liquid crystal screen and ensuring the normal display of the liquid crystal screen.

The first insulating layer 203 in the first embodiment has a single layer structure.

The manufacturing method of the pixel structure of the first embodiment includes the following steps,

Step (A): depositing a first metal layer 202 on the substrate 201, and etching the first metal layer 202 to form a gate electrode 2021 and a common electrode line 2022;

Step (B): forming a first insulating layer 203 covering the first metal layer 202, the thickness is not less than 3000 angstroms;

Step (C): opening a first hole 209 above the common electrode line 2022 on the first insulating layer 203;

Step (D): forming a semiconductor layer 204 on the first insulating layer 203;

Step (E): depositing a second metal layer 205 on the semiconductor layer 204, and etching the second metal layer 205 to form a source electrode 2051 and a drain electrode 2052;

Step (F): forming a second insulating layer 206 covering the second metal layer 205, and a portion of the second insulating layer 206 enters the first hole 209 and enters the second insulating layer 206 in the first hole 209 The thickness of the portion is lower than the thickness of the first insulating layer 203;

Step (G): opening a second hole 210 on the drain electrode 2052 in the second insulating layer 206;

Step (H): depositing a pixel electrode layer 207 made of an ITO material, and the ITO material enters the first hole 209 and the second hole 210, and the ITO material is electrically connected to the pixel electrode layer 207 and the drain electrode 2052.

As shown in FIG. 4 and FIG. 5, the pixel structure of the second embodiment of the present invention includes a substrate 201, a first metal layer 202, a first insulating layer 203, and a semiconductor layer, which are sequentially arranged from bottom to top on the substrate 201. 204, the second metal layer 205, the second insulating layer 206, the pixel electrode layer 207, the first metal layer 202 is etched to form the gate electrode 2021 and the common electrode line 2022, and the second metal layer 205 is etched to form the source electrode 2051 and the drain electrode. A first hole 209 is disposed on the first insulating layer 203, and a third metal layer 208 is disposed between the first hole 209 and the common electrode line 2022. The second insulating layer 206 is disposed on the second insulating layer 206. The second hole 210 located above the drain electrode 2052, the ITO material forming the pixel electrode layer 207 enters the first hole 209 and the second hole 210, and the ITO material enables the pixel electrode layer 207 and the drain electrode 2052 to be electrically connected.

The first insulating layer 203 has a thickness of not less than 3000 angstroms, and the first insulating layer 203 has a two-layer structure, including a first lower insulating layer 2031 on the first metal layer 202 and the first lower insulating layer 2031. The first upper insulating layer 2032, and the thickness of the first upper insulating layer 2032 is greater than the thickness of the first lower insulating layer 2031, because the first hole 209 needs to be opened thereon, and the third metal layer 208 is located at the first lower insulating layer. 2031, between the first upper insulating layer 2032, the first hole 209 is opened in the first upper insulating layer 2031, and the first insulating layer 203 is not less than 3000 angstroms thick, and the first metal layer 202 and the second metal can be added. The distance between the layers 205, so that the gate-source capacitance Cgs can be reduced. The first upper insulating layer 2032 is provided with a first hole 209 above the common electrode line 2022, and the second insulating layer 206 is disposed above the drain 2052. The second hole 210 can increase the storage capacitor Cst. According to the vacuum electrode voltage ΔVp ≈ Cgs / (Cst + Clc), the vacuum electrode voltage ΔVp can be reduced, thereby reducing the risk of flicker on the liquid crystal screen, and ensuring the liquid crystal. The normal display of the screen.

The manufacturing method of the pixel structure of the second embodiment includes the following steps,

Step (B): forming a first lower insulating layer 2031 covering the first metal layer 202, forming a third metal layer 208 on the first lower insulating layer 2031 and above the common electrode line 2022, forming the first under The first upper insulating layer 2032 on the insulating layer 2031 and the third metal layer 2022;

Step (C): opening a first hole 209 above the common electrode line 2022 on the first upper insulating layer 2032;

Step (D): forming a semiconductor layer 204 on the first upper insulating layer 2032;

Step (F): forming a second insulating layer 206 covering the second metal layer 205;

Step (G): opening a second hole 210 above the drain electrode 2052 on the second insulating layer 206;

As shown in FIG. 6 and FIG. 7 , the pixel structure of the third embodiment of the present invention includes a substrate 201, a first metal layer 202, a first insulating layer 203, and a semiconductor layer, which are sequentially disposed from bottom to top on the substrate 201. 204, the second metal layer 205, the second insulating layer 206, the pixel electrode layer 207, the first metal layer 202 is etched to form the gate electrode 2021 and the common electrode line 2022, and the second metal layer 205 is etched to form the source electrode 2051 and the drain electrode. a first insulating layer 203 is disposed on the first insulating layer 203, and a first insulating layer 203 is disposed between the first hole 209 and the common electrode line 2022.

The thickness of the first insulating layer 203 is greater than the thickness of the second insulating layer 206, and the depth of the first hole 209 is more than 80% of the thickness of the first insulating layer 203, so that the first hole 209 is located in the first insulating layer 203, and Not communicating with the upper surface of the common electrode line 2022, leaving a portion of the first insulating layer 203 between the first hole 209 and the common electrode line 2022;

Preferably, the thickness of the first insulating layer 203 is not less than 3000 angstroms, and the angstrom is a unit of length, and 1 angstrom = 10^(-10) meters, which can increase the distance between the first metal layer 202 and the second metal layer 205, thereby Reducing the gate source capacitance Cgs;

The second insulating layer 206 defines a second hole 210 above the drain electrode 2052. The material forming the pixel electrode layer 207 enters the first hole 209 and the second hole 210. The second hole 210 can increase the storage capacitor Cst. According to the vacuum electrode voltage ΔVp ≈ Cgs / (Cst + Clc), the vacuum electrode voltage ΔVp can be reduced, thereby reducing the risk of flicker on the liquid crystal screen and ensuring the normal display of the liquid crystal screen.

The preferred pixel electrode layer 207 is made of an ITO material.

The preferred first insulating layer 203 is a single layer structure.

The manufacturing method of the pixel structure of the third embodiment described above includes the following steps,

Step (B): forming a first insulating layer 203 covering the first metal layer 202, the first insulating layer 203 is a single layer structure, and the thickness 203 is not less than 3000 angstroms;

Step (C): opening a first hole 209 above the common electrode line 2022 on the first insulating layer 203, and a first insulating layer exists between the first hole 209 and the common electrode line 2022, preferably the first hole 209 The depth is 80% or more of the thickness of the first insulating layer 203, so that the first hole 209 is located on the first insulating layer 203 and is not in communication with the upper surface of the common electrode line 2022;

Step (D): forming a semiconductor layer 204 on the first insulating layer 203;

In the manufacturing method of the present invention, all the layers are subjected to processes such as "film formation, photoresist coating, mask exposure, development, etching, photoresist stripping", etc., for the sake of brief description, only The two processes of film formation and etching, and omitting several other conventional processes, are actually necessary. For example, the deep hole is etched, and the first hole or the second hole is etched by a mask (or a halftone mask), wherein the mask is a mask or a mask, and the halftone mask is a multi-level mask or semi-transparent. Membrane mask etching method, the specific steps should be after the deep and shallow holes are engraved, coated with photoresist, (there is no film formation and the photoresist is directly coated because the film has been formed before), using mask ( Or halftone mask) exposing the pattern of the first or second holes on the photoresist, then developing, and then etching the unprotected film from which the photoresist is developed, the first or second holes are formed, and then The photoresist is peeled off, and then the next layer (such as the pixel electrode layer) is formed. Since the second insulating layer needs to etch the deep and shallow holes, the second hole cannot be shallow and shallow if no other metal layer is inserted as a barrier. The holes are etched together, and after the deep and shallow holes have been carved, another mask is used to make the second hole. The above process is performed, and only the film formation is omitted. The so-called second hole is a relatively deep and shallow hole. , but the depth of expression is different, not really the hole The figure is a large piece, and the purpose of the second hole is to increase the storage capacitor Cst.

In summary, the pixel structure and the manufacturing method thereof provided by the present invention, the thickness of the first insulating layer is not less than 3000 angstroms, the distance between the first metal layer and the second metal layer is increased, and the gate source capacitance Cgs is reduced. The first insulating layer is provided with a first hole above the common electrode line, and the second insulating layer is provided with a second hole above the drain, which can increase the storage capacitor Cst, thereby reducing the gate-source capacitance. Cgs, which can increase the storage capacitor Cst, solves the problem of flicker, has a simple structure, is easy to implement, and has a good application prospect.

The basic principles, main features and advantages of the present invention have been shown and described above. It should be understood by those skilled in the art that the present invention is not limited by the foregoing embodiments, and that the present invention is only described in the foregoing description and the description of the present invention, without departing from the spirit and scope of the invention. Various changes and modifications are intended to be included within the scope of the invention as claimed. The scope of the invention is defined by the appended claims and their equivalents.

Claims

A pixel structure includes a substrate, a first metal layer, a first insulating layer, a semiconductor layer, a second metal layer, a second insulating layer, and a pixel electrode layer, which are sequentially arranged from bottom to top on the substrate, a metal layer is etched to form a gate electrode and a common electrode line, and the second metal layer is etched to form a source and a drain, wherein the first insulating layer is provided with a first portion above the common electrode line a hole, a layer of insulating material disposed between the first hole and the common electrode line; a second hole above the drain is formed on the second insulating layer to form a material of the pixel electrode layer Entering the first and second holes.
The pixel structure according to claim 1, wherein the insulating material layer is formed of a second insulating layer.
The pixel structure according to claim 1, wherein a third metal layer is further disposed between the first hole and the insulating material layer.
The pixel structure according to claim 3, wherein the first insulating layer is a two-layer structure, comprising a first lower insulating layer on the first metal layer and a first insulating layer on the first lower insulating layer An upper insulating layer, the first upper insulating layer has a thickness greater than a thickness of the first lower insulating layer, and the insulating material layer is formed by the first lower insulating layer.
The pixel structure according to claim 4, wherein the third metal layer is located between the first lower insulating layer and the first upper insulating layer, and the first hole is opened on the first upper insulating layer. Within the layer.
The pixel structure according to claim 1, wherein the first hole is formed in the first insulating layer, and the insulating material layer is a first insulating layer having a partial thickness.
The pixel structure according to claim 6, wherein the depth of the first hole is 80% or more of the thickness of the first insulating layer.
The pixel structure according to claim 6, wherein the first insulating layer is a single layer structure.
The pixel structure according to any one of claims 1 to 8, wherein the material of the pixel electrode layer is an ITO material.
The pixel structure according to any one of claims 1 to 8, wherein the first insulating layer has a thickness of not less than 3,000 angstroms.
The pixel structure according to any one of claims 1 to 8, wherein the thickness of the second insulating layer is smaller than the thickness of the first insulating layer.
A method of fabricating a pixel structure, comprising the steps of:

Step (A): depositing a first metal layer on the substrate, and etching the first metal layer to form a gate electrode and a common electrode line;

Step (B): forming a first insulating layer covering the first metal layer;

Step (C): opening a first hole above the common electrode line on the first insulating layer;

Step (D): forming a semiconductor layer on the first insulating layer;

Step (E): depositing a second metal layer on the semiconductor layer, and etching the second metal layer to form a source and a drain;

Step (F): forming a second insulating layer covering the second metal layer, and a portion of the second insulating layer enters the first hole;

Step (G): opening a second hole on the drain in the second insulating layer;

Step (H): depositing a pixel electrode layer, and a material of the pixel electrode layer enters the first hole and the second hole.
A method of fabricating a pixel structure, comprising the steps of:

Step (A): depositing a first metal layer on the substrate, and etching the first metal layer to form a gate electrode and a common electrode line;

Step (B): forming a first lower insulating layer covering the first metal layer, forming a third metal layer on the first lower insulating layer and above the common electrode line, forming the first lower insulating layer and the third a first upper insulating layer on the metal layer;

Step (C): opening a first hole above the common electrode line on the first upper insulating layer;

Step (D): forming a semiconductor layer on the first upper insulating layer;

Step (E): depositing a second metal layer on the semiconductor layer, and etching the second metal layer to form a source and a drain;

Step (F): forming a second insulating layer covering the second metal layer;

Step (G): opening a second hole above the drain on the second insulating layer;

Step (H): depositing a pixel electrode layer, and a material of the pixel electrode layer enters the first hole and the second hole.
A method of fabricating a pixel structure, comprising the steps of:

Step (A): depositing a first metal layer on the substrate, and etching the first metal layer to form a gate electrode and a common electrode line;

Step (B): forming a first insulating layer covering the first metal layer;

Step (C): opening a first hole above the common electrode line on the first insulating layer, and a first insulating layer exists between the first hole and the common electrode line;

Step (D): forming a semiconductor layer on the first insulating layer;

Step (E): depositing a second metal layer on the semiconductor layer, and etching the second metal layer to form a source and a drain;

Step (F): forming a second insulating layer covering the second metal layer;

Step (G): opening a second hole above the drain on the second insulating layer;

Step (H): depositing a pixel electrode layer, and the material of the pixel electrode layer enters the first hole and the second hole.