CN107085334A - A kind of dot structure and its manufacture method - Google Patents
A kind of dot structure and its manufacture method Download PDFInfo
- Publication number
- CN107085334A CN107085334A CN201710172813.2A CN201710172813A CN107085334A CN 107085334 A CN107085334 A CN 107085334A CN 201710172813 A CN201710172813 A CN 201710172813A CN 107085334 A CN107085334 A CN 107085334A
- Authority
- CN
- China
- Prior art keywords
- insulating barrier
- metal layer
- hole
- layer
- dot structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 230000004888 barrier function Effects 0.000 claims abstract description 130
- 239000002184 metal Substances 0.000 claims abstract description 97
- 239000000463 material Substances 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 239000004065 semiconductor Substances 0.000 claims abstract description 20
- 239000010410 layer Substances 0.000 claims description 131
- 238000000151 deposition Methods 0.000 claims description 6
- 238000009413 insulation Methods 0.000 claims description 3
- 239000002356 single layer Substances 0.000 claims description 3
- 238000003860 storage Methods 0.000 abstract description 12
- 238000010276 construction Methods 0.000 abstract description 4
- 238000005530 etching Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136213—Storage capacitors associated with the pixel electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Mathematical Physics (AREA)
- Optics & Photonics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses a kind of dot structure and its manufacture method, dot structure includes substrate, the first metal layer being from bottom to top sequentially distributed on the substrate, the first insulating barrier, semiconductor layer, second metal layer, the second insulating barrier, pixel electrode layer, the first metal layer etches to form grid and public electrode wire, second metal layer etches to form source electrode and drain electrode, the first hole above public electrode wire is offered on first insulating barrier, the part of the second insulating barrier enters in first hole；The second hole above drain electrode is offered on second insulating barrier, the ITO materials for forming pixel electrode layer enter in the first hole and the second hole.The present invention can reduce gate-source capacitance Cgs, can increase storage capacitance Cst again, so as to solve flicker（flicker）The problem of, simple in construction, technique is easily realized, is had a good application prospect.
Description
Technical field
The present invention relates to technical field of liquid crystal display, and in particular to a kind of dot structure and its manufacture method.
Background technology
In the conventional pixel designs of available liquid crystal product, gate-source capacitance Cgs is larger, for convenience of description, with most simple
TN pattern a-Si 5Mask techniques exemplified by, as shown in figure 1, first layer metal layer 101 and the overlapping face of second layer metal layer 102
Product can cause leaping voltage than larger and in small distance（feed through）Voltage △ Vp can be than larger, △ Vp ≈ [Cgs/
（Cst+Clc）]*（Vgh-Vgl）, wherein, Cst is that storage capacitance, Clc are liquid crystal capacitance, Vgh and Vgl be grid level high voltage and
Grid low-voltage, in the case that vacuum electrode voltage △ Vp are larger, can increase LCD screen and flash（flicker）Wind
Danger, influences the normal display of LCD screen.
At present, △ Vp can be reduced by reducing gate-source capacitance Cgs, but often storage capacitance Cst also can and then reduce,
△ Vp can not be effectively reduced, then how while gate-source capacitance Cgs is reduced, it is ensured that storage capacitance Cst is constant or even increases
Greatly, it is current urgent problem.
The content of the invention
The purpose of the present invention be overcome in the prior art LCD screen in the presence of flashing（flicker）Risk.This hair
The dot structure and its manufacture method of bright offer, the thickness of the first insulating barrier are not less than 3000 angstroms, can increase the first metal layer, the
The distance between two metal levels, reduce and are offered on gate-source capacitance Cgs, the first insulating barrier above the public electrode wire
The second hole above the drain electrode is offered on first hole, the second insulating barrier, by increasing capacitance it is possible to increase storage capacitance Cst, can subtracted
Small gate-source capacitance Cgs, can increase storage capacitance Cst again, so as to solve flicker（flicker）The problem of, simple in construction, technique is held
Easily realize, have a good application prospect.
In order to achieve the above object, the technical solution adopted in the present invention is：
A kind of dot structure, including substrate, the first metal layer being from bottom to top sequentially distributed on the substrate, the first insulation
Layer, semiconductor layer, second metal layer, the second insulating barrier, pixel electrode layer, the first metal layer etch to form grid and public
Electrode wires, the second metal layer etches to form source electrode and drain electrode, is offered on first insulating barrier positioned at the common electrical
The first hole above polar curve, the part of second insulating barrier enters in first hole；Position is offered on second insulating barrier
The second hole above the drain electrode, the ITO materials for forming the pixel electrode layer enter in first hole and the second hole.
A kind of foregoing dot structure, the thickness of first insulating barrier is not less than 3000 angstroms.
A kind of foregoing dot structure, the thickness of second insulating barrier is less than the thickness of first insulating barrier.
Foregoing dot structure, first insulating barrier is single layer structure.
In addition, also there is a kind of dot structure, including substrate, be from bottom to top sequentially distributed first on the substrate
Metal level, the first insulating barrier, semiconductor layer, second metal layer, the second insulating barrier, pixel electrode layer, the first metal layer are carved
Erosion forms grid and public electrode wire, and the second metal layer etches to form source electrode and drain electrode, is opened up on first insulating barrier
There is the first hole above the public electrode wire, and the 3rd metal level be provided between first hole, public electrode wire,
The second hole above the drain electrode is offered on second insulating barrier, the ITO materials for forming the pixel electrode layer enter
Enter in first hole and the second hole.
A kind of foregoing dot structure, the thickness of first insulating barrier is not less than 3000 angstroms.
A kind of foregoing dot structure, first insulating barrier is double-decker, including the on the first metal layer
Once insulating barrier and on first time insulating barrier first on insulating barrier, the thickness of insulating barrier is more than on described first
The thickness of first time insulating barrier.
A kind of foregoing dot structure, the 3rd metal level be located at first time insulating barrier, on first insulating barrier it
Between, first hole is opened on described first in insulating barrier.
Based on the manufacture method of above-mentioned dot structure, comprise the following steps,
Step（A）：The first metal layer is deposited on substrate, and etches to form grid and public electrode wire in the first metal layer；
Step（B）：Form the first insulating barrier of covering the first metal layer；
Step（C）：The first hole above public electrode wire is opened up on the first insulating barrier；
Step（D）：Semiconductor layer is formed on the first insulating barrier；
Step（E）：Etch to form source electrode and drain electrode in semiconductor layer depositing second metal layer, and in the second metal layer；
Step（F）：The second insulating barrier of covering second metal layer is formed, and the part of second insulating barrier enters first hole
It is interior；
Step（G）：The second hole in drain electrode is opened up in the second insulating barrier；
Step（H）：The pixel electrode layer being made up of ITO materials is deposited, and ITO materials enter first hole, the second hole, ITO
Material is electrically connected with pixel electrode layer and drain electrode.
Based on the manufacture method of above-mentioned dot structure, comprise the following steps,
Step（A）：The first metal layer is deposited on substrate, and etches to form grid and public electrode wire in the first metal layer；
Step（B）：First time insulating barrier of covering the first metal layer is formed, is formed and is located on first time insulating barrier and positioned at public affairs
The 3rd metal level above common-battery polar curve, forms insulating barrier on first be located on first time insulating barrier and the 3rd metal level；
Step（C）：The first hole above public electrode wire is opened up on insulating barrier on first；
Step（D）：Semiconductor layer is formed on insulating barrier on first；
Step（E）：Depositing second metal layer, and etch to form source electrode and drain electrode in the second metal layer on the semiconductor layer；
Step（F）：Form the second insulating barrier of covering second metal layer；
Step（G）：The second hole above drain electrode is opened up over the second dielectric；
Step（H）：The pixel electrode layer being made up of ITO materials is deposited, and ITO materials enter first hole, the second hole, ITO
Material is electrically connected with pixel electrode layer and drain electrode.
The beneficial effects of the invention are as follows：Dot structure and its manufacture method that the present invention is provided, the thickness of the first insulating barrier
Not less than 3000 angstroms, the distance between the first metal layer, second metal layer can be increased, reduce gate-source capacitance Cgs, the first insulating barrier
On offer the first hole above the public electrode wire, offer on the second insulating barrier above the drain electrode
Two holes, by increasing capacitance it is possible to increase storage capacitance Cst, can reduce gate-source capacitance Cgs, can increase storage capacitance Cst again, so as to solve flicker
（flicker）The problem of, simple in construction, technique is easily realized, is had a good application prospect.
Brief description of the drawings
Fig. 1 is the schematic diagram of existing TN patterns a-Si 5Mask technique dot structures；
Fig. 2 is the schematic diagram of present invention pixel structure first embodiment；
Fig. 3 is the top view of the first hole position in first embodiment of the invention；
Fig. 4 is the schematic diagram of present invention pixel structure second embodiment；
Fig. 5 is the top view of the 3rd metal level in second embodiment of the invention.
The implication marked in accompanying drawing is as follows：
101：First layer metal layer；102：Second layer metal layer；201：Substrate；202：The first metal layer；2021：Grid；2022：
Public electrode wire；203：First insulating barrier；2031：First time insulating barrier；2032：Insulating barrier on first；204：Semiconductor layer；
205：Second metal layer；2051：Source electrode；2052：Drain electrode；206：Second insulating barrier；207：Pixel electrode layer；208：3rd metal
Layer；209：First hole；210：Second hole.
Embodiment
Below in conjunction with Figure of description, the present invention is further illustrated.
As shown in Figures 2 and 3, dot structure of the invention, first embodiment, including substrate 201, positioned at the substrate 201
On the first metal layer 202 being from bottom to top sequentially distributed, the first insulating barrier 203, semiconductor layer 204, second metal layer 205,
Second insulating barrier 206, pixel electrode layer 207, the etching of the first metal layer 202 form grid 2021 and public electrode wire 2022, the
Two metal levels 205 etching is formed to be offered positioned at public electrode wire 2022 on source electrode 2051 and drain electrode 2052, the first insulating barrier 203
First hole 209 of top, the part of the second insulating barrier enters in first hole 209；Offered on second insulating barrier 206 positioned at leakage
Second hole 210 of the top of pole 2052, the ITO materials for forming pixel electrode layer 207 enter in the first hole 209 and the second hole 210,
ITO materials can make pixel electrode layer 207 and drain electrode 2052 realize electric connection.
The thickness of first insulating barrier 203 be not less than 3000 angstroms, angstrom be long measure, 1 angstrom=10^ (- 10) rice, and
The thickness of second insulating barrier 206 is less than the thickness of first insulating barrier 203, not less than the first insulating barrier of 3000 angstroms of thickness
203, by increasing capacitance it is possible to increase the distance between the first metal layer 202, second metal layer 205, so as to reduce gate-source capacitance Cgs, first
The first hole 209 positioned at the top of public electrode wire 2022 is offered on insulating barrier 203, offers and is located on the second insulating barrier 206
Second hole 210 of the top of drain electrode 2052, by increasing capacitance it is possible to increase storage capacitance Cst, according to vacuum electrode voltage △ Vp ≈ Cgs/（Cst+
Clc）, vacuum electrode voltage △ Vp can be reduced, flashed so as to reduce LCD screen（flicker）Risk, it is ensured that liquid
The normal display of brilliant screen.
First insulating barrier 203 described in first embodiment is single layer structure.
The manufacture method of the dot structure of the first embodiment, comprises the following steps,
Step（A）：The first metal layer 202 is deposited on substrate 201, and grid 2021 is formed in the first metal layer 202 etching
With public electrode wire 2022；
Step（B）：The first insulating barrier 203 of covering the first metal layer 202 is formed, thickness is not less than 3000 angstroms；
Step（C）：The first hole 209 positioned at the top of public electrode wire 2022 is opened up on the first insulating barrier 203；
Step（D）：Semiconductor layer 204 is formed on the first insulating barrier 203；
Step（E）：Source electrode is formed in the depositing second metal layer 205 of semiconductor layer 204, and in the second metal layer 205 etching
2051 and drain electrode 2052；
Step（F）：The second insulating barrier 206 of covering second metal layer 205 is formed, and the part of second insulating barrier 206 enters
In first hole 209, and the thickness of the part of the second insulating barrier 206 entered in the first hole 209 is less than the first insulating barrier 203
Thickness；
Step（G）：The second hole 210 in drain electrode 2052 is opened up in the second insulating barrier 206；
Step（H）：The pixel electrode layer 207 being made up of ITO materials is deposited, and ITO materials enter the first hole 209, the second hole
210, ITO materials are electrically connected with pixel electrode layer 207 and drain electrode 2052.
As shown in Figures 4 and 5, dot structure of the invention, second embodiment, including substrate 201, positioned at the substrate 201
On the first metal layer 202 being from bottom to top sequentially distributed, the first insulating barrier 203, semiconductor layer 204, second metal layer 205,
Second insulating barrier 206, pixel electrode layer 207, the etching of the first metal layer 202 form grid 2021 and public electrode wire 2022, the
Two metal levels 205 etching is formed to be offered positioned at public electrode wire 2022 on source electrode 2051 and drain electrode 2052, the first insulating barrier 203
First hole 209 of top, and the 3rd metal level 208, the second insulating barrier are provided between the first hole 209, public electrode wire 2022
The second hole 210 positioned at the top of drain electrode 2052 is offered on 206, the ITO materials for forming pixel electrode layer 207 enter the first hole
209 and second in hole 210, and ITO materials can be realized pixel electrode layer 207 and drain electrode 2052 to be electrically connected with.
The thickness of first insulating barrier 203 is not less than 3000 angstroms, and the first insulating barrier 203 is double-decker, including position
In insulation on first time insulating barrier 2031 on the first metal layer 202 and first on first time insulating barrier 2031
The thickness of insulating barrier 2032 is more than the thickness of first time insulating barrier 2031 on layer 2032, and first, since it is desired that being opened up thereon
First hole 209, the 3rd metal level 208 is located on first time insulating barrier 2031, first between insulating barrier 2032, and the first hole 209 is opened
It is located on described first in insulating barrier 2031, not less than the first insulating barrier 203 of 3000 angstroms of thickness, by increasing capacitance it is possible to increase the first metal layer
202nd, the distance between second metal layer 205, position is offered so as to reduce on gate-source capacitance Cgs, first on insulating barrier 2032
The second hole positioned at the top of drain electrode 2052 is offered on the first hole 209, the second insulating barrier 206 in the top of public electrode wire 2022
210, by increasing capacitance it is possible to increase storage capacitance Cst, according to vacuum electrode voltage △ Vp ≈ Cgs/（Cst+Clc）, vacuum electrode can be reduced
Voltage △ Vp, flash so as to reduce LCD screen（flicker）Risk, it is ensured that the normal display of LCD screen.
The manufacture method of the dot structure of the second embodiment, comprises the following steps,
Step（A）：The first metal layer 202 is deposited on substrate 201, and grid 2021 is formed in the first metal layer 202 etching
With public electrode wire 2022；
Step（B）：First time insulating barrier 2031 of covering the first metal layer 202 is formed, is formed and is located at first time insulating barrier
On 2031 and positioned at the 3rd metal level 208 of the top of public electrode wire 2022, formed positioned at first time insulating barrier 2031 and the
On three metal levels 2022 first on insulating barrier 2032；
Step（C）：The first hole 209 positioned at the top of public electrode wire 2022 is opened up on insulating barrier 2032 on first；
Step（D）：Semiconductor layer 204 is formed on insulating barrier 2032 on first；
Step（E）：The depositing second metal layer 205 on semiconductor layer 204, and form source electrode in the second metal layer 205 etching
2051 and drain electrode 2052；
Step（F）：Form the second insulating barrier 206 of covering second metal layer 205；
Step（G）：The second hole 210 positioned at the top of drain electrode 2052 is opened up on the second insulating barrier 206；
Step（H）：The pixel electrode layer 207 being made up of ITO materials is deposited, and ITO materials enter first hole 209, second
Hole 210, ITO materials are electrically connected with pixel electrode layer 207 and drain electrode 2052.
In summary, the present invention is provided dot structure and its manufacture method, the thickness of the first insulating barrier are not less than 3000
Angstrom, the distance between the first metal layer, second metal layer can be increased, reduce and offer position on gate-source capacitance Cgs, the first insulating barrier
The second hole above the drain electrode is offered on the first hole, the second insulating barrier above the public electrode wire, can
Increase storage capacitance Cst, gate-source capacitance Cgs can be reduced, storage capacitance Cst can be increased again, so as to solve flicker（flicker）
The problem of, simple in construction, technique is easily realized, is had a good application prospect.
General principle, principal character and the advantage of the present invention has been shown and described above.The technical staff of the industry should
Understand, the present invention is not limited to the above embodiments, the original for simply illustrating the present invention described in above-described embodiment and specification
Reason, without departing from the spirit and scope of the present invention, various changes and modifications of the present invention are possible, these changes and improvements
It all fall within the protetion scope of the claimed invention.The claimed scope of the invention is by appended claims and its equivalent circle
It is fixed.
Claims (10)
1. a kind of dot structure, including it is substrate, the first metal layer being from bottom to top sequentially distributed on the substrate, first exhausted
Edge layer, semiconductor layer, second metal layer, the second insulating barrier, pixel electrode layer, the first metal layer etch to form grid and public affairs
Common-battery polar curve, the second metal layer etches to form source electrode and drain electrode, it is characterised in that：Position is offered on first insulating barrier
The first hole above the public electrode wire, the part of second insulating barrier enters in first hole；Second insulation
Offer the second hole above the drain electrode on layer, formed the pixel electrode layer ITO materials enter first hole and
In second hole.
2. a kind of dot structure according to claim 1, it is characterised in that：The thickness of first insulating barrier is not less than
3000 angstroms.
3. a kind of dot structure according to claim 1 or 2, it is characterised in that：The thickness of second insulating barrier is less than
The thickness of first insulating barrier.
4. dot structure according to claim 1 or 2, it is characterised in that：First insulating barrier is single layer structure.
5. a kind of dot structure, including it is substrate, the first metal layer being from bottom to top sequentially distributed on the substrate, first exhausted
Edge layer, semiconductor layer, second metal layer, the second insulating barrier, pixel electrode layer, the first metal layer etch to form grid and public affairs
Common-battery polar curve, the second metal layer etches to form source electrode and drain electrode, it is characterised in that：Position is offered on first insulating barrier
The 3rd metal level is provided between the first hole above the public electrode wire, and first hole, public electrode wire, it is described
The second hole above the drain electrode is offered on second insulating barrier, the ITO materials for forming the pixel electrode layer enter institute
State in the first hole and the second hole.
6. a kind of dot structure according to claim 5, it is characterised in that：The thickness of first insulating barrier is not less than
3000 angstroms.
7. a kind of dot structure according to claim 5 or 6, it is characterised in that：First insulating barrier is double-decker,
Including first time insulating barrier on the first metal layer and on first time insulating barrier first on insulating barrier, institute
The thickness for stating insulating barrier on first is more than the thickness of first time insulating barrier.
8. a kind of dot structure according to claim 7, it is characterised in that：3rd metal level is located under described first
Insulating barrier, on first between insulating barrier, first hole is opened on described first in insulating barrier.
9. the manufacture method based on the dot structure described in claim any one of 1-4, it is characterised in that：Comprise the following steps,
Step（A）：The first metal layer is deposited on substrate, and etches to form grid and public electrode wire in the first metal layer；
Step（B）：Form the first insulating barrier of covering the first metal layer；
Step（C）：The first hole above public electrode wire is opened up on the first insulating barrier；
Step（D）：Semiconductor layer is formed on the first insulating barrier；
Step（E）：Etch to form source electrode and drain electrode in semiconductor layer depositing second metal layer, and in the second metal layer；
Step（F）：The second insulating barrier of covering second metal layer is formed, and the part of second insulating barrier enters first hole
It is interior；
Step（G）：The second hole in drain electrode is opened up in the second insulating barrier；
Step（H）：The pixel electrode layer being made up of ITO materials is deposited, and ITO materials enter first hole and the second hole, ITO
Material is electrically connected with pixel electrode layer and drain electrode.
10. the manufacture method based on the dot structure described in claim any one of 5-8, it is characterised in that：Comprise the following steps,
Step（A）：The first metal layer is deposited on substrate, and etches to form grid and public electrode wire in the first metal layer；
Step（B）：First time insulating barrier of covering the first metal layer is formed, is formed and is located on first time insulating barrier and positioned at public affairs
The 3rd metal level above common-battery polar curve, forms insulating barrier on first be located on first time insulating barrier and the 3rd metal level；
Step（C）：The first hole above public electrode wire is opened up on insulating barrier on first；
Step（D）：Semiconductor layer is formed on insulating barrier on first；
Step（E）：Depositing second metal layer, and etch to form source electrode and drain electrode in the second metal layer on the semiconductor layer；
Step（F）：Form the second insulating barrier of covering second metal layer；
Step（G）：The second hole above drain electrode is opened up over the second dielectric；
Step（H）：The pixel electrode layer being made up of ITO materials is deposited, and ITO materials enter first hole and the second hole, ITO
Material is electrically connected with pixel electrode layer and drain electrode.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710172813.2A CN107085334A (en) | 2017-03-22 | 2017-03-22 | A kind of dot structure and its manufacture method |
| PCT/CN2018/072781 WO2018171311A1 (en) | 2017-03-22 | 2018-01-16 | Pixel structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710172813.2A CN107085334A (en) | 2017-03-22 | 2017-03-22 | A kind of dot structure and its manufacture method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107085334A true CN107085334A (en) | 2017-08-22 |
Family
ID=59615096
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710172813.2A Pending CN107085334A (en) | 2017-03-22 | 2017-03-22 | A kind of dot structure and its manufacture method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107085334A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018171311A1 (en) * | 2017-03-22 | 2018-09-27 | 南京中电熊猫平板显示科技有限公司 | Pixel structure and manufacturing method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1183570A (en) * | 1996-11-26 | 1998-06-03 | 三星电子株式会社 | Liquid crystal display using organic insulating material and manufacturing methods thereof |
| CN1716062A (en) * | 2004-06-30 | 2006-01-04 | Lg.菲利浦Lcd株式会社 | Method for producing array board of liquid crystal display device |
| CN101236932A (en) * | 2008-03-07 | 2008-08-06 | 上海广电光电子有限公司 | Thin film transistor array base plate making method |
| US20110149183A1 (en) * | 2009-12-17 | 2011-06-23 | Au Optronics Corporation | Liquid crystal display |
| CN105051596A (en) * | 2013-03-27 | 2015-11-11 | 株式会社半导体能源研究所 | Display device and electronic device |
-
2017
- 2017-03-22 CN CN201710172813.2A patent/CN107085334A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1183570A (en) * | 1996-11-26 | 1998-06-03 | 三星电子株式会社 | Liquid crystal display using organic insulating material and manufacturing methods thereof |
| CN1716062A (en) * | 2004-06-30 | 2006-01-04 | Lg.菲利浦Lcd株式会社 | Method for producing array board of liquid crystal display device |
| CN101236932A (en) * | 2008-03-07 | 2008-08-06 | 上海广电光电子有限公司 | Thin film transistor array base plate making method |
| US20110149183A1 (en) * | 2009-12-17 | 2011-06-23 | Au Optronics Corporation | Liquid crystal display |
| CN105051596A (en) * | 2013-03-27 | 2015-11-11 | 株式会社半导体能源研究所 | Display device and electronic device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018171311A1 (en) * | 2017-03-22 | 2018-09-27 | 南京中电熊猫平板显示科技有限公司 | Pixel structure and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104393000B (en) | A kind of array substrate and preparation method thereof, display device | |
| CN110459571A (en) | A kind of array substrate, the production method of el display device and array substrate | |
| CN108470717A (en) | Array substrate and preparation method thereof, display panel and display device | |
| CN105117088B (en) | A kind of touch-control display panel and preparation method thereof, driving method | |
| CN109742113A (en) | A kind of array substrate, preparation method and relevant apparatus | |
| CN109326609A (en) | A kind of array substrate and preparation method thereof | |
| CN104345511B (en) | Dot structure and its manufacture method, display panel | |
| CN104638017B (en) | Thin film transistor (TFT), dot structure and preparation method thereof, array base palte, display device | |
| CN104280951A (en) | Array substrate, manufacturing method thereof, and display device | |
| CN103681488A (en) | Array substrate, manufacturing method thereof and display device | |
| CN107845674A (en) | Thin film transistor (TFT) and preparation method thereof and array base palte | |
| CN102945846B (en) | Array base palte and manufacture method, display unit | |
| CN105655405B (en) | Pixel structure, manufacturing method thereof and thin film transistor | |
| CN108831302A (en) | Display panel and display device | |
| CN105702687A (en) | TFT (Thin Film Transistor) substrate and manufacturing method thereof | |
| CN106783896A (en) | A kind of array base palte, display panel and display device | |
| CN106444198A (en) | TFT substrate and manufacturing method and liquid crystal display panel thereof | |
| CN108807547A (en) | Thin film transistor (TFT) and preparation method thereof, array substrate and preparation method thereof | |
| CN102593182A (en) | Thin film transistor structure and manufacturing method thereof | |
| CN105914229A (en) | AMOLED display substrate, manufacturing method thereof and display device | |
| CN201438464U (en) | Thin film transistor with top gate structure | |
| CN103474439B (en) | A kind of display device, array base palte and preparation method thereof | |
| CN103278989B (en) | A kind of display panel and preparation method thereof, liquid crystal display | |
| CN106783889A (en) | Display base plate and preparation method thereof, display device | |
| CN107085334A (en) | A kind of dot structure and its manufacture method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170822 |
|
| RJ01 | Rejection of invention patent application after publication |