CN109326609A - A kind of array substrate and preparation method thereof - Google Patents
A kind of array substrate and preparation method thereof Download PDFInfo
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- CN109326609A CN109326609A CN201811061860.0A CN201811061860A CN109326609A CN 109326609 A CN109326609 A CN 109326609A CN 201811061860 A CN201811061860 A CN 201811061860A CN 109326609 A CN109326609 A CN 109326609A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
Abstract
This application discloses a kind of array substrates and preparation method thereof, the array substrate includes substrate, the first metal light-shielding pattern, buffer layer and first film transistor, first metal light-shielding pattern is formed on substrate, buffer layer is formed in the surface on buffer layer and being located at the first metal light-shielding pattern for covering the first metal light-shielding pattern, first film transistor；Wherein, first film transistor includes the first top-gated pattern, and the first top-gated pattern is electrically connected with the first metal light-shielding pattern.By the above-mentioned means, the application can prevent first film transistor to be irradiated by light, and the fever of first film transistor is reduced.
Description
Technical field
This application involves field of display technology, and in particular to a kind of array substrate and preparation method thereof.
Background technique
Since the parasitic capacitance of top-gated autoregistration oxide thin film transistor (TFT, Thin Film Transistor) is small,
Thus it is the first choice of current large scale Organic Light Emitting Diode (Organic LightEmitting Diode, OLED).
Present inventor has found in long-term R & D, common gate driving circuit (Gate on Array, GOA)
In technology, some periphery TFT need biggish driving current, to achieve the purpose that quickly to transmit signal, common implementation method
For increase TFT channel width-over-length ratio, to obtain biggish current signal.For the oxide TFT of self-alignment structure, source and drain areas
Oxide be by conductor, without grid control, TFT open when, the resistance of source and drain areas is very big, has high current to pass through
When, will cause TFT fever it is excessive, damage TFT；And oxide TFT is vulnerable to illumination effect, is easy by damaging after illumination, shadow
Ring the job stability of TFT.
Summary of the invention
The application mainly solves the problems, such as to be to provide a kind of array substrate and preparation method thereof, and the first film can be prevented brilliant
Body pipe is irradiated by light, and the fever of first film transistor is reduced.
In order to solve the above technical problems, the application is the technical solution adopted is that provide a kind of array substrate, the array substrate
It include: substrate, the first metal light-shielding pattern, buffer layer and first film transistor, the first metal light-shielding pattern is formed in substrate
On, buffer layer is formed on buffer layer for covering the first metal light-shielding pattern, first film transistor and is located at the first metal
The surface of light-shielding pattern；Wherein, first film transistor includes the first top-gated pattern, and the first top-gated pattern and the first metal hide
Light pattern electrical connection.
In order to solve the above technical problems, another technical solution that the application uses is to provide a kind of production side of array substrate
This method comprises: providing a substrate the first metal light-shielding pattern is formed on the substrate, the shape on the first metal light-shielding pattern in method
At buffer layer, first film transistor is formed on the buffer layer；Wherein, the top-gated pattern and the first metal of first film transistor
Light-shielding pattern electrical connection.
Through the above scheme, the beneficial effect of the application is: the array substrate includes the substrate being stacked, the first metal
Light-shielding pattern, buffer layer and first film transistor, first film transistor are formed on buffer layer and are located at the first metal and hide
The surface of light pattern, the first top-gated pattern in first film transistor are electrically connected with the first metal light-shielding pattern；Utilize
One metal light-shielding pattern can fall the light barrier of directive first film transistor, so that first film transistor was illuminated by the light
It influences to reduce, improves the job stability of first film transistor；And by by the first metal light-shielding pattern and the first top-gated
Pattern is electrically connected, and forms double-gate structure, and the source-drain electrode of first film transistor will receive the positive grid voltage effect of bottom gate and tire out
Meter generates carrier, so that the resistance of source-drain electrode substantially reduces, so that first film transistor fever is reduced, reduces first
The damage of thin film transistor (TFT).
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.Wherein:
Fig. 1 is the structural schematic diagram of one embodiment of array substrate provided by the present application；
Fig. 2 is the structure schematic top plan view of first film transistor in array substrate shown in FIG. 1；
Fig. 3 is the flow diagram of one embodiment of production method of array substrate provided by the present application；
Fig. 4 is the flow diagram of another embodiment of production method of array substrate provided by the present application；
Fig. 5 is the production method of top gate type thin film transistor provided by the present application.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present application, technical solutions in the embodiments of the present application carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of embodiments of the present application, rather than whole embodiments.Based on this
Embodiment in application, those of ordinary skill in the art are obtained every other under the premise of not making creative labor
Embodiment shall fall in the protection scope of this application.
Refering to fig. 1, Fig. 1 is the structural schematic diagram of one embodiment of array substrate provided by the present application, which includes:
Substrate 11, the first metal light-shielding pattern 12, buffer layer 13 and first film transistor 14.
Substrate 11 can be glass substrate, and the first metal light-shielding pattern 12 is formed on substrate 11, the first metal shading figure
Case 12 can be made of lighttight metal, and the influence to shut out the light to first film transistor 14 is gone as light shield layer, thick
Spending to beThe material of first metal light-shielding pattern 12 can be molybdenum, aluminium, copper, titanium and its alloy etc..
Buffer layer 13 covers the first metal light-shielding pattern 12, and buffer layer 13 may include at least one layer of SiOxOr SiNxFilm,
Its thickness can be
First film transistor 14 is formed on buffer layer 13, and first film transistor 14 is located at the first metal shading figure
The surface of case 12；First film transistor 14 includes the first top-gated pattern 141, and the first top-gated pattern 141 and the first metal hide
Light pattern 12 is electrically connected, as shown in Fig. 2, can be by metal routing or through-hole by the first top-gated pattern 141 and the first metal
Light-shielding pattern 12 is electrically connected.In this application, surface and underface refer to that two components are deposited under the vertical direction of substrate 11
In upper and lower relation, and projection of the two on substrate 11 is least partially overlapped.
Since the first metal light-shielding pattern 12 can fall the light barrier of directive thin film transistor (TFT) 14, so that first
The influence that thin film transistor (TFT) 14 is illuminated by the light reduces, therefore can reduce illumination to the shadow of 14 job stability of first film transistor
It rings, improves the job stability of first film transistor 14；And due to the first metal light-shielding pattern 12 and the first top-gated figure
Case 141 is electrically connected, and forms double-gate structure, when first film transistor 14 works normally, bottom gate (the first metal light-shielding pattern
12) voltage value is larger positive voltage value, and the source-drain electrode of first film transistor 14 will receive the positive grid voltage effect of bottom gate and tire out
Meter, which generates carrier, when there is high current to pass through source-drain electrode, can make the first film so that the resistance of source-drain electrode is substantially reduced
The fever of transistor 14 is reduced, and first film transistor 14 will not be caused to damage because of generating heat excessive.
With continued reference to Fig. 1 and 2, first film transistor 14 further includes first grid insulating pattern 142, the first semiconductor figure
Case 143, the first source electrode pattern 144 and the first drain pattern 145.
First semiconductor pattern 143, first grid insulating pattern 142 and the first top-gated pattern 141 are stacked in slow
It rushes on layer 13, i.e. the first semiconductor pattern 143 is set to buffer layer 13, and first grid insulating pattern 142 is set to the first half and leads
On body pattern 143, the first top-gated pattern 141 is set on first grid insulating pattern 142, and the first top-gated pattern 141,
One gate insulator pattern 142 and the first semiconductor pattern 143 are covered by interlayer insulating film 17.
First semiconductor pattern 143 be divided into the first channel region 1431 positioned at the lower section of first grid insulating pattern 142 with
And first source contact area 1432 and first drain contact region 1433 exposed from 142 two sides of first grid insulating pattern, interlayer
Insulating layer 17 is formed with the first source electrode through-hole 171 and the first drain electrode through-hole 172, the first source electrode pattern 144 and the first drain pattern
145 are formed on interlayer insulating film 14, and are electrically connected to the by the first source electrode through-hole 171 and the first drain electrode through-hole 172 respectively
One source contact area 1432 and the first drain contact region 1433.
In one embodiment, the breadth length ratio W/L of the first channel region of first film transistor 14 can be greater than 10,
For large scale TFT, it is used as the internal part of GOA.
With continued reference to Fig. 1, the array substrate is including further including the second metal light-shielding pattern 15 and the second thin film transistor (TFT) 16.
Second metal light-shielding pattern 15 is formed on substrate 11, and is covered by buffer layer 13；Second thin film transistor (TFT), 16 shape
At in the surface on buffer layer 13 and positioned at the second metal light-shielding pattern 15.
Second thin film transistor (TFT) 16 includes the second top-gated pattern 161, second grid insulating pattern 162, the second semiconductor figure
Case 163, the second source electrode pattern 164 and the second drain pattern 165.15 electricity of second source electrode pattern 164 and the second metal light-shielding pattern
Connection.
First semiconductor pattern 143 and the second semiconductor pattern 163 can be metal oxide semiconductor material, specifically
Ground, they can be indium gallium zinc oxide, indium-zinc oxide and indium gallium zinc tin oxide etc.；First semiconductor pattern 143 and
The thickness of two semiconductor patterns 163 can be
Second semiconductor pattern 163, second grid insulating pattern 162 and the second top-gated pattern dip stratum be folded be set to it is slow
It rushes on layer 13, and by interlayer insulating film covering 17.
First grid insulating pattern 142 and second grid insulating pattern 162 may include at least one layer of SiOxOr SiNxIt is thin
Film, thickness can be with
The material of first top-gated pattern 141 and the second top-gated pattern 161 can for molybdenum, aluminium, copper, titanium and its alloy etc.,
Thickness can be with
Second semiconductor pattern 163 be divided into the second channel region 1631 positioned at the lower section of second grid insulating pattern 162 with
And second source contact area 1632 and second drain contact region 1633 exposed from 162 two sides of second grid insulating pattern.
Interlayer insulating film 17 is also formed with the second source electrode through-hole 173 and the second drain electrode through-hole 174, the second source electrode pattern 164
It is formed on interlayer insulating film 17 with the second drain pattern 165, and passes through the second source electrode through-hole 173 and the second drain electrode through-hole respectively
174 are electrically connected to the second source contact area 1632 and the second drain contact region 1633, interlayer insulating film 17 and buffer layer 13 into one
Step is formed with auxiliary through hole 175, and the second source electrode pattern 164 is electrically connected to the second metal light-shielding pattern 15 by auxiliary through hole 175.
Since the second metal light-shielding pattern 15 and the second source electrode pattern 164 are electrically connected, so that the second top-gated pattern 161 divides
Parasitic capacitance not between the second source electrode pattern 164 and the second drain pattern 165 reduces, so that the second thin film transistor (TFT)
16 driving current is more stable.
Therefore, the second thin film transistor (TFT) 16 is used to be used as current drive unit, and for example, OLED luminescent layer provides driving electricity
Stream.
With continued reference to Fig. 1, the array substrate further include: third thin film transistor (TFT) 18, third thin film transistor (TFT) 18 are formed in
On buffer layer 13, and any metal light-shielding pattern is not provided in the underface of third thin film transistor (TFT) 18.
Third thin film transistor (TFT) 18 includes third top-gated pattern 181, third gate insulator pattern 182, third semiconductor figure
Case 183, third source electrode pattern 184 and third drain pattern 185.
Third semiconductor pattern 183 be divided into the third channel region 1831 positioned at the lower section of third gate insulator pattern 182 with
And the third source contact area 1832 and third drain contact region 1833 exposed from 182 two sides of third gate insulator pattern.
Interlayer insulating film 17 is formed with third source electrode through-hole 176 and third drain electrode through-hole 177,184 He of third source electrode pattern
Third drain pattern 185 is formed on interlayer insulating film 17, and passes through third source electrode through-hole 176 and third drain electrode through-hole respectively
177 are electrically connected to third source contact area 1832 and third drain contact region 1833.
Since metal light-shielding pattern being arranged not immediately below third thin film transistor (TFT) 18, the difficulty of design is reduced, and can be with
Save space；First film transistor 14, the second thin film transistor (TFT) 16, third thin film transistor (TFT) 18 and storage capacitance are (in figure not
Show) it can be used for constituting the array OLED drive of 3T1C, first film transistor 14 can be used for driving GOA circuit, and second
Thin film transistor (TFT) 16 is for driving OLED to shine, for the driving thin film transistor (TFT) of control light emission luminance and grayscale, third film
Transistor 18 can be used as regular tap use.
It is the flow diagram of one embodiment of production method of array substrate provided by the present application with 3, Fig. 3 refering to fig. 1, it should
Method includes:
Step 31: a substrate 11 is provided.
Step 32: the first metal light-shielding pattern 12 is formed on substrate 11.
One substrate 11 is provided, and substrate 11 is cleaned and toasted, then depositing a layer thickness is's
Metal, and the first metal light-shielding pattern 12 is formed by patterned process, material can be molybdenum, aluminium, copper, titanium and its alloy
Deng.
Step 33: buffer layer 13 is formed on the first metal light-shielding pattern 12.
After foring the first metal light-shielding pattern 12, at least one layer SiO is deposited on whole face substrate 11xOr SiNxIt is thin
Film, using as buffer layer 13, with a thickness ofBuffer layer 13 covers the first metal light-shielding pattern 12.
Step 34: first film transistor 14 is formed on buffer layer 13.
First film transistor 14 is made on buffer layer 13, and makes the first top-gated pattern of first film transistor 14
141 are electrically connected with the first metal light-shielding pattern 12.
It is different from the prior art, the production method for present embodiments providing a kind of array substrate, by the way that the first film is brilliant
Body pipe 14 is produced on the surface of the first metal light-shielding pattern 12, so that the influence that first film transistor 14 is illuminated by the light reduces,
Improve the job stability of first film transistor 14；And by by the first metal light-shielding pattern 12 and the first top-gated pattern
141 are electrically connected, and form double-gate structure, so that the resistance of the source-drain electrode of first film transistor 14 substantially reduces, reduce the
The fever of one thin film transistor (TFT) 14.
Refering to fig. 1 and Fig. 4, Fig. 4 be array substrate provided by the present application another embodiment of production method process signal
Figure, this method comprises:
Step 41: a substrate 11 is provided.
Step 42: the first metal light-shielding pattern 12 and the second metal light-shielding pattern 15 are formed on substrate 11.
One layer of metal layer (not shown) is deposited on substrate 11, and it is etched, and is hidden with forming the first metal
Light pattern 12 and the second metal light-shielding pattern 15.
Step 43: buffer layer 13 is formed on the first metal light-shielding pattern 12 and the second metal light-shielding pattern 15.
Buffer layer 13 is set on substrate 11, and covers the first metal light-shielding pattern 12 and the second metal light-shielding pattern
15。
Step 44: it is brilliant that first film transistor 14, the second thin film transistor (TFT) 16 and third film are formed on buffer layer 13
Body pipe 18.
After the production for completing buffer layer 13, it is brilliant that first film transistor 14, the second film are made on buffer layer 13
Body pipe 16 and third thin film transistor (TFT) 18.
First top-gated pattern 141 of first film transistor 14 is electrically connected with the first metal light-shielding pattern 12, the second film
Second source electrode pattern 164 of transistor 16 is electrically connected with the second metal light-shielding pattern 15, the underface of third thin film transistor (TFT) 18
It is not provided with any metal light-shielding pattern.
It is different from the prior art, the production method for present embodiments providing a kind of array substrate utilizes the first film crystal
Pipe 14, the second thin film transistor (TFT) 16 and third thin film transistor (TFT) 18 can be used for forming the array OLED drive of 3T1C, so that
Influence that first film transistor 14 and the second thin film transistor (TFT) 16 are illuminated by the light reduces, and improves first film transistor 14 and the
The job stability of two thin film transistor (TFT)s 16, and the fever of first film transistor 14 is made to reduce and make the second film crystal
The driving current of pipe 16 is more stable.
It is the production method of top gate type thin film transistor provided by the present application refering to Fig. 5, Fig. 5, this method is suitable for production
In above-described embodiment first to third thin film transistor (TFT).
Step 51: forming semiconductor pattern on the buffer layer.
One layer of metal oxide semiconductor material is deposited on the buffer layer as semiconductor layer, and the material of the semiconductor layer can
To be indium gallium zinc oxide, indium-zinc oxide and indium gallium zinc tin oxide etc., with a thickness ofThen partly to this
Conductor layer is etched, to form semiconductor pattern.
Step 52: gate insulating layer is formed on semiconductor pattern.
At least one layer SiO is deposited on semiconductor patternxOr SiNxFilm, using as gate insulating layer, thickness
Step 53: top-gated pattern is formed on gate insulating layer.
Gate insulating layer deposit one layer of metal as gate metal layer, the gate metal layer include molybdenum, aluminium, copper, titanium and
Its alloy, thickness can beWherein, the top-gated pattern of first film transistor and the first metal shading figure
Case is electrically connected, and can make its connection by the way that through-hole is arranged.
Step 54: being that exposure mask patterns gate insulating layer using top-gated pattern, to form gate insulator pattern.
Using yellow light process, top-gated pattern is first etched, recycling top-gated pattern is autoregistration, gate insulating layer is etched,
So that gate insulator pattern is arranged in the lower section of top-gated pattern, the gate insulating layer in remaining region is etched.
Step 55: conductor processing is carried out to semiconductor pattern using top-gated pattern and gate insulator pattern as exposure mask, so that
It obtains semiconductor pattern and forms the channel region and the source electrode exposed from gate insulator pattern two sides being located at below gate insulator pattern
Contact zone and drain contact region.
Plasma treatment is carried out to semiconductor pattern, i.e. progress ion doping, so that not by top-gated pattern and gate insulator
Resistance is substantially reduced the semiconductor pattern of pattern covering after the process, forms source contact area and drain contact region, grid are exhausted
The semiconductor pattern of edge pattern covering is not processed, characteristic of semiconductor is kept, as channel region.
Furthermore, it is possible to deposit at least one layer SiO on top-gated patternxOr SiNxFilm, to form the interlayer of covering buffer layer
Insulating layer, with a thickness ofAnd it is opened in the region for corresponding to source contact area and drain contact region
Hole, to form source electrode through-hole and drain electrode through-hole.
One layer of metal is deposited on interlayer insulating film as source-drain electrode metal layer, the material of the source-drain electrode metal layer can be
Molybdenum, aluminium, copper, titanium and its alloy, with a thickness ofThen it is patterned, to form source electrode pattern and drain electrode
Pattern, and it connect source electrode pattern and drain pattern with source contact area and drain contact region.
In addition, in the production process, the top-gated pattern of first film transistor and the first metal light-shielding pattern are electrically connected
It connects, and the source electrode pattern of the second thin film transistor (TFT) and the second metal light-shielding pattern is electrically connected.
By making first film transistor, the second thin film transistor (TFT) and third thin film transistor (TFT) on the buffer layer, and will
First metal light-shielding pattern and the top-gated pattern of first film transistor are electrically connected, and form double-gate structure, and it is thin to reduce first
The fever of film transistor reduces the damage of first film transistor；And by by the source electrode pattern of the second thin film transistor (TFT) and
Two metal light-shielding patterns are electrically connected, so that the parasitic capacitance of the second thin film transistor (TFT) reduces, enable to the second film crystal
The driving current of pipe is more stable.
The above is only embodiments herein, are not intended to limit the scope of the patents of the application, all to be said using the application
Equivalent structure or equivalent flow shift made by bright book and accompanying drawing content is applied directly or indirectly in other relevant technology necks
Domain similarly includes in the scope of patent protection of the application.
Claims (10)
1. a kind of array substrate, which is characterized in that the array substrate includes:
Substrate；
First metal light-shielding pattern, is formed on the substrate；
Buffer layer, for covering the first metal light-shielding pattern；
First film transistor is formed on the buffer layer and is located at the surface of the first metal light-shielding pattern；
Wherein, the first film transistor includes the first top-gated pattern, and the first top-gated pattern and first metal hide
Light pattern electrical connection.
2. array substrate according to claim 1, which is characterized in that the first film transistor further comprises first
Semiconductor pattern, first grid insulating pattern, the first source electrode pattern and the first drain pattern, wherein the first semiconductor figure
Case, the first grid insulating pattern and the stacking of the first top-gated pattern are set on the buffer layer, and by interlayer insulating film
Covering, first semiconductor pattern are divided into the first channel region below the first grid insulating pattern and from institutes
First grid insulating pattern two sides exposed the first source contact area and the first drain contact region are stated, the interlayer insulating film is formed
There are the first source electrode through-hole and the first drain electrode through-hole, the first source electrode pattern and the first drain pattern are formed in the layer insulation
First source contact area and first are electrically connected on layer and respectively by the first source electrode through-hole and the first drain electrode through-hole
Drain contact region.
3. array substrate according to claim 2, which is characterized in that the array substrate further comprises:
Second metal light-shielding pattern, is formed on the substrate, and is covered by the buffer layer；
Second thin film transistor (TFT) is formed on the buffer layer and is located at the surface of the second metal light-shielding pattern；
Wherein, second thin film transistor (TFT) includes the second source electrode pattern, and the second source electrode pattern and second metal hide
Light pattern electrical connection.
4. array substrate according to claim 3, which is characterized in that
Second thin film transistor (TFT) further comprises the second semiconductor pattern, second grid insulating pattern, the second top-gated pattern
With the second drain pattern, wherein second semiconductor pattern, the second grid insulating pattern and the second top-gated pattern layer
It is folded to be set on the buffer layer, and covered by interlayer insulating film, second semiconductor pattern is divided into positioned at described second
The second channel region and second source contact exposed from second grid insulating pattern two sides below gate insulator pattern
Area and the second drain contact region, the interlayer insulating film are formed with the second source electrode through-hole and the second drain electrode through-hole, second source
Pole figure case and the second drain pattern are formed on the interlayer insulating film and respectively by the second source electrode through-holes and the second leakage
Pole through-hole is electrically connected to second source contact area and the second drain contact region, the interlayer insulating film and the buffer layer into
One step is formed with auxiliary through hole, and the second source electrode pattern is electrically connected to the second metal shading figure by the auxiliary through hole
Case.
5. array substrate according to claim 3, which is characterized in that the array substrate further comprises that third film is brilliant
Body pipe, the third thin film transistor (TFT) are formed on the buffer layer and are not provided with immediately below the third thin film transistor (TFT)
Any metal light-shielding pattern.
6. array substrate according to claim 3, which is characterized in that first channel of the first film transistor
The breadth length ratio in area is greater than 10, and second thin film transistor (TFT) is used to be used as current drive unit.
7. a kind of production method of array substrate, which is characterized in that
One substrate is provided；
The first metal light-shielding pattern is formed over the substrate；
Buffer layer is formed on the first metal light-shielding pattern；
Form first film transistor on the buffer layer, wherein the top-gated pattern of the first film transistor with it is described
The electrical connection of first metal light-shielding pattern.
8. the production method of array substrate according to claim 7, which is characterized in that described to form over the substrate
The step of one metal light-shielding pattern, further comprises:
The second metal light-shielding pattern is formed over the substrate；
It is described to further comprise the step of forming first film transistor on the buffer layer:
The second thin film transistor (TFT) is formed on the buffer layer, wherein the source electrode pattern of second thin film transistor (TFT) with it is described
The electrical connection of second metal light-shielding pattern.
9. the production method of array substrate according to claim 8, which is characterized in that described to be formed on the buffer layer
The step of first film transistor, further comprises:
Third thin film transistor (TFT) is formed on the buffer layer, wherein be not provided with appointing immediately below the third thin film transistor (TFT)
What metal light-shielding pattern.
10. the production method of array substrate according to claim 9, which is characterized in that the shape on the buffer layer
Include: at the step of first film transistor
Semiconductor pattern is formed on the buffer layer；
Gate insulating layer is formed on the semiconductor pattern；
Top-gated pattern is formed on the gate insulating layer；
It is that exposure mask patterns the gate insulating layer using the top-gated pattern, to form gate insulator pattern；
Conductor processing is carried out to the semiconductor pattern using the top-gated pattern and the gate insulator pattern as exposure mask, so that
The semiconductor pattern forms the channel region being located at below the gate insulator pattern and from the gate insulator pattern two
Side exposed source contact area and drain contact region.
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