CN110718562A - Array substrate, manufacturing method thereof and display panel - Google Patents
Array substrate, manufacturing method thereof and display panel Download PDFInfo
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- CN110718562A CN110718562A CN201911021548.3A CN201911021548A CN110718562A CN 110718562 A CN110718562 A CN 110718562A CN 201911021548 A CN201911021548 A CN 201911021548A CN 110718562 A CN110718562 A CN 110718562A
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- 238000004519 manufacturing process Methods 0.000 title claims description 21
- 229910052751 metal Inorganic materials 0.000 claims abstract description 171
- 239000002184 metal Substances 0.000 claims abstract description 171
- 239000010409 thin film Substances 0.000 claims abstract description 62
- 239000010410 layer Substances 0.000 claims description 341
- 239000004065 semiconductor Substances 0.000 claims description 51
- 239000010949 copper Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 13
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- 239000002356 single layer Substances 0.000 claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
- DNAUJKZXPLKYLD-UHFFFAOYSA-N alumane;molybdenum Chemical compound [AlH3].[Mo].[Mo] DNAUJKZXPLKYLD-UHFFFAOYSA-N 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- UNQHSZOIUSRWHT-UHFFFAOYSA-N aluminum molybdenum Chemical compound [Al].[Mo] UNQHSZOIUSRWHT-UHFFFAOYSA-N 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- WUUZKBJEUBFVMV-UHFFFAOYSA-N copper molybdenum Chemical compound [Cu].[Mo] WUUZKBJEUBFVMV-UHFFFAOYSA-N 0.000 claims description 5
- BEDZDZCEOKSNMY-UHFFFAOYSA-N copper molybdenum titanium Chemical compound [Ti][Cu][Mo] BEDZDZCEOKSNMY-UHFFFAOYSA-N 0.000 claims description 5
- 229910052750 molybdenum Inorganic materials 0.000 claims description 5
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- 229910052719 titanium Inorganic materials 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 16
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
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- Thin Film Transistor (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The array substrate comprises a substrate, a first metal shading layer and a second metal shading layer which are arranged on the substrate at the same layer and at intervals, a buffer layer which is arranged on the first metal shading layer and the second metal shading layer and covers the substrate, a thin film transistor and a dielectric layer which are arranged on the buffer layer, wherein the thin film transistor is positioned above the orthographic projection area of the first metal shading layer, and the drain electrode of the thin film transistor penetrates through the dielectric layer and the buffer layer to be in contact with the second metal shading layer. Because the function of routing the metal of part in the array substrate is realized through the metal shading layer on the substrate, the risk of bright lines and bright spots on the display panel caused by short circuit of the metal routing can be reduced, and the aperture opening ratio of the display panel can be improved.
Description
Technical Field
The invention relates to the technical field of electronics, in particular to an array substrate, a manufacturing method thereof and a display panel.
Background
The resolution of the display panel is improved by reducing the metal wiring pitch of the display panel, but in the manufacturing process of the display panel, if particles or photoresist are left, the metal wiring is easily short-circuited to form bright lines or bright spots, which will affect the display effect of the display panel.
Disclosure of Invention
The invention provides an array substrate, a manufacturing method thereof and a display panel, which can solve the technical problem that in the prior art, bright lines or bright spots are formed due to short circuit of metal wires in the display panel, so that the display effect of the display panel is influenced.
The present invention provides an array substrate, including:
a substrate base plate;
the first metal shading layer and the second metal shading layer are arranged on the substrate at the same layer and interval;
the buffer layer is positioned on the first metal shading layer and the second metal shading layer and covers the substrate;
the thin film transistor and the dielectric layer are arranged on the buffer layer, and the thin film transistor is positioned above the orthographic projection area of the first metal shading layer; and
and the drain electrode of the thin film transistor penetrates through the dielectric layer and the buffer layer to be in contact with the second metal shading layer.
Optionally, the first metal shading layer and the second metal shading layer are of a single-layer structure and comprise molybdenum, aluminum, copper or titanium metal materials;
or the first metal shading layer and the second metal shading layer are of a multilayer structure, and the metal material of the multilayer structure comprises a molybdenum-aluminum-molybdenum metal layer structure, an aluminum-molybdenum metal layer structure, a molybdenum-copper metal layer structure or a molybdenum-titanium-copper metal layer structure.
Optionally, the thickness of the first metal light shielding layer and the second metal light shielding layer is 500-.
Optionally, the first metal light shielding layer and the second metal light shielding layer are obtained by the same photomask manufacturing process.
Optionally, the thin film transistor includes an oxide semiconductor, a gate insulating layer, and a gate metal layer sequentially disposed on the buffer layer, and the dielectric layer covers the gate metal layer and the buffer layer;
a source electrode of the thin film transistor penetrates through a first through hole of the dielectric layer and is connected with one side of the oxide semiconductor upper channel layer; and
the drain electrode of the thin film transistor penetrates through the second via hole of the dielectric layer and is connected with the other side of the oxide semiconductor upper channel layer, and the drain electrode of the thin film transistor also penetrates through the dielectric layer and is in contact with the second metal shading layer through the third via hole on the buffer layer.
Optionally, the thin film transistor includes a gate metal layer, a gate insulating layer and an oxide semiconductor, which are sequentially disposed on the buffer layer, and the dielectric layer covers the oxide semiconductor and the buffer layer;
a source electrode of the thin film transistor penetrates through a first through hole of the dielectric layer and is connected with one side of the oxide semiconductor upper channel layer; and
the drain electrode of the thin film transistor penetrates through the second via hole of the dielectric layer and is connected with the other side of the oxide semiconductor upper channel layer, and the drain electrode of the thin film transistor also penetrates through the dielectric layer and is in contact with the second metal shading layer through the third via hole on the buffer layer.
Further, the invention also provides a display panel, which comprises the above mentioned array substrate.
Further, the present invention also provides a method for manufacturing an array substrate, the method comprising:
providing a substrate base plate;
forming a first metal shading layer and a second metal shading layer on the substrate at intervals;
forming a buffer layer on the substrate, the first metal light-shielding layer and the second metal light-shielding layer; and
and forming a thin film transistor and a dielectric layer on the buffer layer, wherein the thin film transistor is positioned above the orthographic projection area of the first metal shading layer, and the drain electrode of the thin film transistor penetrates through the dielectric layer and the buffer layer to be in contact with the second metal shading layer.
Optionally, forming a thin film transistor and a dielectric layer on the buffer layer includes:
sequentially forming an oxide semiconductor, a grid insulating layer, a grid metal layer and a dielectric layer on the buffer layer;
forming a first via hole and a second via hole in the dielectric layer, and forming a third via hole in the dielectric layer and the buffer layer;
filling metal in the first via, the second via, and the third via of the dielectric layer; the metal filled in the first via hole and the second via hole is respectively connected with two sides of the oxide semiconductor upper channel layer to form a source electrode and a drain electrode of the thin film transistor, and the metal in the third via hole is connected with the drain electrode and is in contact with the second metal shading layer; and
a passivation layer is formed on the dielectric layer.
Optionally, forming a thin film transistor and a dielectric layer on the buffer layer includes:
sequentially forming a grid metal layer, a grid insulating layer, an oxide semiconductor and a dielectric layer on the buffer layer;
forming a first via hole and a second via hole in the dielectric layer, and forming a third via hole in the dielectric layer and the buffer layer;
filling metal in the first via, the second via, and the third via of the dielectric layer; the metal filled in the first via hole and the second via hole is respectively connected with two sides of the oxide semiconductor upper channel layer to form a source electrode and a drain electrode of the thin film transistor, and the metal in the third via hole is connected with the drain electrode and is in contact with the second metal shading layer; and
a passivation layer is formed on the dielectric layer.
The invention provides an array substrate, a manufacturing method thereof and a display panel, wherein the function of partial metal wiring in the array substrate is realized through a metal shading layer on a substrate, so that the risk of bright lines and bright spots on the display panel caused by short circuit of the metal wiring can be reduced, and the aperture opening ratio of the display panel is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
fig. 5 is a schematic flow chart illustrating a method for manufacturing an array substrate according to an embodiment of the invention;
fig. 6 is a schematic view of a scene of manufacturing an array substrate based on the method shown in fig. 5.
Detailed Description
In order to make the objects, features and advantages of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, the present invention provides an array substrate 10, which includes a substrate 11, a buffer layer 12, a dielectric layer 13, a first metal light-shielding layer k1, a second metal light-shielding layer k2, and a thin film transistor T, wherein:
the first and second metal light shielding layers k1 and k2 are formed on the substrate 11 at the same layer and at intervals, and it should be understood that the first and second metal light shielding layers k1 and k2 are formed by the same photo-masking process, and may be a single-layer structure including molybdenum (Mo), aluminum (Al), copper (Cu) or titanium (Ti) metal materials, or a multi-layer structure including a molybdenum-aluminum-molybdenum (Mo/Al/Mo) metal layer structure, an aluminum-molybdenum (Al/Mo) metal layer structure, a molybdenum-copper (Mo/Cu) metal layer structure, or a molybdenum-titanium-copper (Mo/Ti/Cu) metal layer structure, including but not limited to the above materials. It should be understood that the thicknesses of the first metal light-shielding layer k1 and the second metal light-shielding layer k2 can be 500-2000A °, in the present invention, the first metal light-shielding layer k1 has a light-shielding effect, and the second metal light-shielding layer k2 has a metal routing function.
The Buffer layer 12(Buffer layer) is located on the first metal light-shielding layer k1 and the second metal light-shielding layer k2 and covers the substrate 11, the Buffer layer 12 may be a single layer of silicon nitride (SiNx) or silicon dioxide (SiO2), or may be a double-layer film, and the thickness thereof is between 1000 and 5000A °.
The buffer layer 12 is further provided with a thin film transistor T and a dielectric layer 13, referring to fig. 1, the thin film transistor T is located above an orthographic projection area of the first metal light shielding layer k1, that is, the thin film transistor T and the first metal light shielding layer k1 at least partially overlap in the orthographic projection area of the array substrate 10.
The Thin Film Transistor T (TFT) includes an oxide semiconductor c, a gate insulating layer g, a gate metal layer f, a source electrode s1, and a drain electrode d 1.
The oxide semiconductor c, the gate insulating Layer g and the gate metal Layer f are sequentially disposed on the buffer Layer 12, the orthographic projection of the gate insulating Layer g on the oxide semiconductor c is a Channel Layer c1(Channel Layer) of the thin film transistor T, and doped regions c11 are disposed on two sides of the Channel Layer c1, in some examples, the doped region c11 may be an N-type lightly doped region c11 and an N-type heavily doped region c 11.
The Oxide semiconductor c (Oxide semiconductor) has a thickness of 100-. For the oxide semiconductor c, the oxide semiconductor c without the protection of the gate insulating layer g may be treated with plasma, and a doped region c11 is provided to serve as a source s1, a drain d 1; the oxide semiconductor c under the gate insulating layer g is not processed to serve as a channel layer c1 of the thin film transistor T.
It is understood that plasma (plasma), also known as plasma, is an ionized gaseous substance consisting of positive and negative ions generated by ionization of atoms and radicals after partial electron deprivation, and a macroscopic electrically neutral ionized gas with dimensions greater than the debye length, the movement of which is dominated by electromagnetic force and exhibits a significant collective behavior, often regarded as a fourth state in which the substance exists in addition to solid, liquid and gas.
The Gate insulating Layer G (GI) is a silicon dioxide (SiO2) film with a thickness of 1000-.
The gate metal layer f may have a thickness of 500-.
The source s1 and the drain d1 of the thin film transistor T have a thickness of 500-10000A °, and may be a single-layer structure including a molybdenum (Mo), aluminum (Al), copper (Cu) or titanium (Ti) metal material, or a multi-layer structure including a molybdenum-aluminum-molybdenum (Mo/Al/Mo) metal layer structure, an aluminum-molybdenum (Al/Mo) metal layer structure, a molybdenum-copper (Mo/Cu) metal layer structure, or a molybdenum-titanium-copper (Mo/Ti/Cu) metal layer structure, including but not limited to the above materials.
It should be understood that, in the present application, the drain d1 of the thin film transistor T is in contact with the second metal light shielding layer k2 to have a metal routing function, in addition to the function of making contact with the doped region c11 on the oxide semiconductor c to implement the drain d1 function.
The dielectric layer 13 (ILD) may be SiO2 film with a thickness of 3000-10000A °. Referring to fig. 1, the dielectric layer 13 covers the gate metal layer f, the oxide semiconductor c and the buffer layer 12, the dielectric layer 13 is further formed with a first via hole L and a second via hole M, and the dielectric layer 13 and the buffer layer 12 are formed with a third via hole N.
The drain d1 of the thin film transistor T penetrates through the dielectric layer 13 and the third via hole N on the buffer layer 12 to contact with the second metal light-shielding layer k2, and meanwhile, the drain d1 of the thin film transistor T also penetrates through the second via hole on the dielectric layer 13 to be connected with the other side (the N-type heavily doped region c11 or the N-type lightly doped region c11) of the channel layer c1 on the oxide semiconductor c. And the source s1 of the thin film transistor T penetrates through the first via hole L to be connected with one side (the N-type lightly doped region c11 or the N-type heavily doped region c11) of the channel layer c1 on the oxide semiconductor c. The drain electrode of the thin film transistor also penetrates through the dielectric layer to be in contact with a third via hole on the buffer layer and the second metal shading layer.
In this embodiment, the array substrate 10 further includes a Passivation layer 14 (PV) disposed on the dielectric layer 13, which may be a SiO2 thin film with a thickness of 1000-.
The invention provides an array substrate 10, a manufacturing method thereof and a display panel, wherein the function of partial metal wiring in the array substrate 10 is realized through a metal shading layer on a substrate 11, so that the risks of bright lines and bright spots on the display panel caused by short circuit of the metal wiring can be reduced, and the aperture opening ratio of the display panel is improved.
In other embodiments, the structural hierarchy of the oxide semiconductor c, the gate insulating layer g and the gate metal layer f in the thin film transistor T is different from the previous embodiment, please refer to fig. 2, in which the gate metal layer f, the gate insulating layer g and the oxide semiconductor c are sequentially disposed on the buffer layer 12, and the gate insulating layer g and the oxide semiconductor c are located above the gate metal layer f. The orthographic projection position of the gate insulating layer g on the oxide semiconductor c is a channel layer c1 of the thin film transistor T, and an N-type lightly doped region c11 and an N-type heavily doped region c11 are respectively arranged at two sides of the channel layer c 1.
As in the previous embodiment, in the present embodiment, the dielectric layer 13 is further provided with a first via hole L and a second via hole M, the source s1 of the thin film transistor T penetrates through the first via hole L of the dielectric layer 13 and is connected to one side (the N-type lightly doped region c11 or the N-type heavily doped region c11) of the channel layer c1 on the oxide semiconductor c, the drain d1 of the thin film transistor T penetrates through the second via hole of the dielectric layer 13 and is connected to the other side (the N-type heavily doped region c11 or the N-type lightly doped region c11) of the channel layer c1 on the oxide semiconductor c, and the dielectric layer 13 covers the oxide semiconductor c and the buffer layer 12. Similarly, the drain electrode of the thin film transistor also penetrates through the dielectric layer to be in contact with a third via hole on the buffer layer and the second metal shading layer.
Referring to fig. 3, fig. 3 shows a conventional display panel structure, which shows RGB modules on a display module, on the sides of which are drain Voltage (VDD), negative power (VSS) and probe lines (sense), signal lines data (r), data (g) and data (b) corresponding to the RGB modules, and write data (wd) and Read Data (RD). The sense line (sense) is used to sense the turn-on voltage of the TFT.
The metal wires can be seen on the upper layer visible to a display panel user, and when the metal wires are short-circuited, bright lines and bright spots are arranged on the display panel, the structure of the display panel obtained based on the array substrate 10 provided by the invention can be seen as shown in fig. 4, and some metal wires of the display panel are seen to sink and arranged on the substrate 11, so that the risk of bright lines and bright spots on the display panel caused by the short-circuited metal wires can be reduced, and the aperture ratio of the display panel is improved.
The present invention also provides a display panel including the above-mentioned array substrate 10.
The present invention also provides a method for manufacturing the array substrate 10, as shown in fig. 5, the method includes:
s501, providing a substrate 11, and forming a first metal light shielding layer k1 and a second metal light shielding layer k2 on the substrate 11 at intervals.
Referring to fig. 6, fig. 6 is a schematic view illustrating a manufacturing scenario of the array substrate 10. The first and second metal light-shielding layers k1 and k2 are deposited on the substrate 11 at the same layer and at intervals, and it should be understood that the first and second metal light-shielding layers k1 and k2 are formed by the same photo-masking process, and may be a single-layer structure including molybdenum (Mo), aluminum (Al), copper (Cu) or titanium (Ti) metal materials, or a multi-layer structure including a molybdenum-aluminum-molybdenum (Mo/Al/Mo) metal layer structure, an aluminum-molybdenum (Al/Mo) metal layer structure, a molybdenum-copper (Mo/Cu) metal layer structure, or a molybdenum-titanium-copper (Mo/Ti/Cu) metal layer structure, including but not limited to the above materials.
It should be understood that the thicknesses of the first metal light-shielding layer k1 and the second metal light-shielding layer k2 may be 500-2000A °, in this embodiment, the first metal light-shielding layer k1 has a light-shielding effect, and the second metal light-shielding layer k2 has a metal routing function.
S502, forming a buffer layer 12 on the first metal light-shielding layer k1, the second metal light-shielding layer k2, and the substrate 11.
Referring to fig. 6, a schematic view of a scenario for manufacturing the array substrate 10, the buffer layer 12 may be a single layer of silicon nitride (SiNx), silicon dioxide (SiO2), or a double layer of film with a thickness of 1000-.
S503, sequentially forming an oxide semiconductor c, a gate insulating layer g, a gate metal layer f, and a dielectric layer 13 on the buffer layer 12.
Referring to fig. 6, in a scene of manufacturing the array substrate 10, the oxide semiconductor c, the gate insulating layer g and the gate metal layer f are located above the orthographic projection area of the first metal light shielding layer k 1. The orthographic projection position of the gate insulating Layer g on the oxide semiconductor c is a Channel Layer c1c1(Channel Layer) of the thin film transistor T, and on both sides of the Channel Layer c1, there are doped regions c11c11, and in some examples, the doped regions c11c11 may be an N-type lightly doped region c11 and an N-type heavily doped region c 11.
It should be understood that, after depositing the oxide semiconductor c, the gate insulating layer g and the gate metal layer f on the buffer layer 12, the gate metal layer f and the gate insulating layer g are defined by using a photomask, specifically, a wet etching process may be used to etch the gate metal layer f, the gate metal layer f is self-aligned, the gate insulating layer g is obtained by etching, and then the dielectric layer 13 is deposited on the buffer layer 12, the oxide semiconductor c and the gate metal layer f.
And S504, forming a first via hole L and a second via hole M on the dielectric layer 13, and forming a third via hole N on the dielectric layer 13 and the buffer layer 12.
And S505, filling metal in the first via hole L, the second via hole M and the third via hole N.
And the metal filled in the first via hole and the second via hole is respectively connected with two sides of the channel layer c1 on the oxide semiconductor c. The metal filled in the third via hole N contacts the second metal light shielding layer k2, that is, the drain d1 of the thin film transistor T penetrates through the dielectric layer 13 and the third via hole N on the buffer layer 12 to contact the second metal light shielding layer k 2.
And S506, forming a passivation layer 14 on the dielectric layer 13. And then etching through holes on the passivation layer 14 at orthographic projection positions where the first via hole L and the second via hole M are located, and finally manufacturing the array substrate 10 shown in fig. 1.
The top gate thin film transistor T is manufactured by the above manufacturing method of the present invention, and in other embodiments of the present invention, a bottom gate thin film transistor T may be manufactured as follows:
s601, providing a substrate 11, and forming a first metal light shielding layer k1 and a second metal light shielding layer k2 on the substrate 11 at intervals.
S602, forming a buffer layer 12 on the first metal light-shielding layer k1, the second metal light-shielding layer k2, and the substrate 11.
S603, sequentially forming a gate metal layer f, a gate insulating layer g, and an oxide semiconductor c on the buffer layer 12, and a dielectric layer 13.
Note that, unlike the top-gate thin film transistor T, the bottom-gate thin film transistor T manufactured in the present embodiment has the structural relationship among the gate metal layer f, the gate insulating layer g, and the oxide semiconductor c as shown in fig. 2, and is located above the orthographic projection area of the first metal light shielding layer k 1. The orthographic projection position of the gate insulating Layer g on the oxide semiconductor c is a Channel Layer c1c1(Channel Layer) of the thin film transistor T, and on both sides of the Channel Layer c1, there are doped regions c11c11, and in some examples, the doped regions c11c11 may be an N-type lightly doped region c11 and an N-type heavily doped region c 11.
And S604, forming a first via hole L and a second via hole M on the dielectric layer 13, and forming a third via hole N on the dielectric layer 13 and the buffer layer 12.
And S605, filling metal in the first via hole L, the second via hole M and the third via hole N.
The metal filled in the first via hole L and the second via hole M is respectively connected to two sides of the channel layer c1 on the oxide semiconductor c. The metal filled in the third via hole N contacts the second metal light shielding layer k2, that is, the third via hole N where the drain d1 of the thin film transistor T penetrates through the dielectric layer 13 and the buffer layer 12 contacts the second metal light shielding layer k 2.
And S606, forming a passivation layer 14 on the dielectric layer 13. And then etching through holes on the passivation layer 14 at orthographic projection positions where the first via hole L and the second via hole M are located, and finally manufacturing the array substrate 10 shown in fig. 2.
In the array substrate 10 manufactured by the method provided by the invention, the function of part of the metal wires is realized by the metal light shielding layer on the substrate 11, so that the risk of bright lines and bright spots on the display panel caused by short circuit of the metal wires can be reduced, and the aperture opening ratio of the display panel can be improved.
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" indicate orientations or positional relationships based on those shown in the drawings, and are used merely for convenience of description and for simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus should not be considered as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The present disclosure provides many different embodiments or examples for implementing different configurations of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize applications of other processes and/or uses of other materials.
Claims (10)
1. An array substrate, comprising:
a substrate base plate;
the first metal shading layer and the second metal shading layer are arranged on the substrate at the same layer and interval;
the buffer layer is positioned on the first metal shading layer and the second metal shading layer and covers the substrate;
the thin film transistor and the dielectric layer are arranged on the buffer layer, and the thin film transistor is positioned above the orthographic projection area of the first metal shading layer; and
and the drain electrode of the thin film transistor penetrates through the dielectric layer and the buffer layer to be in contact with the second metal shading layer.
2. The array substrate of claim 1, wherein the first metallic light shielding layer and the second metallic light shielding layer are of a single layer structure and comprise a molybdenum, aluminum, copper or titanium metallic material;
or the first metal shading layer and the second metal shading layer are of a multilayer structure, and the metal material of the multilayer structure comprises a molybdenum-aluminum-molybdenum metal layer structure, an aluminum-molybdenum metal layer structure, a molybdenum-copper metal layer structure or a molybdenum-titanium-copper metal layer structure.
3. The array substrate of claim 1, wherein the first and second metal light-shielding layers have a thickness of 500-2000A °.
4. The array substrate of claim 1, wherein the first metallic light shielding layer and the second metallic light shielding layer are formed by a same photo-masking process.
5. The array substrate according to any one of claims 1 to 4, wherein the thin film transistor comprises an oxide semiconductor, a gate insulating layer and a gate metal layer sequentially disposed on the buffer layer, and the dielectric layer covers the gate metal layer, the buffer layer;
a source electrode of the thin film transistor penetrates through a first through hole of the dielectric layer and is connected with one side of the oxide semiconductor upper channel layer; and
the drain electrode of the thin film transistor penetrates through the second via hole of the dielectric layer and is connected with the other side of the oxide semiconductor upper channel layer, and the drain electrode of the thin film transistor also penetrates through the dielectric layer and is in contact with the second metal shading layer through the third via hole on the buffer layer.
6. The array substrate according to any one of claims 1 to 4, wherein the thin film transistor comprises a gate metal layer, a gate insulating layer and an oxide semiconductor sequentially disposed on the buffer layer, and the dielectric layer covers the oxide semiconductor and the buffer layer;
a source electrode of the thin film transistor penetrates through a first through hole of the dielectric layer and is connected with one side of the oxide semiconductor upper channel layer; and
the drain electrode of the thin film transistor penetrates through the second via hole of the dielectric layer and is connected with the other side of the oxide semiconductor upper channel layer, and the drain electrode of the thin film transistor also penetrates through the dielectric layer and is in contact with the second metal shading layer through the third via hole on the buffer layer.
7. A display panel comprising the array substrate according to any one of claims 1 to 6.
8. A manufacturing method of an array substrate is characterized by comprising the following steps:
providing a substrate base plate;
forming a first metal shading layer and a second metal shading layer on the substrate at intervals;
forming a buffer layer on the substrate, the first metal light-shielding layer and the second metal light-shielding layer; and
and forming a thin film transistor and a dielectric layer on the buffer layer, wherein the thin film transistor is positioned above the orthographic projection area of the first metal shading layer, and the drain electrode of the thin film transistor penetrates through the dielectric layer and the buffer layer to be in contact with the second metal shading layer.
9. The method of manufacturing an array substrate of claim 8, wherein the forming of the thin film transistor and the dielectric layer on the buffer layer comprises:
sequentially forming an oxide semiconductor, a grid insulating layer, a grid metal layer and a dielectric layer on the buffer layer;
forming a first via hole and a second via hole in the dielectric layer, and forming a third via hole in the dielectric layer and the buffer layer;
filling metal in the first via, the second via, and the third via of the dielectric layer; the metal filled in the first via hole and the second via hole is respectively connected with two sides of the oxide semiconductor upper channel layer to form a source electrode and a drain electrode of the thin film transistor, and the metal in the third via hole is connected with the drain electrode and is in contact with the second metal shading layer; and
a passivation layer is formed on the dielectric layer.
10. The method of manufacturing an array substrate of claim 8, wherein the forming of the thin film transistor and the dielectric layer on the buffer layer comprises:
sequentially forming a grid metal layer, a grid insulating layer, an oxide semiconductor and a dielectric layer on the buffer layer;
forming a first via hole and a second via hole in the dielectric layer, and forming a third via hole in the dielectric layer and the buffer layer;
filling metal in the first via, the second via, and the third via of the dielectric layer; the metal filled in the first via hole and the second via hole is respectively connected with two sides of the oxide semiconductor upper channel layer to form a source electrode and a drain electrode of the thin film transistor, and the metal in the third via hole is connected with the drain electrode and is in contact with the second metal shading layer; and
a passivation layer is formed on the dielectric layer.
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