US20230387321A1 - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
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- US20230387321A1 US20230387321A1 US18/448,186 US202318448186A US2023387321A1 US 20230387321 A1 US20230387321 A1 US 20230387321A1 US 202318448186 A US202318448186 A US 202318448186A US 2023387321 A1 US2023387321 A1 US 2023387321A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 68
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims description 18
- 238000000151 deposition Methods 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 15
- 239000003989 dielectric material Substances 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- XLOMVQKBTHCTTD-UHFFFAOYSA-N zinc oxide Inorganic materials [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 5
- 238000005137 deposition process Methods 0.000 claims description 4
- 239000011787 zinc oxide Substances 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 239000010408 film Substances 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229910003437 indium oxide Inorganic materials 0.000 description 3
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- QGLKJKCYBOYXKC-UHFFFAOYSA-N nonaoxidotritungsten Chemical compound O=[W]1(=O)O[W](=O)(=O)O[W](=O)(=O)O1 QGLKJKCYBOYXKC-UHFFFAOYSA-N 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 229910001930 tungsten oxide Inorganic materials 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- AZWHFTKIBIQKCA-UHFFFAOYSA-N [Sn+2]=O.[O-2].[In+3] Chemical compound [Sn+2]=O.[O-2].[In+3] AZWHFTKIBIQKCA-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- GPBUGPUPKAGMDK-UHFFFAOYSA-N azanylidynemolybdenum Chemical compound [Mo]#N GPBUGPUPKAGMDK-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- -1 tungsten nitride Chemical class 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78642—Vertical transistors
Definitions
- the invention relates to a semiconductor manufacture technique, and particularly relates to a semiconductor device and a method of manufacturing the same.
- the semiconductor device such as transistor has been developed for a long time.
- the transistor includes plane device and vertical device.
- the plane device is, for example, a thin film transistor, wherein a source electrode and a drain electrode are over a gate electrode, and the channel length (Lg) is defined by the spacing between the source electrode and the drain electrode.
- the channel length is desired to be smaller with the miniaturization of the device size, and thus the Lg of the plane device can not meet the requirement due to the resolution limitation of photolithography.
- the vertical device is, for example, a 3D transistor, wherein a vertical channel formed on the substrate, a source electrode and a drain electrode are disposed at two ends of the vertical channel, and the Lg of the vertical device is defined by the thickness of a gate electrode. Therefore, the Lg of vertical device can be made smaller.
- the process of the vertical device is more complicated than the plane device, and it is difficult in the formation and the contact for drain/source/body.
- the invention provides a method of manufacturing a semiconductor device to obtain the semiconductor device having fine channel length.
- the method of manufacturing a semiconductor device of one embodiment of the invention includes forming a first electrode layer on a substrate, and then forming a stack structure on the first electrode layer, wherein the stack structure comprises a first insulating layer, a gate electrode layer, and a second insulating layer.
- An opening is formed in the stack structure.
- a gate dielectric layer is formed on a sidewall of the opening of the stack structure, and an oxide semiconductor layer is formed in the opening, wherein the gate dielectric layer is sandwiched between the oxide semiconductor layer and the gate electrode layer.
- a second electrode layer is then formed on the stack structure to be in direct contact with the oxide semiconductor layer.
- the method further comprises patterning the second insulating layer and the gate electrode layer.
- the method further comprises respectively forming electrode contacts connecting to the first electrode layer, the gate electrode layer, and the second electrode layer.
- the step of forming the gate dielectric layer comprises conformally depositing a dielectric material layer on the stack structure and in the opening, and then etching back the dielectric material layer until the first electrode layer is exposed.
- the step of forming the stack structure comprises depositing the first insulating layer on the first electrode layer, depositing the gate electrode layer on the first insulating layer, and depositing the second insulating layer on the gate electrode layer.
- the step of forming the oxide semiconductor layer in the opening comprises blanket depositing an oxide semiconductor material to fill the opening, and then etching back the oxide semiconductor material until the stack structure is exposed.
- a method of forming the oxide semiconductor layer in the opening comprises a selective deposition process.
- a material of the oxide semiconductor layer comprises indium-gallium-zinc oxide.
- the substrate comprises a silicon-on-insulator (SOI) substrate.
- SOI silicon-on-insulator
- the invention provides a semiconductor device having a planar stack structure containing two source/drain electrodes, a gate electrode layer therebetween, and an oxide semiconductor penetrating through the gate electrode layer, it can realize fine channel length in the semiconductor device by simple process.
- FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment of the invention.
- FIG. 2 is a cross-sectional view along line II-IF of FIG. 1 .
- FIG. 3 is a schematic plan view of a semiconductor device according to a second embodiment of the invention.
- FIG. 4 is a cross-sectional view along line IV-IV′ of FIG. 3 .
- FIG. 5 A to FIG. 5 I are schematic cross-sectional views of a manufacturing process of a semiconductor device according to a third embodiment of the invention.
- FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment of the invention.
- FIG. 2 is a cross-sectional view along line II-IF of FIG. 1 .
- the semiconductor device of the first embodiment includes a substrate 100 , a first electrode layer 102 , a gate electrode layer 104 , a second electrode layer 106 , an oxide semiconductor layer 108 , a gate dielectric layer 110 , a first insulating layer 112 , and a second insulating layer 114 .
- the first electrode layer 102 is disposed on the substrate 100
- the gate electrode layer 104 is disposed on the first electrode layer 102
- the second electrode layer 106 is disposed on the gate electrode layer 104 .
- the substrate 100 may be a silicon-on-insulator (SOI) substrate or other semiconductor substrate.
- SOI silicon-on-insulator
- the gate electrode layer 104 may be made of conductive material such as indium oxide-tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium oxide, zinc oxide, or other suitable material.
- the first electrode layer 102 and the second electrode layer 106 are as a drain and a source of the semiconductor device.
- the first electrode layer 102 is a drain electrode and the second electrode layer 106 is a source electrode; alternatively, the first electrode layer 102 is a source electrode and the second electrode layer 106 is a drain electrode.
- the first electrode layer 102 and the second electrode layer 106 may be a metal film or a metal nitride film, wherein the material of the metal film is selected from Al, Cr, Cu, Ta, Ti, Mo, and W; the material of the metal nitride film is nitride of foregoing metal such as a titanium nitride film, a molybdenum nitride film, a tungsten nitride film), or the like.
- the oxide semiconductor layer 108 penetrates through the gate electrode layer 104 and is in direct contact with the first electrode layer 102 and the second electrode layer 106 , respectively.
- a material of the oxide semiconductor layer 108 includes, for example, indium-gallium-zinc oxide (IGZO) or other suitable oxide semiconductor material.
- the gate dielectric layer 110 is disposed between the gate electrode layer 104 and the oxide semiconductor layer 108
- the first insulating layer 112 is disposed between the gate electrode layer 104 and the first electrode layer 102
- the second insulating layer 114 is disposed between the gate electrode layer 104 and the second electrode layer 106 .
- the profile of the cross section of the semiconductor device is step-shaped, and thus it is beneficial to interconnection of the semiconductor device.
- an electrode contact 116 connects to the first electrode layer 102
- an electrode contact 118 connects to the gate electrode layer 104
- an electrode contact 120 connects to the second electrode layer 106 .
- Those electrode contacts 116 , 118 and 120 can be formed together using the same steps.
- the invention is not limited thereto.
- FIG. 3 is a schematic plan view of a semiconductor device according to a second embodiment of the invention, wherein the reference symbols used in the first embodiment are used to equally represent the same or similar components.
- FIG. 4 is a cross-sectional view along line IV-IV′ of FIG. 3 . The description of the same components can be derived from the first embodiment, and will not be repeated here.
- the semiconductor device of the second embodiment also includes a substrate 100 , a first electrode layer 102 , a gate electrode layer 104 , a second electrode layer 106 , an oxide semiconductor layer 108 , a gate dielectric layer 110 , a first insulating layer 112 , and a second insulating layer 114 .
- the difference between the second and the first embodiments is that the shapes of the oxide semiconductor layer 108 and the second electrode layer 106 are circular. In another embodiment, the shapes of the oxide semiconductor layer 108 and the second electrode layer 106 in the FIG. 3 may be rectangle, and so on.
- FIG. 5 A to FIG. 5 I are schematic cross-sectional views of a manufacturing process of a semiconductor device according to a third embodiment of the invention.
- a first electrode layer 502 is formed on a substrate 500 .
- the substrate 500 may be a SOI substrate or other semiconductor substrate.
- a stack structure 504 is formed on the first electrode layer 502 , wherein the stack structure 504 , for example, includes a first insulating layer 506 , a gate electrode layer 508 , and a second insulating layer 510 .
- the step of forming the stack structure 504 includes depositing the first insulating layer 506 on the first electrode layer 502 , depositing the gate electrode layer 508 on the first insulating layer 506 , and depositing the second insulating layer 510 on the gate electrode layer 508 .
- an opening 512 is formed in the stack structure 504 .
- the opening 512 may be, for example, a rectangle groove or a circular hole.
- it may conformally depositing a dielectric material layer 514 on the stack structure 504 and in the opening 512 first.
- the dielectric material layer 514 in FIG. 5 C is etched back until the first electrode layer 502 is exposed so as to form the gate dielectric layer 514 a .
- the invention is not limited thereto.
- an oxide semiconductor layer 516 is formed in the opening 512 , wherein the gate dielectric layer 514 a is sandwiched between the oxide semiconductor layer 516 and the gate electrode layer 508 .
- the step of forming the oxide semiconductor layer 516 in the opening 512 includes blanket depositing an oxide semiconductor material (not shown) to fill the opening 516 , and then etching back the oxide semiconductor material until the stack structure 504 is exposed.
- a method of forming the oxide semiconductor layer 516 in the opening 512 includes a selective deposition process.
- a material of the oxide semiconductor layer 516 includes, for example, IGZO or other suitable oxide semiconductor material.
- a second electrode layer 518 is formed on the stack structure 504 to be in direct contact with the oxide semiconductor layer 516 , wherein the method of forming the second electrode layer 518 , for example, includes a deposition process.
- a semiconductor device of the third embodiment has been manufactured in this step.
- the second electrode layer 518 is patterned to expose a portion of the stack structure 504 .
- the second insulating layer 510 and the gate electrode layer 508 are patterned, and thus the profile of the cross section of the structure in FIG. 5 H is step-shaped for the interconnection.
- the first insulating layer 506 and the first electrode layer 502 can be further patterned to expose a portion of the substrate 500 (e.g. the semiconductor device as shown in FIG. 4 ).
- electrode contacts 520 a , 520 b and 520 c are formed to connecting to the first electrode layer 502 , the gate electrode layer 508 , and the second electrode layer 518 , respectively.
- the semiconductor device comprises a semiconductor device having a planar stack structure containing two source/drain electrodes, a gate electrode layer therebetween, and an oxide semiconductor perpendicularly penetrating through the gate electrode layer, and thus the channel length (Lg) can be defined by the thickness of the gate electrode layer.
- the channel length (Lg) can be defined by the thickness of the gate electrode layer.
Abstract
A method of manufacturing a semiconductor device is provided. The method of manufacturing a semiconductor device includes forming a first electrode layer on a substrate, and then forming a stack structure on the first electrode layer, wherein the stack structure comprises a first insulating layer, a gate electrode layer, and a second insulating layer. An opening is formed in the stack structure. A gate dielectric layer is formed on a sidewall of the opening of the stack structure, and an oxide semiconductor layer is formed in the opening, wherein the gate dielectric layer is sandwiched between the oxide semiconductor layer and the gate electrode layer. A second electrode layer is then formed on the stack structure to be in direct contact with the oxide semiconductor layer.
Description
- This application is a divisional application of and claims the priority benefit of U.S. patent application Ser. No. 17/386,565, filed on Jul. 28, 2021, now allowed. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
- The invention relates to a semiconductor manufacture technique, and particularly relates to a semiconductor device and a method of manufacturing the same.
- The semiconductor device such as transistor has been developed for a long time. The transistor includes plane device and vertical device. The plane device is, for example, a thin film transistor, wherein a source electrode and a drain electrode are over a gate electrode, and the channel length (Lg) is defined by the spacing between the source electrode and the drain electrode. However, the channel length is desired to be smaller with the miniaturization of the device size, and thus the Lg of the plane device can not meet the requirement due to the resolution limitation of photolithography.
- The vertical device is, for example, a 3D transistor, wherein a vertical channel formed on the substrate, a source electrode and a drain electrode are disposed at two ends of the vertical channel, and the Lg of the vertical device is defined by the thickness of a gate electrode. Therefore, the Lg of vertical device can be made smaller. However, the process of the vertical device is more complicated than the plane device, and it is difficult in the formation and the contact for drain/source/body.
- The invention provides a method of manufacturing a semiconductor device to obtain the semiconductor device having fine channel length.
- The method of manufacturing a semiconductor device of one embodiment of the invention includes forming a first electrode layer on a substrate, and then forming a stack structure on the first electrode layer, wherein the stack structure comprises a first insulating layer, a gate electrode layer, and a second insulating layer. An opening is formed in the stack structure. A gate dielectric layer is formed on a sidewall of the opening of the stack structure, and an oxide semiconductor layer is formed in the opening, wherein the gate dielectric layer is sandwiched between the oxide semiconductor layer and the gate electrode layer. A second electrode layer is then formed on the stack structure to be in direct contact with the oxide semiconductor layer.
- In one embodiment of the invention, after the step of forming the second electrode layer, the method further comprises patterning the second insulating layer and the gate electrode layer.
- In one embodiment of the invention, after the step of forming the second electrode layer, the method further comprises respectively forming electrode contacts connecting to the first electrode layer, the gate electrode layer, and the second electrode layer.
- In one embodiment of the invention, the step of forming the gate dielectric layer comprises conformally depositing a dielectric material layer on the stack structure and in the opening, and then etching back the dielectric material layer until the first electrode layer is exposed.
- In one embodiment of the invention, the step of forming the stack structure comprises depositing the first insulating layer on the first electrode layer, depositing the gate electrode layer on the first insulating layer, and depositing the second insulating layer on the gate electrode layer.
- In one embodiment of the invention, the step of forming the oxide semiconductor layer in the opening comprises blanket depositing an oxide semiconductor material to fill the opening, and then etching back the oxide semiconductor material until the stack structure is exposed.
- In one embodiment of the invention, a method of forming the oxide semiconductor layer in the opening comprises a selective deposition process.
- In one embodiment of the invention, a material of the oxide semiconductor layer comprises indium-gallium-zinc oxide.
- In one embodiment of the invention, the substrate comprises a silicon-on-insulator (SOI) substrate.
- Based on the above, since the invention provides a semiconductor device having a planar stack structure containing two source/drain electrodes, a gate electrode layer therebetween, and an oxide semiconductor penetrating through the gate electrode layer, it can realize fine channel length in the semiconductor device by simple process.
- To make the aforementioned more comprehensible, several embodiments accompanied with drawings are described in detail as follows.
- The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure.
-
FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment of the invention. -
FIG. 2 is a cross-sectional view along line II-IF ofFIG. 1 . -
FIG. 3 is a schematic plan view of a semiconductor device according to a second embodiment of the invention. -
FIG. 4 is a cross-sectional view along line IV-IV′ ofFIG. 3 . -
FIG. 5A toFIG. 5I are schematic cross-sectional views of a manufacturing process of a semiconductor device according to a third embodiment of the invention. - Referring to the embodiments below and the accompanied drawings for a sufficient understanding of the invention. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. However, the invention may be implemented in many other different forms and should not be limited to the embodiments described hereinafter. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. In the drawings, for clarity, the elements and relative dimensions thereof may not be scaled. For easy understanding, the same elements in the following embodiments will be denoted by the same reference numerals.
-
FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment of the invention.FIG. 2 is a cross-sectional view along line II-IF ofFIG. 1 . - Referring to
FIG. 1 andFIG. 2 , the semiconductor device of the first embodiment includes asubstrate 100, afirst electrode layer 102, agate electrode layer 104, asecond electrode layer 106, anoxide semiconductor layer 108, a gatedielectric layer 110, afirst insulating layer 112, and a secondinsulating layer 114. Thefirst electrode layer 102 is disposed on thesubstrate 100, thegate electrode layer 104 is disposed on thefirst electrode layer 102, and thesecond electrode layer 106 is disposed on thegate electrode layer 104. In one embodiment, thesubstrate 100 may be a silicon-on-insulator (SOI) substrate or other semiconductor substrate. Thegate electrode layer 104 may be made of conductive material such as indium oxide-tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium oxide, zinc oxide, or other suitable material. Thefirst electrode layer 102 and thesecond electrode layer 106 are as a drain and a source of the semiconductor device. For example, thefirst electrode layer 102 is a drain electrode and thesecond electrode layer 106 is a source electrode; alternatively, thefirst electrode layer 102 is a source electrode and thesecond electrode layer 106 is a drain electrode. In one embodiment, thefirst electrode layer 102 and thesecond electrode layer 106 may be a metal film or a metal nitride film, wherein the material of the metal film is selected from Al, Cr, Cu, Ta, Ti, Mo, and W; the material of the metal nitride film is nitride of foregoing metal such as a titanium nitride film, a molybdenum nitride film, a tungsten nitride film), or the like. Theoxide semiconductor layer 108 penetrates through thegate electrode layer 104 and is in direct contact with thefirst electrode layer 102 and thesecond electrode layer 106, respectively. A material of theoxide semiconductor layer 108 includes, for example, indium-gallium-zinc oxide (IGZO) or other suitable oxide semiconductor material. The gatedielectric layer 110 is disposed between thegate electrode layer 104 and theoxide semiconductor layer 108, the firstinsulating layer 112 is disposed between thegate electrode layer 104 and thefirst electrode layer 102, and the secondinsulating layer 114 is disposed between thegate electrode layer 104 and thesecond electrode layer 106. - In the first embodiment, the profile of the cross section of the semiconductor device is step-shaped, and thus it is beneficial to interconnection of the semiconductor device. For example, an
electrode contact 116 connects to thefirst electrode layer 102, anelectrode contact 118 connects to thegate electrode layer 104, and anelectrode contact 120 connects to thesecond electrode layer 106. Thoseelectrode contacts -
FIG. 3 is a schematic plan view of a semiconductor device according to a second embodiment of the invention, wherein the reference symbols used in the first embodiment are used to equally represent the same or similar components.FIG. 4 is a cross-sectional view along line IV-IV′ ofFIG. 3 . The description of the same components can be derived from the first embodiment, and will not be repeated here. - Referring to
FIG. 3 andFIG. 4 , the semiconductor device of the second embodiment also includes asubstrate 100, afirst electrode layer 102, agate electrode layer 104, asecond electrode layer 106, anoxide semiconductor layer 108, agate dielectric layer 110, a first insulatinglayer 112, and a second insulatinglayer 114. The difference between the second and the first embodiments is that the shapes of theoxide semiconductor layer 108 and thesecond electrode layer 106 are circular. In another embodiment, the shapes of theoxide semiconductor layer 108 and thesecond electrode layer 106 in theFIG. 3 may be rectangle, and so on. -
FIG. 5A toFIG. 5I are schematic cross-sectional views of a manufacturing process of a semiconductor device according to a third embodiment of the invention. - Referring to
FIG. 5A , afirst electrode layer 502 is formed on asubstrate 500. Thesubstrate 500 may be a SOI substrate or other semiconductor substrate. - Then, referring to
FIG. 5B , astack structure 504 is formed on thefirst electrode layer 502, wherein thestack structure 504, for example, includes a first insulatinglayer 506, agate electrode layer 508, and a second insulatinglayer 510. In the embodiment, the step of forming thestack structure 504, for example, includes depositing the first insulatinglayer 506 on thefirst electrode layer 502, depositing thegate electrode layer 508 on the first insulatinglayer 506, and depositing the second insulatinglayer 510 on thegate electrode layer 508. - Thereafter, referring to
FIG. 5C , anopening 512 is formed in thestack structure 504. Theopening 512 may be, for example, a rectangle groove or a circular hole. To form a gate dielectric layer on asidewall 512 a of theopening 512, it may conformally depositing adielectric material layer 514 on thestack structure 504 and in theopening 512 first. - After that, referring to
FIG. 5D , thedielectric material layer 514 inFIG. 5C is etched back until thefirst electrode layer 502 is exposed so as to form thegate dielectric layer 514 a. However, the invention is not limited thereto. - Then, referring to
FIG. 5E , anoxide semiconductor layer 516 is formed in theopening 512, wherein thegate dielectric layer 514 a is sandwiched between theoxide semiconductor layer 516 and thegate electrode layer 508. In one embodiment, the step of forming theoxide semiconductor layer 516 in theopening 512 includes blanket depositing an oxide semiconductor material (not shown) to fill theopening 516, and then etching back the oxide semiconductor material until thestack structure 504 is exposed. In another embodiment, a method of forming theoxide semiconductor layer 516 in theopening 512 includes a selective deposition process. A material of theoxide semiconductor layer 516 includes, for example, IGZO or other suitable oxide semiconductor material. - Thereafter, referring to
FIG. 5F , asecond electrode layer 518 is formed on thestack structure 504 to be in direct contact with theoxide semiconductor layer 516, wherein the method of forming thesecond electrode layer 518, for example, includes a deposition process. A semiconductor device of the third embodiment has been manufactured in this step. - After the step shown in
FIG. 5F , there are some optional steps as follows. - Please referring to
FIG. 5G , thesecond electrode layer 518 is patterned to expose a portion of thestack structure 504. - Then, referring to
FIG. 5H , the second insulatinglayer 510 and thegate electrode layer 508 are patterned, and thus the profile of the cross section of the structure inFIG. 5H is step-shaped for the interconnection. In another embodiment, the first insulatinglayer 506 and thefirst electrode layer 502 can be further patterned to expose a portion of the substrate 500 (e.g. the semiconductor device as shown inFIG. 4 ). - Thereafter, referring to
FIG. 5I ,electrode contacts first electrode layer 502, thegate electrode layer 508, and thesecond electrode layer 518, respectively. - In summary, the semiconductor device according to the invention comprises a semiconductor device having a planar stack structure containing two source/drain electrodes, a gate electrode layer therebetween, and an oxide semiconductor perpendicularly penetrating through the gate electrode layer, and thus the channel length (Lg) can be defined by the thickness of the gate electrode layer. In other words, according to the invention, fine channel length of the semiconductor device can be accomplished by simple process.
- It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the invention covers modifications and variations provided that they fall within the scope of the following claims and their equivalents.
Claims (9)
1. A method of manufacturing a semiconductor device, comprising:
forming a first electrode layer on a substrate;
forming a stack structure on the first electrode layer, wherein the stack structure comprises a first insulating layer, a gate electrode layer, and a second insulating layer;
forming an opening in the stack structure;
forming a gate dielectric layer on a sidewall of the opening of the stack structure;
forming an oxide semiconductor layer in the opening, wherein the gate dielectric layer is sandwiched between the oxide semiconductor layer and the gate electrode layer; and
forming a second electrode layer on the stack structure to be in direct contact with the oxide semiconductor layer.
2. The method of claim 1 , wherein after the step of forming the second electrode layer further comprises: patterning the second insulating layer and the gate electrode layer.
3. The method of claim 1 , wherein after the step of forming the second electrode layer further comprises: forming a plurality of electrode contacts connecting to the first electrode layer, the gate electrode layer, and the second electrode layer respectively.
4. The method of claim 1 , wherein the step of forming the gate dielectric layer comprises:
conformally depositing a dielectric material layer on the stack structure and in the opening; and
etching back the dielectric material layer until the first electrode layer is exposed.
5. The method of claim 1 , wherein the step of forming the stack structure comprises:
depositing the first insulating layer on the first electrode layer;
depositing the gate electrode layer on the first insulating layer; and
depositing the second insulating layer on the gate electrode layer.
6. The method of claim 1 , wherein the step of forming the oxide semiconductor layer in the opening comprises:
blanket depositing an oxide semiconductor material to fill the opening; and
etching back the oxide semiconductor material until the stack structure is exposed.
7. The method of claim 1 , wherein a method of forming the oxide semiconductor layer in the opening comprises a selective deposition process.
8. The method of claim 1 , wherein a material of the oxide semiconductor layer comprises indium-gallium-zinc oxide.
9. The method of claim 1 , wherein the substrate comprises a silicon-on-insulator (SOI) substrate.
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