CN115050756A - Array substrate, display panel and preparation method thereof - Google Patents
Array substrate, display panel and preparation method thereof Download PDFInfo
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- CN115050756A CN115050756A CN202210669051.8A CN202210669051A CN115050756A CN 115050756 A CN115050756 A CN 115050756A CN 202210669051 A CN202210669051 A CN 202210669051A CN 115050756 A CN115050756 A CN 115050756A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
Abstract
The invention provides an array substrate, a display panel and a preparation method thereof. The first active pattern of the first transistor comprises a silicon semiconductor material, the second active pattern of the second transistor comprises an oxide semiconductor material, the first pole of the capacitor and the second active pattern are arranged at the same layer and at intervals, and the second pole of the capacitor is the first grid of the first transistor. By arranging the first pole and the second active pattern to be on the same layer, the mask plate adopted by the first pole of the capacitor in the prior art can be reduced, the preparation cost can be reduced, and after the first pole of the capacitor and the second active pattern are arranged on the same layer and at intervals, the electrical performance can meet the design requirements of a wearable display product.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a display panel and a preparation method of the display panel.
Background
In the conventional display panel, the array substrate is usually made of Low Temperature Polysilicon Oxide (LTPO) or Low Temperature Polysilicon (LTPS) material. However, the array substrate prepared based on the existing array substrate structure including LTPO has a complicated preparation process, and when the array substrate is applied to a wearable display product, the preparation cost is high.
Disclosure of Invention
The embodiment of the invention provides an array substrate, a display panel and a preparation method of the display panel, which can reduce the number of masks used in the preparation of the array substrate and reduce the preparation cost.
An embodiment of the invention provides an array substrate, which includes a first transistor, a second transistor and a capacitor. The array substrate includes: the semiconductor device includes a first active layer, a first gate layer, a first interlayer insulating layer, and a second active layer.
The first active layer includes a first active pattern of the first transistor including a silicon semiconductor material. The first gate layer is on the first active layer and includes a first gate of the first transistor. The first interlayer insulating layer is on the first gate layer. The second active layer is on the first interlayer insulating layer, the second active layer including an oxide semiconductor material, the second active layer including a second active pattern of the second transistor and a first electrode of the capacitor.
Wherein the first pole and the second active pattern are disposed at an interval, and the first pole overlaps the first gate to form the capacitor.
Optionally, in some embodiments of the present invention, the first gate layer further includes a shielding portion overlapping with a channel region of the second active pattern.
Optionally, in some embodiments of the present invention, the array substrate further includes a shielding layer. The shielding layer is positioned below the first active layer and comprises a first shielding part and a second shielding part. The first shielding portion overlaps with a channel region of the first active pattern, and the second shielding portion overlaps with a channel region of the second active pattern.
Optionally, in some embodiments of the present invention, the first active layer comprises a polysilicon semiconductor and the second active layer comprises indium gallium zinc oxide.
Optionally, in some embodiments of the present invention, the array substrate further includes a second gate layer, a source drain layer, and a first gate insulating layer.
The second gate layer is on the second active layer and includes a second gate of the second transistor. The source drain layer is located on the second gate layer and includes a first source and a first drain of the first transistor, and a second source and a second drain of the second transistor. The first source and the first drain are both electrically connected to the first active pattern, the second source and the second drain are both electrically connected to the second active pattern, and one of the second source and the second drain is electrically connected to the first active pattern. The first gate insulating layer is between the first gate layer and the first interlayer insulating layer.
The embodiment of the invention also provides a display panel which comprises a first transistor, a second transistor and a capacitor. The first active pattern of the first transistor comprises a silicon semiconductor material, the second active pattern of the second transistor comprises an oxide semiconductor material, and the capacitor has a first pole and a second pole.
The first pole and the second active pattern of the second transistor are arranged at the same layer and interval, and the second pole is a first grid of the first transistor.
Optionally, in some embodiments of the present invention, the display panel includes a first active layer, a first gate layer, a second active layer, and a first interlayer insulating layer.
The first active layer includes the first active pattern. The first gate layer is on the first active layer and includes the first gate. The second active layer is on the first gate layer, and includes the second active pattern and the first pole. The first interlayer insulating layer is between the first gate layer and the second active layer.
Wherein the first active layer comprises a polysilicon semiconductor material and the second active layer comprises indium gallium zinc oxide.
Optionally, in some embodiments of the present invention, the display panel further includes a first shielding portion and a second shielding portion.
The first shielding portion is positioned under the first active layer, and the first shielding portion overlaps with a channel region of the first active pattern. The second shielding portion is located under the second active layer, and the second shielding portion overlaps with a channel region of the second active pattern.
The second shielding part is at the same layer as the first shielding part or at the same layer as the first grid.
Optionally, in some embodiments of the present invention, the display panel further includes a second gate layer, a source drain layer, and a first gate insulating layer.
The second gate layer is on the second active layer and includes a second gate of the second transistor. The source drain layer is located on the second gate layer and includes a first source and a first drain of the first transistor, and a second source and a second drain of the second transistor. The first source and the first drain are both electrically connected to the first active pattern, the second source and the second drain are both electrically connected to the second active pattern, and one of the second source and the second drain is electrically connected to the first active pattern. The first gate insulating layer is between the first gate layer and the first interlayer insulating layer.
The invention also provides a preparation method of the display panel, wherein the display panel comprises a first transistor, a second transistor and a capacitor, and the preparation method of the display panel comprises the following steps:
step S100: providing a substrate, and preparing and patterning a first active layer on the substrate. Wherein the first active layer includes a first active pattern of the first transistor, and the first active layer includes a silicon semiconductor material.
Step S200: preparing and patterning a first gate layer; wherein the first gate layer comprises a first gate of the first transistor.
Step S300: a first interlayer insulating layer and a second active layer are prepared, and the second active layer is patterned. Wherein the second active layer includes a second active pattern of the second transistor and a first electrode of the capacitor, the first electrode and the second active pattern are arranged at intervals, the first electrode at least partially overlaps the first gate electrode, and the second active layer includes an oxide semiconductor material.
Step S400: a second gate layer is prepared and patterned. Wherein the second gate layer comprises a second gate of the second transistor.
Step S500: and preparing and patterning the source drain layer. The source and drain layer includes a first source and a first drain electrically connected to the first active pattern, and a second source and a second drain electrically connected to the second active pattern.
The invention provides an array substrate, a display panel and a preparation method thereof. The first active pattern of the first transistor comprises a silicon semiconductor material, the second active pattern of the second transistor comprises an oxide semiconductor material, the first pole of the capacitor and the second active pattern are arranged at the same layer and at intervals, and the second pole of the capacitor is the first grid of the first transistor. By arranging the first pole and the second active pattern to be on the same layer, the mask plate adopted by the first pole of the capacitor in the prior art can be reduced, the preparation cost can be reduced, and after the first pole of the capacitor and the second active pattern are arranged on the same layer and at intervals, the electrical performance can meet the design requirements of a wearable display product.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1A to fig. 1C are schematic structural diagrams of an array substrate according to an embodiment of the present invention;
fig. 2A to 2C are schematic structural diagrams of a display panel according to an embodiment of the invention;
fig. 3 is a flowchart of a process for manufacturing a display panel according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. It should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, not limitation. In the present invention, unless otherwise specified, the use of directional terms such as "upper" and "lower" generally means upper and lower in the actual use or operation of the device, particularly in the orientation of the figures of the drawings; while "inner" and "outer" are with respect to the outline of the device.
Specifically, fig. 1A to 1C are schematic structural diagrams of an array substrate according to an embodiment of the present invention. The embodiment of the invention provides an array substrate. The array substrate comprises a first transistor, a second transistor and a capacitor. The array substrate includes a substrate 1001, a first active layer 101, a first gate layer, a first interlayer insulating layer 103, and a second active layer.
Optionally, the array substrate further includes an isolation layer 1002 and a buffer layer 1003, and the isolation layer 1002 and the buffer layer 1003 are located between the substrate 1001 and the first active layer 101.
The first active layer 101 is located on the substrate 1001. Further, the first active layer 101 is located on the buffer layer 1003. The first active layer 101 includes a first active pattern of the first transistor. Optionally, the first active layer 101 comprises a silicon semiconductor material. Optionally, the first active layer 101 comprises a polysilicon semiconductor material.
The first gate layer is located on the first active layer 101, the first gate layer includes a first gate 1021 of the first transistor, and an orthographic projection of the first gate 1021 on the first active layer 101 overlaps at least a portion of the first active pattern. Optionally, an orthographic projection of the first gate 1021 on the first active layer 101 overlaps with a channel region of the first active pattern.
The first interlayer insulating layer 103 is located on the first gate layer. Optionally, the thickness of the first interlayer insulating layer 103 is 500 to 2000 angstroms.
The second active layer is on the first interlayer insulating layer 103, the second active layer includes an oxide semiconductor material, and the second active layer includes a second active pattern 1041 of the second transistor and a first electrode 1042 of the capacitor. Optionally, the second active layer includes Indium Gallium Zinc Oxide (IGZO), Indium Gallium Tin Oxide (IGTO), Indium Gallium Zinc Tin Oxide (IGZTO), or the like.
The first pole 1042 and the second active pattern 1041 are disposed at an interval, and the first pole 1042 overlaps the first gate 1021 to form the capacitor C.
Optionally, the array substrate further includes a second gate layer 105, a source drain layer 106, and a first gate insulating layer 107.
The second gate layer 105 is on the second active layer, and the second gate layer 105 includes a second gate of the second transistor. An orthographic projection of the second gate electrode on the second active layer overlaps at least a portion of the second active pattern 1041. Optionally, an orthographic projection of the second gate electrode on the second active layer overlaps with a channel region of the second active pattern 1041.
The source drain layer 106 is located on the second gate layer 105, and the source drain layer 106 includes a first source and a first drain of the first transistor, and a second source and a second drain of the second transistor. The first source and the first drain are both electrically connected to the first active pattern, the second source and the second drain are both electrically connected to the second active pattern 1041, and one of the second source and the second drain is electrically connected to the first active pattern. That is, the first source electrode and the first drain electrode are electrically connected to the source region and the drain region of the first active pattern, respectively, and the second source electrode and the second drain electrode are electrically connected to the source region and the drain region of the second active pattern 1041, respectively.
The first gate insulating layer 107 is located between the first gate layer and the first interlayer insulating layer 103. Alternatively, the first gate insulating layer 107 includes a silicon compound, a metal oxide, or the like. Further, the first gate insulating layer 107 includes silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or the like. Alternatively, the thickness of the first gate insulating layer 107 may be 800 to 2000 angstroms.
Optionally, the array substrate further includes a second gate insulating layer 108, a third gate insulating layer 109, a second interlayer insulating layer 110, and a planarization layer 111. The second gate insulating layer 108 is located between the first active layer 101 and the first gate layer, the third gate insulating layer 109 is located between the second active layer and the second gate layer 105, the second interlayer insulating layer 110 is located between the second gate layer 105 and the source drain layer 106, and the planarization layer 111 is located on the source drain layer 106.
Compared with the design of using GE2 (a gate layer located between the first gate insulating layer 107 and the first interlayer insulating layer 103) to prepare the first pole 1042 of the capacitor in the prior art, the first pole 1042 of the capacitor and the second active pattern 1041 are set to be the same layer, so that the second active pattern 1041 and the first pole 1042 can be prepared by one mask, and compared with the prior art, one mask for forming the first pole 1042 of the capacitor by using GE2 is reduced, which is beneficial to reducing the preparation cost.
Since the contact with the second active layer must be made of silicon oxide and the dielectric of the capacitor must be made of silicon nitride, the arrangement of the first gate insulating layer 107 and the first interlayer insulating layer 103 is reserved in this application.
Optionally, the capacitance of the capacitor is 1.92 x 10E (-11) method to 1.92 x 10E (-12) method.
Optionally, with continued reference to fig. 1B, the first gate layer further includes a blocking portion 1022, and an orthographic projection of the blocking portion 1022 on the second active layer overlaps with the channel region of the second active pattern 1041, so as to block the channel region of the second active pattern 1041 by the blocking portion 1022. Since the first gate 1021 and the shielding part 1022 are in the same layer, the first gate 1021 and the shielding part 1022 can be prepared simultaneously by using one mask.
Optionally, please continue to refer to fig. 1A to 1C. The array substrate further comprises a shielding layer. The shielding layer is located under the first active layer 101. The shielding layer includes a first shielding portion 1121, and an orthographic projection of the first shielding portion 1121 on the first active layer 101 overlaps with a channel region of the first active pattern.
Optionally, with continued reference to fig. 1C, the shielding layer further includes a second shielding portion 1122, a forward projection of the second shielding portion 1122 on the second active layer overlaps with a channel region of the second active pattern 1041, and the second shielding portion 1122 can prevent charges in the substrate 1001 from electrically affecting the channel region of the second active pattern 1041. In addition, since the first shielding portion 1121 and the second shielding portion 1122 are on the same layer, the first shielding portion 1121 and the second shielding portion 1122 can be simultaneously prepared by using one mask during preparation.
Optionally, the array substrate is provided with a groove penetrating through the isolation layer 1002, the buffer layer 1003, the first gate insulating layer 107, the second gate insulating layer 108, the third gate insulating layer 109, the first interlayer insulating layer 103, and the second interlayer insulating layer 110 in a corresponding bending region, and the flat layer 111 includes a filling portion located in the groove, so that the array substrate has a better bending performance in the corresponding bending region.
The array substrate provided by the invention is verified and compared with the array substrate comprising GE2 in the prior art, and the obtained results are shown in the following table:
as can be seen from the table, the array substrate provided by the present invention has a smaller electrical difference from the conventional array substrate, and thus the array substrate provided by the present invention can reduce the production cost, and is beneficial to increase the productivity and mass production. In addition, in the conventional array substrate, a double-gate structure is mostly adopted for a transistor to realize the stability of a device structure, but the problems of non-uniformity, instability and the like of the device exist. When the array substrate provided by the invention is applied to a wearable display product, the transistor can meet the design requirement without adopting a double-gate structure.
Fig. 2A to 2C are schematic structural diagrams of a display panel according to an embodiment of the present invention, and the embodiment of the present invention further provides a display panel including a first transistor, a second transistor, and a capacitor. The first active pattern of the first transistor comprises a silicon semiconductor material, the second active pattern 2041 of the second transistor comprises an oxide semiconductor material, and the capacitor has a first pole 2042 and a second pole.
The first electrode 2042 and the second active pattern 2041 of the second transistor are disposed in the same layer and at an interval, and the second electrode is the first gate 2021 of the first transistor.
Specifically, the display panel includes a first active layer 201, a first gate layer, a second active layer, and a first interlayer insulating layer 203.
The first active layer 201 includes the first active pattern. The first gate layer is located on the first active layer 201, and the first gate layer includes the first gate 2021. The second active layer is on the first gate layer, and includes the second active pattern 2041 and the first pole 2042. The first interlayer insulating layer 203 is located between the first gate layer and the second active layer. Optionally, the first active layer 201 includes a polysilicon semiconductor material, and the second active layer includes indium gallium zinc oxide.
Optionally, the display panel further includes a first shielding portion located under the first active layer 201, and an orthographic projection of the first shielding portion on the first active layer 201 overlaps with a channel region of the first active pattern.
Optionally, the display panel further includes a second shielding portion B2, the second shielding portion B2 is located below the second active layer, and an orthographic projection of the second shielding portion B2 on the second active layer overlaps with a channel region of the second active pattern 2041. Optionally, the second shielding portion B2 is in the same layer as the first shielding portion, or in the same layer as the first gate 2021, so that the second shielding portion B2 and the first shielding portion are manufactured by a single mask, or the second shielding portion B2 and the first gate 2021 are manufactured by a single mask.
With reference to fig. 2A to fig. 2C, the display panel further includes a substrate 2001, an isolation layer 2002, a buffer layer 2003, a second gate layer 205, a source/drain layer 206, a first gate insulating layer 207, a second gate insulating layer 208, a third gate insulating layer 209, a second interlayer insulating layer 210, and a planarization layer 211.
The isolation layer 2002 and the buffer layer 2003 are located between the substrate 2001 and the first active layer 201. The second gate layer 205 is located on the second active layer, and the second gate layer 205 includes a second gate of the second transistor, and an orthographic projection of the second gate on the second active layer at least partially overlaps the second active pattern. The source drain layer 206 is located on the second gate layer 205, and the source drain layer 206 includes a first source and a first drain of the first transistor, and a second source and a second drain of the second transistor. The first source and the first drain are electrically connected to the first active pattern, the second source and the second drain are electrically connected to the second active pattern 2041, and one of the second source and the second drain is electrically connected to the first active pattern. The first gate insulating layer 207 is located between the first gate layer and the first interlayer insulating layer 203. The second gate insulating layer 208 is located between the first active layer 201 and the first gate layer, the third gate insulating layer 209 is located between the second active layer and the second gate layer 205, the second interlayer insulating layer 210 is located between the second gate layer 205 and the source drain layer 206, and the planarization layer 211 is located on the source drain layer 206.
Optionally, the display panel further includes a shielding layer 212, and the shielding layer 212 is located between the substrate 2001 and the isolation layer 2002. The shielding layer 212 includes the first shielding portion.
With reference to fig. 2A to fig. 2C, the display panel further includes a light emitting device, the light emitting device is disposed on the source drain layer 206, the light emitting device includes an anode 213, a cathode 214, and a light emitting layer 215 disposed between the anode 213 and the cathode 214, and the light emitting layer 215 is disposed in a pixel defining area of the pixel defining layer 216. Optionally, the anode 213 is electrically connected to the first source or the first drain of the first transistor T1. Optionally, the light emitting device comprises an organic light emitting diode, a sub-millimeter light emitting diode, a micro light emitting diode, or the like.
In the invention, the first electrode 2042 of the capacitor is arranged on the same layer as the second active pattern 2041, so that the second active pattern 2041 and the first electrode 2042 can be manufactured by one mask, and compared with the prior art, one mask for forming the first electrode 1042 of the capacitor by using GE2 (a gate layer located between the first gate insulating layer 107 and the first interlayer insulating layer 103) is reduced, which is favorable for reducing the manufacturing cost.
Fig. 3 is a flowchart illustrating a manufacturing method of a display panel according to an embodiment of the present invention, where the display panel includes a first transistor, a second transistor, and a capacitor, and the manufacturing method of the display panel includes:
step S100: providing a substrate, and preparing and patterning a first active layer on the substrate. Wherein the first active layer includes a first active pattern of the first transistor, and the first active layer includes a silicon semiconductor material. Optionally, the first active layer comprises a polysilicon semiconductor material.
Optionally, the substrate comprises a rigid substrate and a flexible substrate. The substrate may comprise a single layer of insulating material of glass, quartz and polymer resin, or a multi-layer of insulating material of a double layer of polymer resin, for example.
Optionally, the substrate further includes an isolation layer and a buffer layer, and the isolation layer and the buffer layer are located between the substrate and the first active layer. Alternatively, the isolation layer and the buffer layer each include a silicon compound or the like. Further, the silicon compound includes at least one of silicon oxide, silicon nitride, silicon oxynitride, and the like.
Step S200: preparing and patterning a first gate layer; wherein the first gate layer includes a first gate of the first transistor, and an orthographic projection of the first gate on the first active layer overlaps with a channel region of the first active pattern.
Optionally, the first gate layer includes at least one of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), and the like. The first grid layer can be a single-layer film structure, and can also be a laminated structure of Ti/Al/Ti, Mo/Al/Mo, Mo/AlGe/Mo, Cu/Ti, Cu/MoTi or Cu/MoNb and the like.
Step S300: a first interlayer insulating layer and a second active layer are prepared, and the second active layer is patterned. Wherein the second active layer comprises a second active pattern of the second transistor and a first electrode of the capacitor, the first electrode and the second active pattern are arranged at intervals, an orthographic projection of the first electrode on the first gate layer at least partially overlaps with the first gate, and the second active layer comprises an oxide semiconductor material.
Alternatively, the first interlayer insulating layer includes a silicon compound, a metal oxide, or the like. Further, the first interlayer insulating layer includes at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, and the like.
Optionally, the second active layer includes any one of oxides based on titanium (Ti), hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), germanium (Ge), zinc (Zn), gallium (Ga), tin (Sn), or indium (In), or composite oxides thereof, such as Indium Gallium Zinc Oxide (IGZO), Indium Gallium Tin Oxide (IGTO), or Indium Gallium Zinc Tin Oxide (IGZTO), and the like.
Step S400: a second gate layer is prepared and patterned. Wherein the second gate layer includes a second gate of the second transistor, and an orthographic projection of the second gate on the second active layer overlaps with a channel region of the second active pattern.
Alternatively, the second gate layer 105 includes at least one of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), and the like. The second grid layer can be a single-layer film structure, and can also be a laminated structure of Ti/Al/Ti, Mo/Al/Mo, Mo/AlGe/Mo, Cu/Ti, Cu/MoTi or Cu/MoNb and the like.
Step S500: and preparing and patterning the source drain layer. The source and drain layer includes a first source and a first drain electrically connected to the first active pattern, and a second source and a second drain electrically connected to the second active pattern.
Optionally, the source drain layer includes at least one of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), and the like. The source drain electrode layer can be in a single-layer film structure, and can also be in a laminated structure of Ti/Al/Ti, Mo/Al/Mo, Mo/AlGe/Mo, Cu/Ti, Cu/MoTi or Cu/MoNb and the like.
Optionally, before the step S200, a step of preparing a second gate insulating layer on the first active layer is further included. Before the step S300, a step of preparing a first gate insulating layer on the first gate layer is further included; wherein the first interlayer insulating layer is on the first gate insulating layer. Before the step S400, a step of preparing a third gate insulating layer on the second active layer is further included. Before the step S500, a step of preparing a second interlayer insulating layer on the second gate layer, and a step of preparing a first via hole and a second via hole are further included; a first via hole penetrates through the first gate insulating layer, the second gate insulating layer, the third gate insulating layer, the first interlayer insulating layer and the second interlayer insulating layer 110 to expose a source region and a drain region of the first active pattern, and the first source electrode and the first drain electrode are electrically connected to the source region and the drain region of the first active pattern through the first via hole, respectively; the second via hole penetrates through the third gate insulating layer and the second interlayer insulating layer to expose the source region and the drain region of the second active pattern, and the second source electrode and the second drain electrode are electrically connected to the source region and the drain region of the second active pattern through the second via hole respectively.
The invention also provides a display device, which comprises any one of the array substrates or any one of the display panels. It is understood that the display device includes a movable display device (e.g., a notebook computer, a mobile phone, etc.), a fixed terminal (e.g., a desktop computer, a television, etc.), a measuring device (e.g., a sports bracelet, a temperature measuring instrument, etc.), and the like.
The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for those skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (10)
1. An array substrate, comprising a first transistor, a second transistor and a capacitor, the array substrate comprising:
a first active layer including a first active pattern of the first transistor, including a silicon semiconductor material;
a first gate layer on the first active layer, including a first gate of the first transistor;
a first interlayer insulating layer on the first gate layer; and the number of the first and second groups,
a second active layer on the first interlayer insulating layer, the second active layer including an oxide semiconductor material, the second active layer including a second active pattern of the second transistor and a first electrode of the capacitor;
wherein the first pole and the second active pattern are arranged at intervals, and the first pole overlaps with the first gate to form the capacitor.
2. The array substrate of claim 1, wherein the first gate layer further comprises a shielding portion overlapping with a channel region of the second active pattern.
3. The array substrate of claim 1, further comprising:
and the shielding layer is positioned below the first active layer and comprises a first shielding part and a second shielding part, the first shielding part is overlapped with the channel region of the first active pattern, and the second shielding part is overlapped with the channel region of the second active pattern.
4. The array substrate of claim 1, wherein the first active layer comprises a polysilicon semiconductor and the second active layer comprises indium gallium zinc oxide.
5. The array substrate of claim 1, further comprising:
a second gate layer on the second active layer, including a second gate of the second transistor;
the source drain layer is positioned on the second grid layer and comprises a first source electrode and a first drain electrode of the first transistor, and a second source electrode and a second drain electrode of the second transistor; the first source and the first drain are both electrically connected to the first active pattern, the second source and the second drain are both electrically connected to the second active pattern, and one of the second source and the second drain is electrically connected to the first active pattern; and the number of the first and second groups,
a first gate insulating layer between the first gate layer and the first interlayer insulating layer.
6. A display panel comprising a first transistor, a second transistor, and a capacitor, a first active pattern of the first transistor comprising a silicon semiconductor material, a second active pattern of the second transistor comprising an oxide semiconductor material, the capacitor having a first pole and a second pole;
the first pole and the second active pattern of the second transistor are arranged at the same layer and interval, and the second pole is a first grid of the first transistor.
7. The display panel according to claim 6, comprising:
a first active layer including the first active pattern;
a first gate layer on the first active layer, including the first gate;
a second active layer on the first gate layer, including the second active pattern and the first electrode; and the number of the first and second groups,
a first interlayer insulating layer between the first gate layer and the second active layer;
wherein the first active layer comprises a polysilicon semiconductor material and the second active layer comprises indium gallium zinc oxide.
8. The display panel according to claim 6, further comprising:
a first blocking portion under the first active layer, the first blocking portion overlapping with a channel region of the first active pattern; and the number of the first and second groups,
a second shielding portion under the second active layer, the second shielding portion overlapping with a channel region of the second active pattern;
the second shielding part is at the same layer as the first shielding part or at the same layer as the first grid.
9. The display panel according to claim 7, further comprising:
a second gate layer on the second active layer, including a second gate of the second transistor;
the source drain layer is positioned on the second grid layer and comprises a first source electrode and a first drain electrode of the first transistor, and a second source electrode and a second drain electrode of the second transistor; the first source electrode and the first drain electrode are electrically connected to the first active pattern, the second source electrode and the second drain electrode are electrically connected to the second active pattern, and one of the second source electrode and the second drain electrode is electrically connected to the first active pattern; and the number of the first and second groups,
a first gate insulating layer between the first gate layer and the first interlayer insulating layer.
10. A preparation method of a display panel is characterized in that the display panel comprises a first transistor, a second transistor and a capacitor, and the preparation method of the display panel comprises the following steps:
step S100: providing a substrate, and preparing and patterning a first active layer on the substrate; wherein the first active layer includes a first active pattern of the first transistor, the first active layer including a silicon semiconductor material;
step S200: preparing and patterning a first gate layer; wherein the first gate layer comprises a first gate of the first transistor;
step S300: preparing a first interlayer insulating layer and a second active layer, and patterning the second active layer; wherein the second active layer comprises a second active pattern of the second transistor and a first pole of the capacitor, the first pole and the second active pattern are arranged at intervals, the first pole is at least partially overlapped with the first grid, and the second active layer comprises an oxide semiconductor material;
step S400: preparing and patterning a second gate layer; wherein the second gate layer comprises a second gate of the second transistor;
step S500: preparing and patterning a source drain layer; the source and drain layer includes a first source and a first drain electrically connected to the first active pattern, and a second source and a second drain electrically connected to the second active pattern.
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| US20220310665A1 (en) * | 2020-09-04 | 2022-09-29 | Tcl China Star Optoelectronics Technology Co., Ltd. | Array substrate and manufacturing method thereof |
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| US20220310665A1 (en) * | 2020-09-04 | 2022-09-29 | Tcl China Star Optoelectronics Technology Co., Ltd. | Array substrate and manufacturing method thereof |
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