CN112635534A - Display panel, display device and manufacturing method of display panel - Google Patents

Display panel, display device and manufacturing method of display panel Download PDF

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Publication number
CN112635534A
CN112635534A CN202011538383.XA CN202011538383A CN112635534A CN 112635534 A CN112635534 A CN 112635534A CN 202011538383 A CN202011538383 A CN 202011538383A CN 112635534 A CN112635534 A CN 112635534A
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China
Prior art keywords
layer
electrode
display panel
metal
conductor
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Chinese (zh)
Inventor
钟建峰
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to CN202011538383.XA priority Critical patent/CN112635534A/en
Publication of CN112635534A publication Critical patent/CN112635534A/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

The invention provides a display panel, a display device and a manufacturing method of the display panel, wherein the display panel comprises a substrate, a metal shading layer, a buffer layer and a first electrode layer which are sequentially stacked, the first electrode layer comprises an active layer and a conductor layer which are arranged at intervals, the display panel also comprises an interlayer insulating layer and a second electrode layer which are sequentially stacked on the first electrode layer, the second electrode layer comprises a first electrode and a second electrode which are arranged at intervals, the first electrode is electrically connected with the active layer, the second electrode comprises a first electrode part and a second electrode part which are connected, the first electrode part is electrically connected with the active layer, a first capacitor is formed between the second electrode part and the conductor layer, and the second electrode part is electrically connected with the metal shading layer, so that a second capacitor is formed between the metal shading layer and the conductor layer. In the scheme, a first capacitor is formed between the second electrode part and the conductor layer, and a second capacitor is formed between the metal shading layer and the conductor layer, so that the capacitance of the display panel is increased.

Description

Display panel, display device and manufacturing method of display panel
Technical Field
The invention relates to the technical field of display, in particular to a display panel, a display device and a manufacturing method of the display panel.
Background
With the development of display technology, large-sized display panels are increasingly popular.
In order to improve the resolution of a large-sized OLED (Organic Light-emitting Diode), the size of the pixel structure in the backplane needs to be reduced. The pixel structure comprises a plurality of structures such as a thin film transistor, a light emitting region, a capacitance region, a wiring and the like. The capacitor region in the conventional OLED needs a large size to provide sufficient capacitance.
Therefore, it is necessary to provide a display panel in which the size of the capacitor can be increased.
Disclosure of Invention
The invention aims to provide a display panel, a display device and a manufacturing method of the display panel, which can improve the size of a capacitor.
An embodiment of the present invention provides a display panel, including:
a substrate;
a metal light shielding layer disposed on the substrate;
a buffer layer disposed on the metallic light-shielding layer;
a first electrode layer disposed on the buffer layer, the first electrode layer comprising:
an active layer;
a conductor layer disposed at an interval from the active layer, the conductor layer being disposed opposite to the metallic light shielding layer;
an interlayer insulating layer disposed on the first electrode layer;
a second electrode layer disposed on the inter-insulating layer, the second electrode layer including:
the first electrode is electrically connected with the active layer;
a second electrode spaced apart from the first electrode, the second electrode comprising:
a first electrode portion electrically connected to the active layer;
the second electrode part is connected with the first electrode part, the second electrode part is arranged opposite to the conductor layer, a first capacitor is formed between the second electrode part and the conductor layer, and the second electrode part is electrically connected with the metal shading layer, so that a second capacitor is formed between the metal shading layer and the conductor layer.
In one embodiment, the display panel includes a plurality of thin film transistors, the first electrode is a drain electrode of the corresponding thin film transistor, the first electrode portion is a source electrode of the corresponding thin film transistor, and the second electrode portion is an anode electrode.
In one embodiment, the first electrode layer further comprises:
a gate insulating layer disposed on the active layer;
the grid layer is arranged on the grid insulating layer and is electrically connected with the conductor layer.
In one embodiment, a first through hole is formed in the buffer layer, and a conductive material is arranged in the first through hole;
a second through hole is formed in the interlayer insulating layer, and a conductive material is arranged in the second through hole;
the second electrode part is electrically connected with the metal shading layer through the first through hole and the second through hole.
In one embodiment, the first electrode layer and the second electrode layer include:
a first transparent layer disposed on the inter insulating layer;
a metal layer disposed on the first transparent layer;
a second transparent layer disposed on the metal layer.
In one embodiment, the first transparent layer and the second transparent layer each have a thickness in a range of 500 to 1000 angstroms, and the metal layer has a thickness in a range of 3000 to 6000 angstroms.
In an embodiment, the metal light shielding layer is a laminated structure including a plurality of metal film layers.
In one embodiment, the thickness of the metallic light shielding layer ranges from 1000 to 4000 angstroms.
The embodiment of the invention also provides a display device which comprises the display panel.
The embodiment of the invention also provides a manufacturing method of the display panel, which comprises the following steps:
providing a substrate;
forming a metal light shielding layer on the substrate;
forming a buffer layer on the metallic light-shielding layer;
forming a first electrode layer on the buffer layer, wherein the first electrode layer comprises an active layer and a conductor layer, the conductor layer and the active layer are arranged at intervals, and the conductor layer and the metal shading layer are arranged oppositely;
forming an interlayer insulating layer on the first electrode layer;
forming a second electrode layer on the interlayer insulating layer, wherein the second electrode layer comprises a first electrode and a second electrode, and the first electrode is electrically connected with the active layer; the second electrode and the first electrode are arranged at intervals, and the second electrode comprises: the first electrode part is electrically connected with the active layer; the second electrode part is connected with the first electrode part, the second electrode part is arranged opposite to the conductor layer, a first capacitor is formed between the second electrode part and the conductor layer, and the second electrode part is electrically connected with the metal shading layer, so that a second capacitor is formed between the metal shading layer and the conductor layer.
In the display panel, the display device and the manufacturing method of the display panel in the embodiment of the invention, on the basis of forming the first capacitor between the second electrode part and the conductor layer, the second electrode part is electrically connected with the metal shading layer to form the second capacitor between the metal shading layer and the conductor layer, so that the capacitance of the display panel is increased.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention.
Fig. 2 is a schematic flow chart illustrating a manufacturing method of a display panel according to an embodiment of the present invention.
Fig. 3 is a scene schematic diagram of a manufacturing method of a display panel according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.
The embodiment of the invention provides a display device. The display device includes a display panel. Referring to fig. 1, fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention. As shown in fig. 1, the display panel 1 includes a substrate 11, a metal light-shielding layer 12, a buffer layer 13, a first electrode layer 14, an interlayer insulating layer 15, and a second electrode layer 16.
The substrate 11 is used for bearing the structures of the metal shading layer 12, the buffer layer 13 and the like. The substrate 11 may be a flexible substrate or a rigid substrate, and the type of the substrate 11 is not limited in the embodiment of the present invention.
The metal light-shielding layer 12 is provided on the substrate 11. The composition material of the metallic light shielding layer 12 may be a metal or a metal alloy, such as at least one of molybdenum Mo, copper Cu, and titanium Ti. Further, the metallic light shielding layer 12 may be a laminated structure including a plurality of metallic film layers, for example, a three-layer sandwich structure: a first layer of metal Mo, a second layer of metal Ti positioned in the middle layer, and a third layer of metal Cu. The thickness of the metallic light-shielding layer 12 ranges from 1000 to 4000 angstroms.
The buffer layer 13 is provided on the metallic light-shielding layer 12. Wherein, the composition material of the buffer layer 13 may be silicon oxide SiOxAnd/or silicon nitride SiNx. In an embodiment, the buffer layer 13 may further include a plurality of layers, wherein each layer may be formed of SiOxOr SiNx. As shown in fig. 3, the buffer layer 13 is provided with a first through hole 131, and the first through hole 131 has a conductive material therein.
The first electrode layer 14 is disposed on the buffer layer 13. In one embodiment, the first electrode layer 14 includes an active layer 141 and a conductor layer 142.
The active layer 141 includes a channel region 1411 and a doped region 1412, as shown in fig. 1, the doped region 1412 is located at two sides of the channel region 1411. The channel region 1411 is made of a semiconductor material, such as a metal oxide IGZO (indium gallium zinc oxide), IGTO (indium gallium tin oxide), or the like. The doped regions 1412 are formed of a conductive material. In one embodiment, the composition material of the doped region 1412 may also be a semiconductor material. Note that the doped region 1412 made of a semiconductor material is subjected to Plasma treatment, so that the resistance value thereof is reduced and is converted into a conductive layer having a conductive characteristic. Wherein the Plasma treatment can use hydrogen H2Helium He and ammonia NH3And the like. In summary, the channel region 1411 and the doped region 1412 can both be fabricated using semiconductor materials, so that they can be fabricated using the same process, thereby reducing the number of photomasks, wherein the thickness of the semiconductor material is in the range of 300 to 1000 angstroms.
As shown in fig. 1, the conductive layer 142 is provided at a distance from the active layer 141, and the conductive layer 142 is provided opposite to the metal light-shielding layer 12. The constituent material of the conductor layer 142 may include a conductor material, and may also include a plasma-processed semiconductor material, such as a metal oxide IGZO (indium gallium zinc oxide), IGTO (indium gallium tin oxide), or the like. Wherein the thickness of the semiconductor material ranges from 300 to 1000 angstroms. It should be noted that, since both the conductive layer 142 and the active layer 141 can be made of semiconductor materials, both can be made by the same process, which reduces the number of photomasks.
In one embodiment, the first electrode layer 14 further comprises: a gate insulating layer 143, and a gate layer 144. Here, the gate electrode layer 144 is disposed on the gate insulating layer 143, and the gate insulating layer 143 is disposed on the active layer 141, specifically, on the channel region 1411. The gate insulating layer 143 serves to insulate the gate layer 144 from the active layer 141. The constituent material of the gate insulating layer 143 includes silicon oxide SiOxAnd/or silicon nitride SiNx. In an embodiment, the gate insulating layer 143 may further include a plurality of layers, wherein a composition material of each layer may be SiOxOr SiNx. It should be noted that, when the doped region 1412 and the conductive layer 142 are subjected to Plasma processing, the gate insulating layer 144 may protect the channel region 1411 and prevent the channel region 1411 from becoming conductive.
The composition material of the gate layer 144 may be a metal or a metal alloy, such as at least one of Mo, Cu, and Ti. Further, the gate layer 144 may be a laminated structure including multiple layers of metals, such as a three-layer sandwich structure: the first layer of metal Mo, the second layer of metal Ti positioned in the middle layer and the third layer of metal Cu. The gate layer 144 has a thickness in the range of 2000-. The gate layer 144 is electrically connected to the conductive layer 142, so that the conductive layer 142 and the gate layer 144 have the same potential.
The interlayer insulating layer 15 is disposed on the first electrode layer 14. The constituent material of the interlayer insulating layer 15 may be silicon oxide SiOxAnd/or silicon nitride SiNx. In one embodiment, the interlayer insulating layer 15 may further include a plurality of layers, wherein each layer may be formed of SiOxOr SiNx. The thickness of the interlayer insulating layer 15 ranges from 2000-10000 angstroms.
As shown in fig. 3, the inter-layer insulation 15 is provided with a second via 151 and a third via 152, and the second via 151 and the third via 152 have a conductive material therein. In one embodiment, the second through hole 151 and the first through hole 131 penetrate. The first through-hole 131, the second through-hole 151, and the third through-hole 152 may be prepared using a half-tone process. Specifically, a layer of photoresist is disposed on the inter-insulating layer 15, the second through hole 151 is etched to form a part of the second through hole 151, the photoresist at the position of the third through hole 152 is removed, the third through hole 152 and the second through hole 151 are etched at the same time, and finally, the first through hole 131, the second through hole 151 and the third through hole 152 are simultaneously prepared.
The second electrode layer 16 is disposed on the interlayer insulating layer 15. The second electrode layer 16 includes: a first electrode 161 and a second electrode 162. The first electrode 161 is electrically connected to the active layer 141. The second electrode 162 and the first electrode 161 are spaced apart from each other.
The second electrode 162 includes: a first electrode portion 1621 and a second electrode portion 1622. The first electrode portion 1621 is electrically connected to the active layer 141. In one embodiment, the second electrode portion 1622 is contiguous with the first electrode portion 1621. In the manufacturing process, an extension portion of the first electrode portion 1621 may be used as the second electrode portion 1622, that is, the first electrode portion 1621 and the second electrode portion 1622 may be integrally molded.
As shown in fig. 1, the second electrode portion 1622 is disposed opposite to the conductive layer 142, a first capacitor C1 is formed between the second electrode portion 1622 and the conductive layer 142, and the second electrode portion 1622 is electrically connected to the metallic shading layer 12, so that a second capacitor C2 is formed between the metallic shading layer 12 and the conductive layer 142. In one embodiment, the second electrode portion 1622 is electrically connected to the metallic light shielding layer 12 through the first via 131 and the second via 151.
In summary, a first capacitor C1 is formed between the second electrode portion 1622 and the conductive layer 142, and a second capacitor C2 is formed between the metal light shielding layer 12 and the conductive layer 142, so that the size of the capacitor in the display panel 1 is greatly increased, and the size of the capacitor area can be reduced.
In one embodiment, the first electrode layer 14 and the second electrode layer 16 include: the first transparent layer A, the metal layer B and the second transparent layer C are sequentially stacked. Here, the first electrode layer 14 and the first transparent layer a in the first electrode portion 1621 are provided on the interlayer insulating layer 15. The first transparent layer a of the second electrode portion 1622 is disposed on the metallic light shielding layer 12. The first transparent layer a and the second transparent layer C may be formed of IZO, ITO, or the like. The constituent material of the metal layer B may be aluminum, silver, or the like. The first transparent layer A and the second transparent layer C both have a thickness ranging from 500 to 1000 angstroms, and the metal layer B has a thickness ranging from 3000 to 6000 angstroms.
In one embodiment, the display panel 1 includes a plurality of thin film transistors, the first electrode 161 is a drain electrode of a corresponding thin film transistor, the first electrode portion 1621 is a source electrode of a corresponding thin film transistor, and the second electrode portion 1622 is an anode electrode.
Further, as shown in fig. 1, the display panel 1 further includes a passivation layer 17, a pixel defining layer 18, a light emitting layer 19, and a cathode 20.
A passivation layer 17 is disposed on the second electrode layer 16. The passivation layer 17 may be formed of silicon oxide SiOxAnd/or silicon nitride SiNx. In an embodiment, the passivation layer 17 may further include a plurality of layers, wherein each layer may be formed of SiOxOr SiNx. The thickness of the passivation layer 17 ranges from 1000 a to 5000 a.
The pixel defining layer 18 and the light emitting layer 19 are both disposed on the passivation layer 17. The pixel defining layer 18 includes a plurality of pixel defining portions, and the light emitting layer 19 includes a plurality of light emitting portions. Each light emitting section is disposed between corresponding adjacent pixel defining sections. The light-emitting layer 19 is formed by evaporating or printing an organic light-emitting material.
The cathode 20 is disposed on the pixel defining layer 18 and the light emitting layer 19. The cathode 20 may be made of a material having a low work function, such as a metal material, e.g., silver, aluminum, lithium, etc.
The embodiment of the invention also provides a manufacturing method of the display panel. Referring to fig. 2, fig. 2 is a schematic flow chart illustrating a manufacturing method of a display panel according to an embodiment of the invention. As shown in fig. 2, the manufacturing method of the display panel includes:
step S101, a substrate is provided.
As shown in fig. 1 or 3, the substrate 11 is used to support a metal light shielding layer 12, a buffer layer 13, and the like thereon. The substrate 11 may be a flexible substrate or a rigid substrate, and the type of the substrate 11 is not limited in the embodiment of the present invention.
Step S102 is to form a metal light shielding layer on the substrate.
The constituent material of the metallic light shield layer 12 may be a metal or a metal alloy, such as at least one of molybdenum Mo, copper Cu, and titanium Ti. Further, the metallic light shielding layer 12 may be a laminated structure including a plurality of metallic film layers, for example, a three-layer sandwich structure: a first layer of metal Mo, a second layer of metal Ti positioned in the middle layer, and a third layer of metal Cu. The thickness of the metallic light-shielding layer 12 ranges from 1000 to 4000 angstroms.
In step S103, a buffer layer is formed on the metal light-shielding layer.
The buffer layer 13 may be made of silicon oxide SiOxAnd/or silicon nitride SiNx. In an embodiment, the buffer layer 13 may further include a plurality of layers, wherein each layer may be formed of SiOxOr SiNx. As shown in fig. 3, the buffer layer 13 is provided with a first through hole 131, and the first through hole 131 has a conductive material therein.
Step S104, forming a first electrode layer on the buffer layer, where the first electrode layer includes an active layer and a conductor layer, the conductor layer and the active layer are disposed at an interval, and the conductor layer and the metal light shielding layer are disposed opposite to each other.
In one embodiment, the first electrode layer 14 includes an active layer 141 and a conductor layer 142. The active layer 141 includes a channel region 1411 and a doped region 1412, as shown in fig. 1, the doped region 1412 is located at two sides of the channel region 1411. The channel region 1411 is made of a semiconductor material, such as a metal oxide IGZO (indium gallium zinc oxide), IGTO (indium gallium tin oxide), or the like. The doped regions 1412 are formed of a conductive material. In one embodiment, the composition material of the doped region 1412 may also be a semiconductor material. To be explainedThe doped region 1412 made of a semiconductor material is subjected to Plasma treatment, so that the resistance value is reduced and the doped region is converted into a conductor layer with conductor characteristics. Wherein the Plasma treatment can use hydrogen H2Helium He and ammonia NH3And the like. In summary, the channel region 1411 and the doped region 1412 can both be fabricated using semiconductor materials, so that they can be fabricated using the same process, thereby reducing the number of photomasks, wherein the thickness of the semiconductor material is in the range of 300 to 1000 angstroms.
As shown in fig. 1, the conductive layer 142 is provided at a distance from the active layer 141, and the conductive layer 142 is provided opposite to the metal light-shielding layer 12. The constituent material of the conductor layer 142 may include a conductor material, and may also include a plasma-processed semiconductor material, such as a metal oxide IGZO (indium gallium zinc oxide), IGTO (indium gallium tin oxide), or the like. Wherein the thickness of the semiconductor material ranges from 300 to 1000 angstroms. It should be noted that, since both the conductive layer 142 and the active layer 141 can be made of semiconductor materials, as shown in fig. 3, they can be made by the same process, thereby reducing the number of photomasks.
In one embodiment, the first electrode layer 14 further comprises: a gate insulating layer 143, and a gate layer 144. Here, the gate electrode layer 144 is disposed on the gate insulating layer 143, and the gate insulating layer 143 is disposed on the active layer 141, specifically, on the channel region 1411. The gate insulating layer 143 serves to insulate the gate layer 144 from the active layer 141. The constituent material of the gate insulating layer 143 includes silicon oxide SiOxAnd/or silicon nitride SiNx. In an embodiment, the gate insulating layer 143 may further include a plurality of layers, wherein a composition material of each layer may be SiOxOr SiNx. It should be noted that, when the doped region 1412 and the conductive layer 142 are subjected to Plasma processing, the gate insulating layer 144 may protect the channel region 1411 and prevent the channel region 1411 from becoming conductive.
The composition material of the gate layer 144 may be a metal or a metal alloy, such as at least one of Mo, Cu, and Ti. Further, the gate layer 144 may be a laminated structure including multiple layers of metals, such as a three-layer sandwich structure: the first layer of metal Mo, the second layer of metal Ti positioned in the middle layer and the third layer of metal Cu. The gate layer 144 has a thickness in the range of 2000-. The gate layer 144 is electrically connected to the conductive layer 142, so that the conductive layer 142 and the gate layer 144 have the same potential.
The process flow of the gate insulating layer 143 and the gate layer 144 will be described in detail below. Specifically, a gate insulating material is coated on the active layer 141 and the conductor layer 142, and then a gate material is coated on the gate insulating material. The gate material is patterned by wet etching to obtain a patterned gate layer 144, and then the gate insulating material under the gate layer 144 is retained according to the gate layer 144, and the rest of the gate insulating material is etched to obtain the gate insulating layer 143.
In step S105, an interlayer insulating layer is formed on the first electrode layer.
The constituent material of the interlayer insulating layer 15 may be silicon oxide SiOxAnd/or silicon nitride SiNx. In one embodiment, the interlayer insulating layer 15 may further include a plurality of layers, wherein each layer may be formed of SiOxOr SiNx. The thickness of the interlayer insulating layer 15 ranges from 2000-10000 angstroms.
As shown in fig. 3, the inter-layer insulation 15 is provided with a second via 151 and a third via 152, and the second via 151 and the third via 152 have a conductive material therein. In one embodiment, the second through hole 151 and the first through hole 131 penetrate. The first through-hole 131, the second through-hole 151, and the third through-hole 152 may be prepared using a half-tone process. Specifically, a layer of photoresist is disposed on the inter-insulating layer 15, the second through hole 151 is etched to form a part of the second through hole 151, the photoresist at the position of the third through hole 152 is removed, the third through hole 152 and the second through hole 151 are etched at the same time, and finally, the first through hole 131, the second through hole 151 and the third through hole 152 are simultaneously prepared.
Step S106 is to form a second electrode layer on the inter-insulating layer, where the second electrode layer includes a first electrode and a second electrode, and the first electrode is electrically connected to the active layer. The second electrode and the first electrode are arranged at intervals, and the second electrode comprises: the first electrode part is electrically connected with the active layer. The second electrode part is connected with the first electrode part, the second electrode part is arranged opposite to the conductor layer, a first capacitor is formed between the second electrode part and the conductor layer, and the second electrode part is electrically connected with the metal shading layer, so that a second capacitor is formed between the metal shading layer and the conductor layer.
The second electrode layer 16 includes: a first electrode 161 and a second electrode 162. The first electrode 161 is electrically connected to the active layer 141. The second electrode 162 and the first electrode 161 are spaced apart from each other.
The second electrode 162 includes: a first electrode portion 1621 and a second electrode portion 1622. The first electrode portion 1621 is electrically connected to the active layer 141. In one embodiment, the second electrode portion 1622 is contiguous with the first electrode portion 1621. In the manufacturing process, an extension portion of the first electrode portion 1621 may be used as the second electrode portion 1622, that is, the first electrode portion 1621 and the second electrode portion 1622 may be integrally molded.
As shown in fig. 1, the second electrode portion 1622 is disposed opposite to the conductive layer 142, a first capacitor C1 is formed between the second electrode portion 1622 and the conductive layer 142, and the second electrode portion 1622 is electrically connected to the metallic shading layer 12, so that a second capacitor C2 is formed between the metallic shading layer 12 and the conductive layer 142. In one embodiment, the second electrode portion 1622 is electrically connected to the metallic light shielding layer 12 through the first via 131 and the second via 151.
In summary, a first capacitor C1 is formed between the second electrode portion 1622 and the conductive layer 142, and a second capacitor C2 is formed between the metal light shielding layer 12 and the conductive layer 142, so that the size of the capacitor in the display panel 1 is greatly increased, and the size of the capacitor area can be reduced.
In one embodiment, the first electrode layer 14 and the second electrode layer 16 include: the first transparent layer A, the metal layer B and the second transparent layer C are sequentially stacked. Here, the first electrode layer 14 and the first transparent layer a in the first electrode portion 1621 are provided on the interlayer insulating layer 15. The first transparent layer a of the second electrode portion 1622 is disposed on the metallic light shielding layer 12. The first transparent layer a and the second transparent layer C may be formed of IZO, ITO, or the like. The constituent material of the metal layer B may be aluminum, silver, or the like. The first transparent layer A and the second transparent layer C both have a thickness ranging from 500 to 1000 angstroms, and the metal layer B has a thickness ranging from 3000 to 6000 angstroms.
In one embodiment, the display panel 1 includes a plurality of thin film transistors, the first electrode 161 is a drain electrode of a corresponding thin film transistor, the first electrode portion 1621 is a source electrode of a corresponding thin film transistor, and the second electrode portion 1622 is an anode electrode.
Further, as shown in fig. 3, the display panel 1 further includes a passivation layer 17, a pixel defining layer 18, a light emitting layer 19, and a cathode 20.
A passivation layer 17 is prepared on the second electrode layer 16. The passivation layer 17 may be formed of silicon oxide SiOxAnd/or silicon nitride SiNx. In an embodiment, the passivation layer 17 may further include a plurality of layers, wherein each layer may be formed of SiOxOr SiNx. The thickness of the passivation layer 17 ranges from 1000 a to 5000 a.
A pixel defining layer 18 and a light emitting layer 19 are prepared on the passivation layer 17. The pixel defining layer 18 includes a plurality of pixel defining portions, and the light emitting layer 19 includes a plurality of light emitting portions. Each light emitting section is disposed between corresponding adjacent pixel defining sections. The light-emitting layer 19 is formed by evaporating or printing an organic light-emitting material.
A cathode 20 is prepared on the pixel defining layer 18 and the light emitting layer 19. The cathode 20 may be made of a material having a low work function, such as a metal material, e.g., silver, aluminum, lithium, etc.
In the display panel, the display device and the manufacturing method of the display panel in the embodiment of the invention, on the basis of forming the first capacitor between the second electrode part and the conductor layer, the second electrode part is electrically connected with the metal shading layer to form the second capacitor between the metal shading layer and the conductor layer, so that the capacitance of the display panel is increased.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The display panel, the display device and the manufacturing method of the display panel provided by the embodiment of the present application are introduced in detail, a specific example is applied in the present application to explain the principle and the implementation manner of the present application, and the description of the above embodiment is only used to help understanding the technical scheme and the core idea of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.

Claims (10)

1. A display panel, comprising:
a substrate;
a metal light shielding layer disposed on the substrate;
a buffer layer disposed on the metallic light-shielding layer;
a first electrode layer disposed on the buffer layer, the first electrode layer comprising:
an active layer;
a conductor layer disposed at an interval from the active layer, the conductor layer being disposed opposite to the metallic light shielding layer;
an interlayer insulating layer disposed on the first electrode layer;
a second electrode layer disposed on the inter-insulating layer, the second electrode layer including:
the first electrode is electrically connected with the active layer;
a second electrode spaced apart from the first electrode, the second electrode comprising:
a first electrode portion electrically connected to the active layer;
the second electrode part is connected with the first electrode part, the second electrode part is arranged opposite to the conductor layer, a first capacitor is formed between the second electrode part and the conductor layer, and the second electrode part is electrically connected with the metal shading layer, so that a second capacitor is formed between the metal shading layer and the conductor layer.
2. The display panel according to claim 1, wherein the display panel includes a plurality of thin film transistors, the first electrode is a drain electrode of a corresponding thin film transistor, the first electrode portion is a source electrode of a corresponding thin film transistor, and the second electrode portion is an anode electrode.
3. The display panel according to claim 1, wherein the first electrode layer further comprises:
a gate insulating layer disposed on the active layer;
the grid layer is arranged on the grid insulating layer and is electrically connected with the conductor layer.
4. The display panel according to claim 1,
a first through hole is formed in the buffer layer, and a conductive material is arranged in the first through hole;
a second through hole is formed in the interlayer insulating layer, and a conductive material is arranged in the second through hole;
the second electrode part is electrically connected with the metal shading layer through the first through hole and the second through hole.
5. The display panel according to claim 1, wherein the first electrode layer and the second electrode layer comprise:
a first transparent layer disposed on the interlayer insulating layer or the metallic light shielding layer;
a metal layer disposed on the first transparent layer;
a second transparent layer disposed on the metal layer.
6. The display panel of claim 5, wherein the first and second transparent layers each have a thickness in a range of 500 to 1000 angstroms and the metal layer has a thickness in a range of 3000 to 6000 angstroms.
7. The display panel according to claim 1, wherein the metal light shielding layer is a laminated structure including a plurality of metal film layers.
8. The display panel of claim 1, wherein the metallic light-shielding layer has a thickness ranging from 1000 to 4000 angstroms.
9. A display device characterized by comprising the display panel according to any one of claims 1 to 8.
10. A method for manufacturing a display panel is characterized by comprising the following steps:
providing a substrate;
forming a metal light shielding layer on the substrate;
forming a buffer layer on the metallic light-shielding layer;
forming a first electrode layer on the buffer layer, wherein the first electrode layer comprises an active layer and a conductor layer, the conductor layer and the active layer are arranged at intervals, and the conductor layer and the metal shading layer are arranged oppositely;
forming an interlayer insulating layer on the first electrode layer;
forming a second electrode layer on the interlayer insulating layer, wherein the second electrode layer comprises a first electrode and a second electrode, and the first electrode is electrically connected with the active layer; the second electrode and the first electrode are arranged at intervals, and the second electrode comprises: the first electrode part is electrically connected with the active layer; the second electrode part is connected with the first electrode part, the second electrode part is arranged opposite to the conductor layer, a first capacitor is formed between the second electrode part and the conductor layer, and the second electrode part is electrically connected with the metal shading layer, so that a second capacitor is formed between the metal shading layer and the conductor layer.
CN202011538383.XA 2020-12-23 2020-12-23 Display panel, display device and manufacturing method of display panel Pending CN112635534A (en)

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