CN111293153A - Display panel and display panel manufacturing method - Google Patents
Display panel and display panel manufacturing method Download PDFInfo
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- CN111293153A CN111293153A CN202010106899.0A CN202010106899A CN111293153A CN 111293153 A CN111293153 A CN 111293153A CN 202010106899 A CN202010106899 A CN 202010106899A CN 111293153 A CN111293153 A CN 111293153A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/122—Pixel-defining structures or layers, e.g. banks
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
Abstract
The embodiment of the application provides a display panel and a display panel manufacturing method. The display panel includes: a pixel electrode layer at least partially disposed within the binding region, the pixel electrode layer comprising: the transparent conductive film comprises a first transparent conductive film layer, a metal layer, a second transparent conductive film layer and a third transparent conductive film layer. The first transparent conductive film layer comprises a first surface and a second surface which are oppositely arranged; the metal layer is arranged on the first surface; the second transparent conductive film layer is arranged on one side of the metal layer, which is far away from the first surface; the third transparent conductive film layer covers one side of the second transparent conductive film layer, which is far away from the metal layer, and wraps the edges of the first transparent conductive film layer, the metal layer and the second transparent conductive film layer. The display panel that this application embodiment provided wraps up through increasing the transparent conducting film layer of third, and the protection metal level is not oxidized.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to a display panel and a display panel manufacturing method.
Background
In a top emission Organic Light-Emitting Diode (OLED) panel, an anode is usually made of metal, and is easily oxidized after being exposed for a long time, and usually, a metal layer needs to be removed from a PAD in a peripheral bonding (bonding) area, or the metal layer cannot be exposed to the outside.
Disclosure of Invention
The embodiment of the application provides a display panel and a display panel manufacturing method, which can solve the problem that a metal layer in a binding region is exposed and is easy to oxidize.
The application provides a display panel, including:
the display panel is provided with a pixel area and a binding area, and the pixel area and the binding area are arranged adjacently; the display panel includes:
a pixel electrode layer at least partially disposed within the binding region, the pixel electrode layer comprising:
the first transparent conductive thin film layer comprises a first surface and a second surface which are oppositely arranged;
a metal layer disposed on the first side;
the second transparent conductive thin film layer is arranged on one side, far away from the first surface, of the metal layer;
and the third transparent conductive thin film layer covers one side of the second transparent conductive thin film layer, which is far away from the metal layer, and wraps the edges of the first transparent conductive thin film layer, the metal layer and the second transparent conductive thin film layer.
In some embodiments, the display panel further includes an interlayer insulating layer, a source drain layer, a passivation layer, a planarization layer, and a pixel defining layer; the planarization layer is arranged on one side, close to the first transparent conductive film layer, of the pixel electrode layer; the passivation layer is arranged on one side, far away from the pixel electrode layer, of the planarization layer; the source drain layer is arranged on one side, far away from the planarization layer, of the passivation layer; the interlayer insulating layer is arranged on one side, away from the passivation layer, of the source drain layer, the source drain layer partially covers the interlayer insulating layer, and the passivation layer covers the source drain layer and the interlayer insulating layer; the pixel defining layer is arranged on one side of the pixel electrode layer far away from the planarization layer and covers the planarization layer;
the passivation layer and the planarization layer of the binding region are provided with a first contact hole; the first contact hole extends from the surface of one side, away from the passivation layer, of the planarization layer to the surface of one side, away from the interlayer insulating layer, of the source drain layer; the pixel electrode layer is connected with the source drain electrode layer through the first contact hole.
In some embodiments, the passivation layer and the planarization layer of the pixel region are provided with a second contact hole, and the second contact hole extends from the surface of one side, away from the passivation layer, of the planarization layer to the surface of one side, away from the interlayer insulating layer, of the source drain layer; the pixel electrode layer is connected with the source drain electrode layer through the second contact hole.
In some embodiments, the pixel defining layer of the binding region is provided with a first groove; the first groove extends from the surface of one side, away from the pixel electrode layer, of the pixel defining layer to the surface of one side, away from the first face, of the third transparent conductive thin film layer of the pixel region.
In some embodiments, the pixel defining layer of the pixel region is provided with a second groove; the second groove extends from the surface of one side, away from the pixel electrode layer, of the pixel defining layer to the surface of one side, away from the first face, of the third transparent conductive thin film layer of the pixel area.
In some embodiments, the material of the first, second and third transparent conductive thin film layers is indium tin oxide; the metal layer is made of silver.
In some embodiments, the first transparent conductive thin film layer has a thickness of
To
The thickness of the metal layer is
To
The thickness of the second transparent conductive film layer is
To
The thickness of the third transparent conductive film layer is
To
In some embodiments, the material of the interlayer insulating layer and the passivation layer is a silicon oxide derivative, a silicon nitride derivative, or a combination thereof, and the thickness of the interlayer insulating layer is
To
The thickness of the passivation layer is
To
In some embodiments, the material of the planarization layer is a photoresist material, and the thickness of the planarization layer is 0.5 μm to 3 μm.
The application provides a manufacturing method of a display panel, comprising the following steps:
providing a first transparent conductive film layer, wherein the first transparent conductive film layer comprises a first surface and a second surface which are oppositely arranged;
arranging a metal layer on the first surface;
arranging a second transparent conductive film layer on the metal layer;
arranging a third transparent conductive thin film layer on the second transparent conductive thin film layer, wherein the third transparent conductive thin film layer covers one side of the second transparent conductive thin film layer, which is far away from the metal layer, and wraps the edges of the first transparent conductive thin film layer, the metal layer and the second transparent conductive thin film layer to form a pixel electrode layer;
and at least partially arranging the pixel electrode layer in a binding region of the display panel, wherein the binding region is arranged adjacent to the pixel.
The display panel provided by the embodiment of the application has the pixel area and the binding area which are adjacently arranged. The display panel includes: and the pixel electrode layer is at least partially arranged in the binding region. The pixel electrode layer includes: the display device comprises a first transparent conductive thin film layer, a metal layer, a second transparent conductive thin film layer and a third transparent conductive thin film layer. The first transparent conductive thin film layer comprises a first face and a second face which are oppositely arranged, the metal layer is arranged on the first face, the second transparent conductive thin film layer is arranged on the metal layer and is far away from one side of the first face, and the third transparent conductive thin film layer covers the second transparent conductive thin film layer and is far away from one side of the metal layer and wraps the edges of the first transparent conductive thin film layer, the metal layer and the second transparent conductive thin film layer. The display panel that this application embodiment provided wraps up through increasing the transparent conducting film layer of third, and the protection metal level is not oxidized.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic view of a display panel according to an embodiment of the present disclosure.
Fig. 2 is a schematic structural diagram of a display panel according to an embodiment of the present application.
Fig. 3 is a schematic structural diagram of a pixel electrode layer according to an embodiment of the present disclosure.
Fig. 4 is a first flowchart of a display panel manufacturing method according to an embodiment of the present disclosure.
Fig. 5 is a second flowchart of a display panel manufacturing method according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that in the description of the present application, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, which are only for convenience in describing the present application and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be configured in a specific orientation, and operate, and thus, should not be construed as limiting the present application.
The embodiments of the present application provide a display panel, which is described in detail below.
Referring to fig. 1, fig. 1 is a schematic view of a display panel 10 according to an embodiment of the present disclosure. The display panel 10 has a pixel region 10a and a binding region 10b, and the pixel region 10a and the binding region 10b are adjacently disposed.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a display panel 10 according to an embodiment of the present disclosure. The display panel 10 includes a glass substrate 101, a light-shielding layer 102, a buffer layer 103, a semiconductor layer 104, a conductor layer 105, a gate insulating layer 106, a gate metal layer 107, an interlayer insulating layer 108, a source/drain layer 109, a passivation layer 110, a planarization layer 111, a pixel electrode layer 112, and a pixel definition layer 113. A light-shielding layer 102, a buffer layer 103, a semiconductor layer 104, a conductor layer 105, a gate insulating layer 106, a gate metal layer 107, an interlayer insulating layer 108, a source/drain layer 109, a passivation layer 110, a planarization layer 111, a pixel electrode layer 112, and a pixel definition layer 113 are sequentially deposited on the glass substrate 101.
The light-shielding layer 102 is located in the pixel region 10 a. The light-shielding layer 102 is made of metal or alloy. Specifically, the material used for the light-shielding layer 102 may be molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or an alloy of the foregoing metals. The light-shielding layer 102 has a thickness of
To
Specifically, the light-shielding layer 102 may have a thickness of
Or
The buffer layer 103 is made of silicon oxide derivatives, silicon nitride derivatives, or a combination thereof. The buffer layer 103 has a thickness of
To
Specifically, the buffer layer 103 may have a thickness of
Or
The semiconductor layer 104 is located in the conductor layer 105, and the gate insulating layer 106 and the gate metal layer 107 are sequentially disposed on the semiconductor layer 104. The semiconductor layer 104 and the conductor layer 105 are located in the pixel region 10 a.
The semiconductor layer 104 is made of metal oxide. Specifically, the semiconductor layer 104 is made of indium gallium zinc oxideAny one of substance (IGZO), Indium Zinc Tin Oxide (IZTO), Indium Gallium Zinc Tin Oxide (IGZTO), Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Indium Aluminum Zinc Oxide (IAZO), Indium Gallium Tin Oxide (IGTO), or Antimony Tin Oxide (ATO). Wherein the thickness of the semiconductor layer 104 and the conductor layer 105 is
To
Specifically, the thickness of the semiconductor layer 104 and the conductor layer 105 may be
Or
The gate insulating layer 106 is made of a silicon oxide derivative, a silicon nitride derivative, or a combination thereof. The thickness of the gate insulating layer 106 is
To
Specifically, the thickness of the gate insulating layer 106 may be
Or
The gate metal layer 107 may be made of molybdenum (Mo) or aluminum (al)
Copper (Cu), titanium (Ti), or alloys of the foregoing metals. The thickness of the gate metal layer 107 is
To
Specifically, the thickness of the gate metal layer 107 may be
Or
The interlayer insulating layer 108 is made of silicon oxide derivative, silicon nitride derivative, or a combination thereof. The interlayer insulating layer 108 has a thickness of
To
Specifically, the interlayer insulating layer 108 has a thickness of
Or
The interlayer insulating layer 108 of the pixel region 10a is disposed on the conductor layer 105, and the interlayer insulating layer 108 of the pixel region 10a is provided with a third contact hole and a fourth contact hole. The interlayer insulating layer 109 covers the conductive layer 105, the gate insulating layer 106, and the gate metal layer 107.
The source/drain layer 109 is made of metal. Specifically, the source drain layer 109 may be made of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or an alloy of the foregoing metals. The source drain layer 109 has a thickness of
To
Specifically, the thickness of the source drain layer 109 is
Or
The source/drain electrode layer 109 of the binding region 10b is disposed on the interlayer insulating layer 108 and partially covers the interlayer insulating layer 108, and the source/drain electrode layer 109 of the pixel region 10a is patterned and then connected to the conductor layer 105 through the third contact hole and the fourth contact hole.
The passivation layer 110 is made of silicon oxide derivatives, silicon nitride derivatives, or a combination thereof. The passivation layer 110 has a thickness of
To
Specifically, the thickness of the passivation layer 110 may be
Or
The passivation layer 110 covers the source-drain layer 109 and the interlayer insulating layer 108.
The material used for the planarization layer 111 is a photoresist material. The planarization layer 111 has a thickness of 0.5 μm to 3 μm. Specifically, the thickness of the planarization layer 111 may be 0.5 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm, or 3 μm.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a pixel electrode layer 112 in the display panel 10 according to the embodiment of the present disclosure. The display panel 10 includes a pixel electrode layer 112, the pixel electrode layer 112 is at least partially disposed in the binding region 10b, and the pixel electrode layer 112 includes: a first transparent conductive thin film layer 1121, a metal layer 1122, a second transparent conductive thin film layer 1123, and a third transparent conductive thin film layer 1124. The first transparent conductive thin film layer 1121 includes a first face 1121a and a second face 1121b that are oppositely disposed. The metal layer 1122 is provided on the first surface 1121 a. A second transparent conductive thin film layer 1123 is disposed on the side of the metal layer 1122 away from the first face 1121 a. The third transparent conductive thin film layer 1124 covers a side of the second transparent conductive thin film layer 1123 away from the metal layer 1122 and wraps edges of the first transparent conductive thin film layer 1121, the metal layer 1122, and the second transparent conductive thin film layer 1123.
The first transparent conductive thin film layer 1121, the second transparent conductive thin film layer 1123, and the third transparent conductive thin film layer 1124 are made of Indium Tin Oxide (ITO), and the metal layer 1122 is made of silver (Ag).
Wherein the first transparent conductive thin film layer 1121 has a thickness of
To
The thickness of the metal layer 1122 is
To
The second transparent conductive thin film layer 1123 has a thickness of
To
The thickness of the third transparent conductive film layer 1124 is
To
Specifically, the thickness of the first transparent conductive thin film layer 1121 may be
Or
The thickness of the metal layer 1122 may be
Or
The thickness of the second transparent conductive thin film layer 1123 may be
Or
The thickness of the third transparent conductive film layer 1124 may be
Or
It should be noted that the first surface 1121a may be an upper surface of the first transparent conductive thin film layer 1121, and the second surface 1121b may be a lower surface of the first transparent conductive thin film layer 1121. Of course, the first surface 1121a may also be a lower surface of the first transparent conductive thin film layer 1121, and the second surface 1121b may also be an upper surface of the first transparent conductive thin film layer 1121. In this embodiment, without specific description, the first surface 1121a is defined as an upper surface of the first transparent conductive thin film layer 1121, and the second surface 1121b is defined as a lower surface of the first transparent conductive thin film layer 1121.
The passivation layer 110 and the planarization layer 111 of the binding region 10b are provided with a first contact hole, and the first contact hole extends from a surface of the planarization layer 111 on a side away from the passivation layer 110 to a surface of the source drain layer 109 on a side away from the interlayer insulating layer 108. The pixel electrode layer 112 is connected to the source/drain electrode layer 109 through a first contact hole. The passivation layer 110 and the planarization layer 111 of the pixel region 10a are provided with a second contact hole extending from a surface of the planarization layer 111 on a side away from the passivation layer 110 to a surface of the source drain layer 109 on a side away from the interlayer insulating layer 108. The pixel electrode layer 112 is connected to the source drain layer 109 through a second contact hole.
Wherein the pixel defining layer 113 of the binding region 10b is provided with a first groove 114. The first groove 114 extends from a side surface of the pixel defining layer 113 away from the pixel electrode layer 112 to a side surface of the third transparent conductive film layer 1124 of the binding region 10b away from the first surface 1121 a. The pixel defining layer 113 of the pixel region 10a is provided with a second groove 115. The second groove 115 extends from the surface of the pixel defining layer 113 away from the pixel electrode layer 112 to the surface of the third transparent conductive film layer 1124 of the pixel region 10a away from the first surface 1121 a.
The display panel 10 provided in the embodiment of the present application includes a glass substrate 101, a light shielding layer 102, a buffer layer 103, a semiconductor layer 104, a conductor layer 105, a gate insulating layer 106, a gate metal layer 107, an interlayer insulating layer 108, a source/drain electrode layer 109, a passivation layer 110, a planarization layer 111, a pixel electrode layer 112, and a pixel definition layer 113. The pixel electrode layer 112 wraps the first transparent conductive thin film layer 1121, the metal layer 1122 and the second transparent conductive thin film layer 1123 through the third transparent conductive thin film layer 1124, so that the metal layer can be protected from being oxidized. Since the third transparent conductive thin film layer 1124 is covered, the thickness of the second transparent conductive thin film layer 1123 can be reduced, making the etching process easier to handle, while the taper angle (taper angle) is slowed down. And the thickness of the third transparent conductive thin film layer 1124 is thicker, which is more beneficial to the development and selection of OLED devices.
The present invention provides a method for manufacturing a display panel, which is described in detail below. Referring to fig. 4, fig. 4 is a first flowchart illustrating a display panel manufacturing method according to an embodiment of the present disclosure.
A first transparent conductive film layer is provided 201, the first transparent conductive film layer including a first side and a second side disposed opposite to each other.
202 are provided with a metal layer on the first side.
203 a second transparent conductive thin film layer is disposed on the metal layer.
204, a third transparent conductive thin film layer is arranged on the second transparent conductive thin film layer, wherein the third transparent conductive thin film layer covers one side of the second transparent conductive thin film layer far away from the metal layer and wraps the edges of the first transparent conductive thin film layer, the metal layer and the second transparent conductive thin film layer to form a pixel electrode layer.
According to the display panel manufacturing method, the first transparent conductive thin film layer, the metal layer and the second transparent conductive thin film layer are wrapped by the third transparent conductive thin film layer, and the metal layer can be protected from being oxidized.
Referring to fig. 5, fig. 5 is a second flowchart illustrating a display panel manufacturing method according to an embodiment of the present disclosure.
301 a glass substrate is provided and cleaned.
302 deposit a light shield layer on the glass substrate.
The shading layer is located in the pixel area.
303 depositing a buffer layer on the glass substrate and the light-shielding layer.
Wherein, the buffer layer covers the glass substrate and the shading layer.
304 a semiconductor layer is deposited on the buffer layer.
Wherein, a pattern is made on the semiconductor layer by adopting a yellow light or etching method.
The yellow light is a process of performing glue coating, soft baking, exposure, development and hard baking on wafers such as silicon wafers to enable the wafers to be photoetched to form a certain pattern. Etching (etching) is a technique in which material is removed using a chemical reaction or physical impact. In the embodiment of the application, the semiconductor layer material can be coated on the buffer layer, and then the pattern of the semiconductor layer is photoetched through a yellow light process; or after the semiconductor layer material is deposited on the buffer layer, patterning is carried out by an etching method.
Wherein the semiconductor layer is disposed in the pixel region.
305 a gate insulating layer is deposited over the semiconductor layer.
A gate metal layer is deposited 306 on the gate insulation layer.
The method comprises the steps of manufacturing a graph of a grid metal layer by adopting a yellow light or etching method, manufacturing a grid insulation layer by adopting the yellow light or etching method by utilizing the graph of the grid metal layer as self-alignment, and etching all the grid insulation layer which is not covered by the grid metal layer.
307 the semiconductor layer, the gate insulating layer, and the gate metal layer are subjected to Plasma (Plasma) treatment over the entire surface, and a part of the semiconductor layer is formed as a conductor layer.
The plasma (plasma) is a gas substance in an ionized state composed of negatively charged particles (negative ions and electrons), positively charged particles (positive ions), and uncharged particles. Usually in parallel with the solid, liquid, gaseous state of matter, referred to as the fourth state of matter. By applying plasma technology, a new surface structure can be obtained on the semiconductor layer. Specifically, for a semiconductor layer without a gate insulating layer and a gate metal layer over it, the resistance is reduced after plasma treatment to form a conductor layer; the semiconductor layer under the gate insulating layer is not processed to maintain semiconductor characteristics as a Thin Film Transistor (TFT) channel. In a display panel, a thin film transistor may be used as a switching device or a driving device, and thus, the thin film transistor forms a channel that may serve as a path channel for moving charge carriers.
An interlayer insulating layer is deposited 308 over the buffer layer, the conductor layer, and the gate metal layer.
Wherein, a third contact hole and a fourth contact hole are etched in the interlayer insulating layer.
309 a source drain layer is deposited on the interlayer insulating layer.
And the source drain layer of the pixel region is connected with the conductor layer through a third contact hole and a fourth contact hole which are arranged on the interlayer insulating layer after patterning. The source drain layer of the binding region is arranged on the interlayer insulating layer and partially covers the interlayer insulating layer.
310 depositing a passivation layer on the interlayer insulating layer and the source drain layer.
The passivation layer covers the source drain layer and the interlayer insulating layer.
311 a planarization layer is deposited on the passivation layer.
And manufacturing a first contact hole and a second contact hole on the passivation layer and the planarization layer by adopting a yellow light process. The passivation layer and the planarization layer of the binding region are provided with first contact holes, and the first contact holes extend from the surface of one side, away from the passivation layer, of the planarization layer to the surface of one side, away from the interlayer insulating layer, of the source drain layer. The passivation layer and the planarization layer of the pixel region are provided with second contact holes, and the second contact holes extend from the surface of one side, away from the passivation layer, of the planarization layer to the surface of one side, away from the interlayer insulating layer, of the source drain layer.
312 a pixel electrode layer is disposed on the planarization layer.
The pixel electrode layer is connected with the source drain electrode layer through the first contact hole and the second contact hole.
313 a pixel defining layer is provided on the planarization layer and the pixel electrode layer.
After the pixel defining layer is arranged, a first groove is arranged on the pixel defining layer of the binding region, a second groove is arranged on the pixel defining layer of the pixel region, and the first groove extends from the surface of one side, far away from the pixel electrode layer, of the pixel defining layer to the surface of one side, far away from the first surface, of the third transparent conductive thin film layer of the binding region. The second groove extends from the surface of one side, away from the pixel electrode layer, of the pixel definition layer to the surface of one side, away from the first surface, of the third transparent conductive thin film layer of the pixel area. A cathode layer is then deposited and encapsulated.
According to the display panel manufacturing method provided by the embodiment of the application, the first transparent conductive thin film layer, the metal layer and the second transparent conductive thin film layer are wrapped by the third transparent conductive thin film layer, so that the metal layer can be protected from being oxidized. Due to the fact that the third transparent conductive thin film layer is covered, the thickness of the second transparent conductive thin film layer can be reduced, the etching process is easier to operate, and meanwhile the taper angle is slowed down. And the thickness of the third transparent conductive film layer is thicker, which is more beneficial to the development and selection of OLED devices.
The display panel and the display panel manufacturing method provided by the embodiment of the present application are described in detail, and the principle and the embodiment of the present application are described herein by applying specific examples, and the description of the above embodiments is only used to help understanding the present application. Meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. A display panel is characterized in that the display panel is provided with a pixel area and a binding area, and the pixel area and the binding area are adjacently arranged; the display panel includes:
a pixel electrode layer at least partially disposed within the binding region, the pixel electrode layer comprising:
the first transparent conductive thin film layer comprises a first surface and a second surface which are oppositely arranged;
a metal layer disposed on the first side;
the second transparent conductive thin film layer is arranged on one side, far away from the first surface, of the metal layer;
and the third transparent conductive thin film layer covers one side of the second transparent conductive thin film layer, which is far away from the metal layer, and wraps the edges of the first transparent conductive thin film layer, the metal layer and the second transparent conductive thin film layer.
2. The display panel according to claim 1, further comprising an interlayer insulating layer, a source drain layer, a passivation layer, a planarization layer, and a pixel defining layer; the planarization layer is arranged on one side, close to the first transparent conductive film layer, of the pixel electrode layer; the passivation layer is arranged on one side, far away from the pixel electrode layer, of the planarization layer; the source drain layer is arranged on one side, far away from the planarization layer, of the passivation layer; the interlayer insulating layer is arranged on one side, away from the passivation layer, of the source drain layer, the source drain layer partially covers the interlayer insulating layer, and the passivation layer covers the source drain layer and the interlayer insulating layer; the pixel defining layer is arranged on one side of the pixel electrode layer far away from the planarization layer and covers the planarization layer;
the passivation layer and the planarization layer of the binding region are provided with a first contact hole; the first contact hole extends from the surface of one side, away from the passivation layer, of the planarization layer to the surface of one side, away from the interlayer insulating layer, of the source drain layer; the pixel electrode layer is connected with the source drain electrode layer through the first contact hole.
3. The display panel according to claim 2, wherein the passivation layer and the planarization layer of the pixel region are provided with a second contact hole extending from a surface of the planarization layer away from the passivation layer to a surface of the source drain layer away from the interlayer insulating layer; the pixel electrode layer is connected with the source drain electrode layer through the second contact hole.
4. The display panel according to claim 3, wherein the pixel defining layer of the binding region is provided with a first groove; the first groove extends from the surface of one side, away from the pixel electrode layer, of the pixel definition layer to the surface of one side, away from the first face, of the third transparent conductive thin film layer of the binding region.
5. The display panel according to claim 4, wherein the pixel defining layer of the pixel region is provided with a second groove; the second groove extends from the surface of one side, away from the pixel electrode layer, of the pixel defining layer to the surface of one side, away from the first face, of the third transparent conductive thin film layer of the pixel area.
6. The display panel according to any one of claims 1 to 5, wherein the material of the first transparent conductive thin film layer, the second transparent conductive thin film layer, and the third transparent conductive thin film layer is indium tin oxide; the metal layer is made of silver.
7. The display panel according to claim 6, wherein the first transparent conductive thin film layer has a thickness of
To
The thickness of the metal layer is
To
The thickness of the second transparent conductive film layer is
To
The thickness of the third transparent conductive film layer is
To
8. The display panel according to any one of claims 2 to 5, wherein the material of the interlayer insulating layer and the passivation layer is a silicon oxide derivative, a silicon nitride derivative, or a combination thereof, and the thickness of the interlayer insulating layer is
To
The thickness of the passivation layer is
To
9. The display panel according to any one of claims 2 to 5, wherein the material of the planarization layer is a photoresist material, and the thickness of the planarization layer is 0.5 μm to 3 μm.
10. A method for manufacturing a display panel includes:
providing a first transparent conductive film layer, wherein the first transparent conductive film layer comprises a first surface and a second surface which are oppositely arranged;
arranging a metal layer on the first surface;
arranging a second transparent conductive film layer on the metal layer;
arranging a third transparent conductive thin film layer on the second transparent conductive thin film layer, wherein the third transparent conductive thin film layer covers one side of the second transparent conductive thin film layer, which is far away from the metal layer, and wraps the edges of the first transparent conductive thin film layer, the metal layer and the second transparent conductive thin film layer to form a pixel electrode layer;
and at least partially arranging the pixel electrode layer in a binding region of the display panel, wherein the binding region is arranged adjacent to the pixel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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| CN112701129A (en) * | 2021-01-07 | 2021-04-23 | 深圳市华星光电半导体显示技术有限公司 | Display panel and manufacturing method thereof |
| CN112909200A (en) * | 2021-01-20 | 2021-06-04 | 深圳市华星光电半导体显示技术有限公司 | Display panel and preparation method thereof |
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