CN109119440B - OLED backboard and manufacturing method thereof - Google Patents
OLED backboard and manufacturing method thereof Download PDFInfo
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- CN109119440B CN109119440B CN201810805876.1A CN201810805876A CN109119440B CN 109119440 B CN109119440 B CN 109119440B CN 201810805876 A CN201810805876 A CN 201810805876A CN 109119440 B CN109119440 B CN 109119440B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/122—Pixel-defining structures or layers, e.g. banks
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
Abstract
The invention provides an OLED (organic light emitting diode) backboard and a manufacturing method thereof. The transparent conductor layer and the pixel electrode in the OLED backboard form a transparent capacitor structure, and the OLED light emitting area is also positioned above the transparent capacitor structure, namely the capacitor area and the light emitting area of the OLED backboard are the same area.
Description
Technical Field
The invention relates to the technical field of display, in particular to an OLED (organic light emitting diode) backboard and a manufacturing method thereof.
Background
An Organic Light Emitting diode Display (OLED) has many advantages of self-luminescence, low driving voltage, high luminous efficiency, short response time, high definition and contrast, a viewing angle of nearly 180 °, a wide temperature range, flexible Display, large-area full color Display, and the like, and is considered as a Display device with the most potential for development.
OLED devices typically include: the electron injection device comprises a substrate, an anode arranged on the substrate, a hole injection layer arranged on the anode, a hole transport layer arranged on the hole injection layer, a luminescent layer arranged on the hole transport layer, an electron transport layer arranged on the luminescent layer, an electron injection layer arranged on the electron transport layer and a cathode arranged on the electron injection layer. The light emitting principle of the OLED device is that a semiconductor material and an organic light emitting material emit light under the drive of an electric field through carrier injection and recombination. Specifically, an Indium Tin Oxide (ITO) electrode and a metal electrode are generally used as an anode and a cathode of the device, respectively, and under a certain voltage, electrons and holes are injected into an electron transport layer and a hole transport layer from the cathode and the anode, respectively, and the electrons and the holes migrate to a light emitting layer through the electron transport layer and the hole transport layer, respectively, and meet in the light emitting layer to form excitons and excite light emitting molecules, which emit visible light through radiative relaxation.
OLEDs can be classified into two broad categories, namely, direct addressing and thin film transistor Matrix addressing, namely, Passive Matrix OLEDs (PMOLEDs) and Active Matrix OLEDs (AMOLEDs) according to driving methods. The AMOLED has pixels arranged in an array, belongs to an active display type, has high luminous efficiency, and is generally used as a large-sized display device with high definition.
The AMOLED display device generally includes an OLED backplane and an organic material layer disposed on the OLED backplane, and a capacitance region in the existing OLED backplane has a smaller area of a light emitting region due to the presence of a metal electrode plate, which limits the fabrication of the high resolution AMOLED display device.
Disclosure of Invention
The invention aims to provide an OLED backboard which is large in light-emitting area, high in aperture opening ratio and applicable to a high-resolution OLED display panel.
The invention also aims to provide a manufacturing method of the OLED backboard, which can increase the light-emitting area of the OLED backboard and the aperture ratio of the OLED backboard.
To achieve the above object, the present invention provides an OLED backplane comprising: the pixel structure comprises a substrate, a buffer layer arranged on the substrate, an active layer and a transparent conductor layer which are arranged on the buffer layer and arranged at intervals, a grid electrode insulating layer arranged on the active layer, a grid electrode arranged on the grid electrode insulating layer, an interlayer insulating layer covering the buffer layer, the active layer, the transparent conductor layer and the grid electrode, a source electrode and a drain electrode arranged on the interlayer insulating layer, a passivation layer arranged on the interlayer insulating layer, the source electrode and the drain electrode, a flat layer arranged on the passivation layer, a pixel electrode arranged on the flat layer and a pixel defining layer arranged on the flat layer and the pixel electrode;
the transparent conductor layer and the pixel electrode form a transparent capacitor structure; the pixel defining layer defines an OLED light emitting area over the transparent capacitive structure.
The active layer comprises a channel region positioned below the gate insulation layer, and a source contact region and a drain contact region positioned at two sides of the channel region; the source electrode is in contact with the source electrode contact region through a first via hole penetrating through the interlayer insulating layer, and the drain electrode is in contact with the drain electrode contact region through a second via hole penetrating through the interlayer insulating layer.
The pixel electrode is in contact with the drain electrode through a third through hole penetrating through the passivation layer and the flat layer, and is in contact with the interlayer insulating layer through a first opening penetrating through the passivation layer and the flat layer.
The interlayer insulating layer is used as a dielectric layer of the transparent capacitor structure.
The pixel defining layer is provided with a second opening which exposes the pixel electrode positioned above the transparent conductor layer, and the second opening defines an OLED light emitting area above the transparent capacitor structure.
The OLED backboard further comprises a light shielding layer which is arranged between the substrate base plate and the buffer layer and is positioned below the active layer.
The thickness of the light shielding layer is
The light shielding layer is made of one or more of molybdenum, aluminum, copper and titanium.
The thickness of the buffer layer is
The buffer layer is one or the combination of two of a silicon oxide layer and a silicon nitride layer; the thickness of the active layer and the transparent conductor layer are both
The active layer and the transparent conductor layer are made of one of indium gallium zinc oxide, indium zinc tin oxide and indium gallium zinc tin oxide; the thickness of the gate insulating layer is
The grid insulation layer is one or the combination of two of a silicon oxide layer and a silicon nitride layer; the grid electrode is made of an alloy consisting of one or more of molybdenum, aluminum, copper and titanium; the thickness of the grid electrode is
The thickness of the interlayer insulating layer is
The interlayer insulating layer is one or the combination of two of a silicon oxide layer and a silicon nitride layer; the source electrode and the drain electrode are made of one or more of molybdenum, aluminum, copper and titanium; the thickness of the source electrode and the drain electrode are both
The thickness of the passivation layer is
The passivation layer is one or the combination of two of a silicon oxide layer and a silicon nitride layer.
The invention also provides a manufacturing method of the OLED backboard, which comprises the following steps:
step S1, providing a substrate, and forming a light-shielding layer and a buffer layer covering the substrate and the light-shielding layer on the substrate;
step S2, forming a first semiconductor layer and a second semiconductor layer on the buffer layer at an interval; the first semiconductor layer is positioned above the light shielding layer;
step S3, forming a first insulating layer covering the buffer layer, the first semiconductor layer, and the second semiconductor layer, depositing a first metal layer on the first insulating layer, and patterning the first metal layer to form a gate electrode over the first semiconductor layer;
step S4, etching the first insulating layer by taking the grid electrode as a shield to obtain a grid electrode insulating layer positioned below the grid electrode;
step S5, performing plasma processing on the first semiconductor layer and the second semiconductor layer with the gate and the gate insulating layer as a mask to obtain an active layer and a transparent conductor layer disposed at an interval with the active layer; the active layer comprises a channel region positioned below the gate insulation layer, and a source contact region and a drain contact region positioned at two sides of the channel region;
step S6, forming an interlayer insulating layer covering the buffer layer, the active layer, the transparent conductor layer, and the gate, opening the interlayer insulating layer to form a first via hole and a second via hole respectively exposing the source contact region and the drain contact region, depositing a second metal layer on the interlayer insulating layer, and patterning the second metal layer to form a source electrode and a drain electrode; the source electrode is contacted with the source electrode contact region through the first through hole, and the drain electrode is contacted with the drain electrode contact region through the second through hole;
step S7, forming a passivation layer covering the interlayer insulating layer, the source electrode, and the drain electrode, forming a planarization layer on the passivation layer, opening the passivation layer and the planarization layer, and forming a third via hole exposing the drain electrode and a first opening exposing the interlayer insulating layer above the transparent conductor layer; forming a pixel electrode on the planarization layer; the pixel electrode is contacted with the drain electrode through the third through hole and is contacted with the interlayer insulating layer through the first opening;
the transparent conductor layer and the pixel electrode form a transparent capacitor structure, and the interlayer insulating layer is used as a dielectric layer of the transparent capacitor structure;
step S8, forming a pixel defining layer on the planarization layer and the pixel electrode, and opening the pixel defining layer to form a second opening exposing the pixel electrode above the transparent conductor layer, wherein the second opening defines an OLED light emitting area above the transparent capacitor structure.
The thickness of the light shielding layer is
The light shielding layer is made of an alloy consisting of one or more of molybdenum, aluminum, copper and titanium; the thickness of the buffer layer is
The buffer layer is one or the combination of two of a silicon oxide layer and a silicon nitride layer; the thickness of the active layer and the transparent conductor layer are both
The active layer and the transparent conductor layer are made of one of indium gallium zinc oxide, indium zinc tin oxide and indium gallium zinc tin oxide; the thickness of the gate insulating layer is
The grid insulation layer is one or the combination of two of a silicon oxide layer and a silicon nitride layer; the grid electrode is made of an alloy consisting of one or more of molybdenum, aluminum, copper and titanium; the thickness of the grid electrode is
The thickness of the interlayer insulating layer is
The interlayer insulating layer is one or the combination of two of a silicon oxide layer and a silicon nitride layer; the source electrode and the drain electrode are made of one or more of molybdenum, aluminum, copper and titanium; the thickness of the source electrode and the drain electrode are both
The thickness of the passivation layer is
The passivation layer is one or the combination of two of a silicon oxide layer and a silicon nitride layer.
The invention has the beneficial effects that: the transparent conductor layer and the pixel electrode in the OLED backboard form a transparent capacitor structure, and the OLED light emitting area is also positioned above the transparent capacitor structure, namely the capacitor area and the light emitting area of the OLED backboard are the same area. According to the manufacturing method of the OLED backboard, the transparent conductor layer and the pixel electrode form the transparent capacitor structure, and the OLED light emitting area is also located above the transparent capacitor structure, so that the light emitting area of the OLED backboard and the opening ratio of the OLED backboard are increased.
Drawings
For a better understanding of the nature and technical aspects of the present invention, reference should be made to the following detailed description of the invention, taken in conjunction with the accompanying drawings, which are provided for purposes of illustration and description and are not intended to limit the invention.
In the drawings, there is shown in the drawings,
FIG. 1 is a schematic structural diagram of an OELD backplane according to the present invention;
FIG. 2 is a flow chart of a method for fabricating an OELD backplane according to the present invention;
FIG. 3 is a schematic diagram of a step S1 of the method for fabricating an OELD backplane according to the present invention;
fig. 4 is a schematic diagram of step S2 of the method for manufacturing an OELD backplane according to the present invention;
FIG. 5 is a schematic diagram of a step S3 of the method for fabricating an OELD backplane according to the present invention;
FIG. 6 is a schematic diagram of a step S4 of the method for fabricating an OELD backplane according to the present invention;
fig. 7 is a schematic diagram of step S5 of the method for manufacturing an OELD backplane according to the present invention;
fig. 8 is a schematic diagram of step S6 of the method for manufacturing an OELD backplane according to the present invention;
fig. 9 is a schematic diagram of step S7 of the method for manufacturing an OELD backplane according to the present invention;
fig. 10 is a schematic diagram of step S8 of the method for manufacturing an OELD backplane according to the present invention.
Detailed Description
To further illustrate the technical means and effects of the present invention, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings.
Referring to fig. 1, the present invention provides an OLED backplane, including: a substrate 10, a buffer layer 30 disposed on the substrate 10, an active layer 43 and a transparent conductor layer 44 disposed on the buffer layer 30 at an interval, a gate insulating layer 52 disposed on the active layer 43, a gate 60 disposed on the gate insulating layer 52, an interlayer insulating layer 70 covering the buffer layer 30, the active layer 43, the transparent conductor layer 44 and the gate 60, a source 81 and a drain 82 disposed on the interlayer insulating layer 70, a passivation layer 90 disposed on the interlayer insulating layer 70, the source 81 and the drain 82, a planarization layer 100 disposed on the passivation layer 90, a pixel electrode 110 disposed on the planarization layer 100, and a pixel defining layer 120 disposed on the planarization layer 100 and the pixel electrode 110;
the transparent conductor layer 44 and the pixel electrode 110 form a transparent capacitor structure; the pixel defining layer 120 defines an OLED light emitting area over the transparent capacitive structure.
It should be noted that the transparent conductor layer 44 and the pixel electrode 110 of the present invention form a transparent capacitor structure, and the OLED light emitting region is also located above the transparent capacitor structure, i.e. the capacitor region and the light emitting region of the OLED backplane of the present invention are the same region, because the transparent capacitor structure does not affect the aperture opening ratio of the OLED backplane, the light emitting area of the OLED backplane of the present invention is larger, the aperture opening ratio of the OLED backplane is increased, and the OLED backplane can be applied to a high resolution OLED display panel.
Specifically, the active layer 43 includes a channel region 431 located below the gate insulating layer 52, and a source contact region 432 and a drain contact region 433 located at both sides of the channel region 431; the source electrode 81 is in contact with a source contact region 432 through a first via hole 71 penetrating the interlayer insulating layer 70, and the drain electrode 82 is in contact with a drain contact region 433 through a second via hole 72 penetrating the interlayer insulating layer 70.
Specifically, the pixel electrode 110 contacts the drain electrode 82 through the third via hole 101 penetrating through the passivation layer 90 and the planarization layer 100, and contacts the interlayer insulating layer 70 through the first opening 102 penetrating through the passivation layer 90 and the planarization layer 100.
Specifically, the interlayer insulating layer 70 is used as a dielectric layer of the transparent capacitor structure, that is, in the present invention, the passivation layer 90 and the planarization layer 100 are opened, and only one layer of the interlayer insulating layer 70 is used as the dielectric layer of the transparent capacitor structure, so as to increase the power storage capability of the transparent capacitor structure.
Specifically, the pixel defining layer 120 is provided with a second opening 121 exposing the pixel electrode 110 above the transparent conductor layer 44, and the second opening 121 defines an OLED light emitting area above the transparent capacitor structure.
Specifically, the active layer 43, the gate insulating layer 52, the gate electrode 60, the interlayer insulating layer 70, the source electrode 81, the drain electrode 82, the passivation layer 90, the planarization layer 100, and the pixel electrode 110 form a thin film transistor structure. While the pixel electrode 110 may serve as an anode of a subsequent OLED device for emitting light.
Specifically, the OLED backplane further includes a light shielding layer 20 disposed between the substrate 10 and the buffer layer 30 and below the active layer 43, so as to prevent the threshold voltage of the thin film transistor structure from drifting when the active layer 43 is illuminated.
Specifically, the light-shielding layer 20 has a thickness of
The light shielding layer 20 is made of an alloy consisting of one or more of molybdenum (Mo), aluminum (Al), copper (Cu) and titanium (Ti);
the buffer layer 30 has a thickness of
The buffer layer 30 is one or a combination of two of a silicon oxide layer and a silicon nitride layer, that is, the buffer layer 30 may be a silicon oxide layer or a silicon nitride layer, or may be a multilayer structure in which a silicon oxide layer and a silicon nitride layer are stacked;
the thickness of the active layer 43 and the transparent conductor layer 44 are both
The active layer 43 and the transparent conductor layer 44 are made of one of Indium Gallium Zinc Oxide (IGZO), Indium Zinc Tin Oxide (IZTO) and Indium Gallium Zinc Tin Oxide (IGZTO);
the gate insulating layer 52 has a thickness of
The gate insulating layer 52 is one or a combination of two of a silicon oxide layer and a silicon nitride layer; the material of the grid 60 is an alloy consisting of one or more of molybdenum, aluminum, copper and titanium; the thickness of the gate 60 is
The interlayer insulating layer 70 has a thickness of
The interlayer insulating layer 70 is one or a combination of two of a silicon oxide layer and a silicon nitride layer; the source electrode 81 and the drain electrode 82 are made of an alloy consisting of one or more of molybdenum, aluminum, copper and titanium; the source electrode 81 and the drain electrode 82 each have a thickness
The thickness of the passivation layer 90 is
The passivation layer 90 is one or a combination of two of a silicon oxide layer and a silicon nitride layer.
Referring to fig. 2, based on the above OELD backplane, the present invention further provides a method for manufacturing an OLED backplane, including the following steps:
step S1, please refer to fig. 3, providing a substrate 10, and forming a light-shielding layer 20 and a buffer layer 30 covering the substrate 10 and the light-shielding layer 20 on the substrate 10.
Specifically, the light-shielding layer 20 has a thickness of
The light shielding layer 20 is made of an alloy of one or more of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti).
Specifically, the buffer layer 30 has a thickness of
The buffer layer 30 is one or a combination of two of a silicon oxide layer and a silicon nitride layer, that is, the buffer layer 30 may be a silicon oxide layer or a silicon nitride layer, or may be a multilayer structure in which a silicon oxide layer and a silicon nitride layer are stacked.
Step S2, referring to fig. 4, forming a first semiconductor layer 41 and a second semiconductor layer 42 on the buffer layer 30 at an interval; the first semiconductor layer 41 is located above the light-shielding layer 20.
Step S3, please refer to fig. 5, a first insulating layer 51 is formed to cover the buffer layer 30, the first semiconductor layer 41 and the second semiconductor layer 42, a first metal layer is deposited on the first insulating layer 51, and the first metal layer is patterned to form a gate 60 located above the first semiconductor layer 41.
In step S4, referring to fig. 6, the first insulating layer 51 is etched using the gate 60 as a mask, so as to obtain a gate insulating layer 52 located under the gate 60.
Specifically, the thickness of the gate insulating layer 52 is
The gate insulating layer 52 is one or a combination of two of a silicon oxide layer and a silicon nitride layer; the material of the grid 60 is an alloy consisting of one or more of molybdenum, aluminum, copper and titanium; the thickness of the gate 60 is
Step S5, referring to fig. 7, performing plasma treatment on the first semiconductor layer 41 and the second semiconductor layer 42 by using the gate electrode 60 and the gate insulating layer 52 as a shielding layer, so that the resistance of the portion of the first semiconductor layer 41 and the second semiconductor layer 42 which is not shielded by the gate electrode 60 and the gate insulating layer 52 is reduced, and the portion of the first semiconductor layer 41 and the second semiconductor layer 42 is subjected to a conductor treatment to make the property of the portion of the first semiconductor layer 41 and the second semiconductor layer 42 approach a conductor, thereby obtaining an active layer 43 and a transparent conductor layer 44 spaced apart from the active layer 43; the active layer 43 includes a channel region 431 under the gate insulating layer 52 and source and drain contact regions 432 and 433 on both sides of the channel region 431.
Specifically, the thicknesses of the active layer 43 and the transparent conductor layer 44 are both
The active layer 43 and the transparent conductor layer 44 are made of one of Indium Gallium Zinc Oxide (IGZO), Indium Zinc Tin Oxide (IZTO), and Indium Gallium Zinc Tin Oxide (IGZTO).
Step S6, referring to fig. 8, forming an interlayer insulating layer 70 covering the buffer layer 30, the active layer 43, the transparent conductor layer 44 and the gate 60, opening the interlayer insulating layer 70 to form a first via hole 71 and a second via hole 72 respectively exposing the source contact region 432 and the drain contact region 433, depositing a second metal layer on the interlayer insulating layer 70, and patterning the second metal layer to form a source 81 and a drain 82; the source 81 is in contact with a source contact region 432 through a first via 71 and the drain 82 is in contact with a drain contact region 433 through a second via 72.
Specifically, the interlayer insulating layer 70 has a thickness of
The interlayer insulating layer 70 is one or a combination of two of a silicon oxide layer and a silicon nitride layer; the source electrode 81 and the drain electrode 82 are made of an alloy consisting of one or more of molybdenum, aluminum, copper and titanium; the source electrode 81 and the drain electrode 82 each have a thickness
Step S7, please refer to fig. 9, in which a passivation layer 90 covering the interlayer insulating layer 70, the source electrode 81 and the drain electrode 82 is formed, a planarization layer 100 is formed on the passivation layer 90, the passivation layer 90 and the planarization layer 100 are opened, and a third via hole 101 exposing the drain electrode 82 and a first opening 102 exposing the interlayer insulating layer 70 above the transparent conductive layer 44 are formed; forming a pixel electrode 110 on the planarization layer 100; the pixel electrode 110 contacts the drain electrode 82 through the third via hole 101 and contacts the interlayer insulating layer 70 through the first opening 102;
the transparent conductor layer 44 and the pixel electrode 110 form a transparent capacitor structure, and the interlayer insulating layer 70 is used as a dielectric layer of the transparent capacitor structure, that is, in the invention, the passivation layer 90 and the planarization layer 100 are perforated, and only one layer of the interlayer insulating layer 70 is used as the dielectric layer of the transparent capacitor structure, so as to increase the power storage capability of the transparent capacitor structure.
Specifically, the active layer 43, the gate insulating layer 52, the gate electrode 60, the interlayer insulating layer 70, the source electrode 81, the drain electrode 82, the passivation layer 90, the planarization layer 100, and the pixel electrode 110 form a thin film transistor structure. While the pixel electrode 110 may serve as an anode of a subsequent OLED device for emitting light.
Specifically, the thickness of the passivation layer 90 is
The passivation layer 90 is one or a combination of two of a silicon oxide layer and a silicon nitride layer.
In step S8, referring to fig. 10, a pixel defining layer 120 is formed on the planarization layer 100 and the pixel electrode 110, and the pixel defining layer 120 is opened to form a second opening 121 exposing the pixel electrode 110 above the transparent conductive layer 44, wherein the second opening 121 defines an OLED light emitting area above the transparent capacitor structure.
It should be noted that the transparent conductor layer 44 and the pixel electrode 110 of the present invention form a transparent capacitor structure, and the OLED light emitting region is also located above the transparent capacitor structure, i.e. the capacitor region and the light emitting region of the OLED backplane of the present invention are the same region, because the transparent capacitor structure does not affect the aperture opening ratio of the OLED backplane, the light emitting area of the OLED backplane of the present invention is larger, the aperture opening ratio of the OLED backplane is increased, and the OLED backplane can be applied to a high resolution OLED display panel.
In summary, the transparent conductor layer and the pixel electrode in the OLED backplane of the present invention form a transparent capacitor structure, and the OLED light-emitting region is also located above the transparent capacitor structure, i.e., the capacitor region and the light-emitting region of the OLED backplane of the present invention are the same region. According to the manufacturing method of the OLED backboard, the transparent conductor layer and the pixel electrode form the transparent capacitor structure, and the OLED light emitting area is also located above the transparent capacitor structure, so that the light emitting area of the OLED backboard and the opening ratio of the OLED backboard are increased.
As described above, it will be apparent to those skilled in the art that other various changes and modifications may be made based on the technical solution and concept of the present invention, and all such changes and modifications are intended to fall within the scope of the appended claims.
Claims (7)
1. An OLED backplane, comprising: a substrate (10), a buffer layer (30) arranged on the substrate (10), an active layer (43) and a transparent conductor layer (44) arranged on the buffer layer (30) at intervals, a gate insulation layer (52) arranged on the active layer (43), a gate (60) arranged on the gate insulation layer (52), a cover layer (30) and the active layer (43), an interlayer insulating layer (70) including a transparent conductor layer (44) and a gate electrode (60), a source electrode (81) and a drain electrode (82) provided on the interlayer insulating layer (70), a passivation layer (90) provided on the interlayer insulating layer (70), the source electrode (81) and the drain electrode (82), a planarization layer (100) provided on the passivation layer (90), a pixel electrode (110) provided on the planarization layer (100), and a pixel defining layer (120) provided on the planarization layer (100) and the pixel electrode (110);
the transparent conductor layer (44) and the pixel electrode (110) form a transparent capacitor structure; the pixel defining layer (120) defines an OLED light emitting area over the transparent capacitive structure;
the pixel electrode (110) is in contact with the drain electrode (82) through a third via hole (101) penetrating through the passivation layer (90) and the flat layer (100), and is in contact with the interlayer insulating layer (70) through a first opening (102) penetrating through the passivation layer (90) and the flat layer (100);
the pixel defining layer (120) is provided with a second opening (121) exposing the pixel electrode (110) positioned above the transparent conductor layer (44), and the second opening (121) defines an OLED light emitting area above the transparent capacitor structure;
the thickness of the buffer layer (30) is
The buffer layer (30) is one or the combination of two of a silicon oxide layer and a silicon nitride layer; the thickness of the active layer (43) and the transparent conductor layer (44) are both
The active layer (43) and the transparent conductor layer (44) are made of one of indium gallium zinc oxide, indium zinc tin oxide and indium gallium zinc tin oxide; the thickness of the gate insulating layer (52) is
The gate insulating layer (52) is one or a combination of two of a silicon oxide layer and a silicon nitride layer; the grid (60) is made of an alloy consisting of one or more of molybdenum, aluminum, copper and titanium; the thickness of the grid electrode (60) is
The thickness of the interlayer insulating layer (70) is
The interlayer insulating layer (70) is one or the combination of two of a silicon oxide layer and a silicon nitride layer; the source electrode (81) and the drain electrode (82) are made of an alloy consisting of one or more of molybdenum, aluminum, copper and titanium; the thickness of the source electrode (81) and the thickness of the drain electrode (82) are both
The thickness of the passivation layer (90) is
The passivation layer (90) is one or the combination of two of a silicon oxide layer and a silicon nitride layer.
2. The OLED backplane of claim 1, wherein the active layer (43) comprises a channel region (431) under the gate insulation layer (52) and source and drain contact regions (432, 433) on both sides of the channel region (431); the source electrode (81) is in contact with a source contact region (432) through a first via (71) that penetrates the interlayer insulating layer (70), and the drain electrode (82) is in contact with a drain contact region (433) through a second via (72) that penetrates the interlayer insulating layer (70).
3. The OLED backplane according to claim 1, wherein the interlayer insulating layer (70) serves as a dielectric layer of the transparent capacitive structure.
4. The OLED backplane according to claim 1, further comprising a light shielding layer (20) disposed between the substrate (10) and the buffer layer (30) and below the active layer (43).
5. The OLED backplane according to claim 4, wherein the light-shielding layer (20) has a thickness of
The shading layer (20) is made of one or more of molybdenum, aluminum, copper and titanium.
6. A manufacturing method of an OLED backboard is characterized by comprising the following steps:
step S1, providing a substrate (10), and forming a light shielding layer (20) and a buffer layer (30) covering the substrate (10) and the light shielding layer (20) on the substrate (10);
step S2, forming a first semiconductor layer (41) and a second semiconductor layer (42) which are arranged at intervals on the buffer layer (30); the first semiconductor layer (41) is positioned above the light shielding layer (20);
step S3, forming a first insulating layer (51) covering the buffer layer (30), the first semiconductor layer (41) and the second semiconductor layer (42), depositing a first metal layer on the first insulating layer (51), and patterning the first metal layer to form a gate electrode (60) over the first semiconductor layer (41);
step S4, etching the first insulating layer (51) by taking the grid (60) as a shield to obtain a grid insulating layer (52) positioned below the grid (60);
step S5, using the grid electrode (60) and the grid electrode insulating layer (52) as shielding, carrying out plasma treatment on the first semiconductor layer (41) and the second semiconductor layer (42) to obtain an active layer (43) and a transparent conductor layer (44) arranged at an interval with the active layer (43); the active layer (43) comprises a channel region (431) positioned below the gate insulating layer (52) and a source contact region (432) and a drain contact region (433) positioned at two sides of the channel region (431);
step S6, forming an interlayer insulating layer (70) covering the buffer layer (30), the active layer (43), the transparent conductor layer (44) and the gate (60), opening the interlayer insulating layer (70), forming a first via hole (71) and a second via hole (72) exposing the source contact region (432) and the drain contact region (433), respectively, depositing a second metal layer on the interlayer insulating layer (70), and patterning the second metal layer to form a source electrode (81) and a drain electrode (82); the source (81) is in contact with a source contact region (432) through a first via (71), and the drain (82) is in contact with a drain contact region (433) through a second via (72);
step S7, forming a passivation layer (90) covering the interlayer insulating layer (70), the source electrode (81) and the drain electrode (82), forming a flat layer (100) on the passivation layer (90), opening the passivation layer (90) and the flat layer (100), forming a third via hole (101) exposing the drain electrode (82) and a first opening (102) exposing the interlayer insulating layer (70) above the transparent conductor layer (44); forming a pixel electrode (110) on the planarization layer (100); the pixel electrode (110) is in contact with the drain electrode (82) through the third via hole (101) and is in contact with the interlayer insulating layer (70) through the first opening (102);
the transparent conductor layer (44) and the pixel electrode (110) form a transparent capacitor structure, and the interlayer insulating layer (70) is used as a dielectric layer of the transparent capacitor structure;
step S8, forming a pixel defining layer (120) on the planarization layer (100) and the pixel electrode (110), and opening the pixel defining layer (120) to form a second opening (121) exposing the pixel electrode (110) above the transparent conductor layer (44), wherein the second opening (121) defines an OLED light emitting area above the transparent capacitor structure.
7. The method for manufacturing the OLED backplane according to claim 6, wherein the light shielding layer (20) has a thickness of
The light shielding layer (20) is made ofAn alloy consisting of one or more of molybdenum, aluminum, copper, and titanium; the thickness of the buffer layer (30) is
The buffer layer (30) is one or the combination of two of a silicon oxide layer and a silicon nitride layer; the thickness of the active layer (43) and the transparent conductor layer (44) are both
The active layer (43) and the transparent conductor layer (44) are made of one of indium gallium zinc oxide, indium zinc tin oxide and indium gallium zinc tin oxide; the thickness of the gate insulating layer (52) is
The gate insulating layer (52) is one or a combination of two of a silicon oxide layer and a silicon nitride layer; the grid (60) is made of an alloy consisting of one or more of molybdenum, aluminum, copper and titanium; the thickness of the grid electrode (60) is
The thickness of the interlayer insulating layer (70) is
The interlayer insulating layer (70) is one or the combination of two of a silicon oxide layer and a silicon nitride layer; the source electrode (81) and the drain electrode (82) are made of an alloy consisting of one or more of molybdenum, aluminum, copper and titanium; the thickness of the source electrode (81) and the thickness of the drain electrode (82) are both
The thickness of the passivation layer (90) is
The passivation layer (90) is one or the combination of two of a silicon oxide layer and a silicon nitride layer.
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