JPS58197882A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS58197882A JPS58197882A JP8094182A JP8094182A JPS58197882A JP S58197882 A JPS58197882 A JP S58197882A JP 8094182 A JP8094182 A JP 8094182A JP 8094182 A JP8094182 A JP 8094182A JP S58197882 A JPS58197882 A JP S58197882A
- Authority
- JP
- Japan
- Prior art keywords
- polysilicon
- oxide film
- platinum
- film
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000004065 semiconductor Substances 0.000 title abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 17
- 229910052710 silicon Inorganic materials 0.000 claims description 17
- 239000010703 silicon Substances 0.000 claims description 17
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 229910021332 silicide Inorganic materials 0.000 claims description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 5
- 238000002955 isolation Methods 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 18
- 229920005591 polysilicon Polymers 0.000 abstract description 18
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 abstract description 9
- 150000004767 nitrides Chemical class 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract description 5
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 abstract description 4
- 230000005669 field effect Effects 0.000 abstract description 4
- 238000009413 insulation Methods 0.000 abstract description 4
- 229910052697 platinum Inorganic materials 0.000 abstract description 4
- 229910021339 platinum silicide Inorganic materials 0.000 abstract description 4
- QZPSXPBJTPJTSZ-UHFFFAOYSA-N aqua regia Chemical compound Cl.O[N+]([O-])=O QZPSXPBJTPJTSZ-UHFFFAOYSA-N 0.000 abstract 1
- 230000010354 integration Effects 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 210000004907 gland Anatomy 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に係り、＃に絶縁ゲート
型電界効果半導体装置の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing an insulated gate field effect semiconductor device.
現在使用されている絶縁ゲート型電界効果半導体装置の
一例として、シリコンゲートＭＯ８ＩＣのトランジスタ
ーの断面図を第１図に示す、ポリシリ３を覆う酸化膜４
′に配線領域５を接触させない様に設計マージンを持た
せている。このことが集積度の向上ＫＭＲって一つの大
きな障害になっている。又別の使用例を第２図に示す。As an example of currently used insulated gate field effect semiconductor devices, a cross-sectional view of a silicon gate MO8IC transistor is shown in FIG.
A design margin is provided so that the wiring area 5 does not come into contact with the wiring area 5. This is a major obstacle to increasing the degree of integration of KMR. Another usage example is shown in FIG.
この第２図の場合は第１図の場合と比して集積度は良い
が５の金属配線領域と２のポリシリコンの間に新たな寄
生容量が生じる。ｔたこの場合にはポリシリ上で金属配
線５を分断する為２のポリシリコンの巾は金属配＠５の
間隔よシ大きくしなければならない、このことが特性及
び集積度の向上にとって障害となっている。伺、第１図
、第２図で、ｌはＰ型半導体基体、２はゲート酸化膜、
４はフィールド酸化膜、６はＰ＋型絶縁分離領域である
。In the case of FIG. 2, the degree of integration is better than in the case of FIG. 1, but a new parasitic capacitance occurs between the metal wiring region 5 and the polysilicon 2. In this case, the width of the polysilicon layer 2 must be larger than the spacing between the metal interconnections 5 in order to separate the metal interconnections 5 on the polysilicon layer, which poses an obstacle to improving the characteristics and degree of integration. ing. In Figures 1 and 2, l is a P-type semiconductor substrate, 2 is a gate oxide film,
4 is a field oxide film, and 6 is a P+ type insulation isolation region.
本発明の目的はゲート電極とソースあるいはドレインの
オーミ、り部の間隔を最小限にして高集積度高性能の絶
縁ゲー）Ｉｔ電界効果牛導体装製電製造方法を提供する
ことにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a highly integrated, high performance insulated gate (IT) field effect conductor device manufacturing method that minimizes the distance between the gate electrode and the ohm or groove of the source or drain.
前記目的を達成する為の本発明の基本的構成Ｖｉ。Basic configuration Vi of the present invention for achieving the above object.
第１導電型のシリコン基体表面に第１のゲート誘電体と
絶縁分離の為の比較的厚い第２の誘電体とを形成する工
程と、前記第１の誘電体上に前記第２の誘電体上に延在
する様に第１のシリコン領域を形成する工程と、このシ
リコン領域の前記第１の誘電体にほぼ垂直な面を選択的
に酸化する工程と、ソース、ドレイン上より前記第２の
誘電体上に延在し前記第１のシリコン領域より前記選択
酸化膜によって隔てられる様に第２のシリコン領域を形
成する工程と、前記第２のシリコン領域の全部と前記第
１のシリコン領域の一部あるいは全部を金属シリサイド
にする工程を含む半導体製電の製造方法にある。forming a first gate dielectric and a relatively thick second dielectric for insulation separation on the surface of a silicon substrate of a first conductivity type; and forming the second dielectric on the first dielectric. forming a first silicon region extending upward; selectively oxidizing a surface of the silicon region substantially perpendicular to the first dielectric; and oxidizing the second silicon region from above the source and drain. forming a second silicon region extending over the dielectric material and separated from the first silicon region by the selective oxide film; and all of the second silicon region and the first silicon region. A method of manufacturing semiconductor electrical equipment includes a step of converting part or all of the semiconductor into metal silicide.
以下１本発明の実施例を図面を用いて説明する。An embodiment of the present invention will be described below with reference to the drawings.
第３図（ａｔ〜第３第３雌〜発明に依る一実施例の手順
を示す。第３図（ａ）に示す様にチッ′化膜を利用した
選択酸化を用いてＰ型半導体基体１の表面部に比較的厚
い酸化ｌＩ４とその下のＰ型絶縁介離領域６を選択的に
形成する。次に第３図（ｂｌに示す様にゲート酸化膜２
．ｎ型のポリシリ７を形成しこの上にチッ化膜８を選択
的に形成する。次にチッ化膜８をマスクに第３図（Ｃ１
に示す様にポリシリコンを選択的にエツチング除去する
。次に第３図（ｄｉに示す様にポリシリコン７をマスク
にゲート酸化膜２を選択的に除去し、このゲート酸化膜
の除去され丸窓よりｎ型のソース及びドレインの拡散領
域９を形成する。次に第３図ｆｅ）に示す様に第２のポ
リシリコン１０を形成し続いてチッ化膜１１を気相成長
に依って形成する。この時チッ化＠８の出張りの為に気
相成長のいわゆるステップカバーレジの悪さの為にポリ
シリコン７の側面にはポリシリコンとチ、化膜は形成さ
れない。次に第３図（ｆ）Ｋオす様Ｋｆ、イ、膜１、ヶ
、□、択、化Ｌし ’ポリシリコンの側面
に１２の酸化膜を形成する。FIG. 3(a) shows the procedure of an embodiment according to the invention.As shown in FIG. 3(a), a P-type semiconductor substrate is A relatively thick oxide film 2 and a P-type insulating intervening region 6 thereunder are selectively formed on the surface of the gate oxide film 2. Next, as shown in FIG.
．． An n-type polysilicon layer 7 is formed, and a nitride film 8 is selectively formed thereon. Next, using the nitride film 8 as a mask, see FIG.
The polysilicon is selectively etched away as shown in FIG. Next, as shown in FIG. 3 (di), the gate oxide film 2 is selectively removed using the polysilicon 7 as a mask, and n-type source and drain diffusion regions 9 are formed through the round window where the gate oxide film is removed. Next, as shown in FIG. 3(fe), a second polysilicon layer 10 is formed, and then a nitride film 11 is formed by vapor phase growth. At this time, due to the protrusion of the nitride film, no polysilicon film is formed on the side surface of the polysilicon film 7 due to the poor so-called step coverage of vapor phase growth. Next, as shown in FIG. 3(f), 12 oxide films are formed on the side surfaces of the polysilicon.
次にチッ化腺８及び１１をエツチング除去すれば第３図
（ｇ）の様になる。次に第３図（ｈ）に示す様に白金属
１３を全面に形成する０次に第３図（ｉｌＫ示す様に白
金のシンターを行ってポリシリコン１０の全部とポリシ
リコン７の一部を白金シリサイド１４に変える１次に第
３図（ｊｌＫ示す様に王水工、チで白金シリサイドに変
化しない白金のみを選択的に除去する０次に第３図（ｋ
ｌ Ｋ示す様に酸化Ｊ［１１１５を形成しこの酸化膜１
５を選択的に開孔子る。次に第３図（υに示す様に１５
の開孔部よりコンタクトを取って二層目のＴｉ−Ｗ層６
とＡ１１７の配線を形成して完成する。Next, if the nitride glands 8 and 11 are removed by etching, the result will be as shown in FIG. 3(g). Next, as shown in FIG. 3(h), platinum metal 13 is formed on the entire surface. Next, as shown in FIG. The first stage is changed to platinum silicide 14, as shown in Figure 3 (jlK).
l As shown in K, oxide J[1115 is formed and this oxide film 1
5. Selectively open Confucius. Next, as shown in Figure 3 (υ), 15
Contact is made through the opening of the second Ti-W layer 6.
and A117 wiring is formed and completed.
以下１本発明に依る効果を示す。前記実施例からもわか
る様に本発明に依ればソース、ドレインのコンタクト部
とゲート電極物質の間隔を１μ以下にする事も困難なこ
とではない。またゲートポリシリコン上に金属シリサイ
ドを形成する事に依ってポリシリコンの抵抗を下げる事
が出来る。また本発明は必然的にソース、ト°レインか
らの引き出し配線を金属シリサイドとする事になるが、
この金属シリサイドは比較的薄く形成する事が可能な為
に２層目の配線にとって極めて有利なものとなる。The effects of the present invention will be described below. As can be seen from the above embodiments, according to the present invention, it is not difficult to reduce the distance between the source and drain contact portions and the gate electrode material to 1 μm or less. Furthermore, by forming metal silicide on the gate polysilicon, the resistance of the polysilicon can be lowered. Also, in the present invention, the wiring drawn out from the source and train is necessarily made of metal silicide, but
Since this metal silicide can be formed relatively thin, it is extremely advantageous for the second layer wiring.
第１図と第２図はシリコンゲーＦＭＯ８型トランジスタ
の断面図を示す、第３図（ａ）〜第３図（Ｌ）は本発明
に依る実施手順を示す断面図である。
同図において、ｌ・・・・・・Ｐ型半導体基体、２・・
・・・・ゲート酸化膜、３・・・・・・ポリシリコン、
４・・・・・・フィールド、酸化膜、４′・・・・・酸
化膜、５・・・・・・配線領域。
６・・・・・・Ｐ＋型絶縁分離領域、７・・・・・・金
属配線領域（たとえばアルミ＋シリコン）、８・・・・
・・チッ化膜。
９ ・・・・ｎ型ソース及びドレイン領域、１０・・・
・・・薄いポリシリコン、１１・・・・・・チッ化に、
１２・・・・・・側面酸化膜、１３・・・・・・白金、
１４・・・・・・白金シリサイド、１５・・・・・・酸
化膜−，１６・・・・・Ｔｉ−Ｗ層、１７・・・・・・
アルミニウムである。
第 ２ 図
Ｌ３図（ｄ）′
Ｊ！＃３閏（９）′
＃−３目（７ｔ） ’
平’、 ３１２１０）1 and 2 are cross-sectional views of a silicon game FMO8 type transistor, and FIGS. 3(a) to 3(L) are cross-sectional views showing an implementation procedure according to the present invention. In the figure, l...P-type semiconductor substrate, 2...
...Gate oxide film, 3...Polysilicon,
4...field, oxide film, 4'...oxide film, 5...wiring area. 6... P+ type insulation isolation region, 7... Metal wiring region (for example, aluminum + silicon), 8...
...Tinitride film. 9...n-type source and drain region, 10...
... Thin polysilicon, 11... Chnitride,
12... Side oxide film, 13... Platinum,
14...Platinum silicide, 15...Oxide film, 16...Ti-W layer, 17...
It is aluminum. Figure 2 Figure L3 (d)' J! #3 leap (9)'#-3 (7t) 'flat', 31210)
Claims (1)
絶縁分離の為の比較的厚いＷＩＪ２の誘電体を形成する
工程と、＃第１の誘電体上に該第２の誘電体上に延在す
る様に第１のシリコン領域を形成する工程と、該第１の
シリコン領域の第１の誘電体にほぼ垂直な面に選択的に
＠面識化膜を形成する工程と、ソース、ドレイン上よシ
該１ｉ４２の誘電体上に延在し該第１のシリコン領域よ
り該適訳酸化膜によって隔てられる様に！２のシリコン
領域を形成する工程と、＃第２のシリコン領域の全部と
該第１の７．９３７層の一部あるいは全部を金属シリサ
イドに変換する工程とを有することを特徴とする半導体
装置の製造方法。Forming a relatively thick WIJ2 dielectric on the surface of the first conductivity type silicon substrate for isolation from the first gate dielectric; a step of forming a first silicon region so as to extend; a step of selectively forming an @-plane identification film on a plane substantially perpendicular to the first dielectric of the first silicon region; Extending from above over the dielectric of the 1i42 and separated from the first silicon region by the oxide film! a step of forming a second silicon region; and a step of converting all of the second silicon region and part or all of the first 7.937 layer into metal silicide. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8094182A JPS58197882A (en) | 1982-05-14 | 1982-05-14 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8094182A JPS58197882A (en) | 1982-05-14 | 1982-05-14 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58197882A true JPS58197882A (en) | 1983-11-17 |
Family
ID=13732501
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8094182A Pending JPS58197882A (en) | 1982-05-14 | 1982-05-14 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58197882A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63114172A (en) * | 1986-10-24 | 1988-05-19 | Yokogawa Hewlett Packard Ltd | Integrated circuit |
| JPS63287052A (en) * | 1987-05-19 | 1988-11-24 | Nec Corp | Semiconductor integrated circuit device |
| EP0777268A3 (en) * | 1995-11-30 | 1997-11-05 | Lucent Technologies Inc. | Integrated circuit fabrication |
-
1982
- 1982-05-14 JP JP8094182A patent/JPS58197882A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63114172A (en) * | 1986-10-24 | 1988-05-19 | Yokogawa Hewlett Packard Ltd | Integrated circuit |
| JPS63287052A (en) * | 1987-05-19 | 1988-11-24 | Nec Corp | Semiconductor integrated circuit device |
| EP0777268A3 (en) * | 1995-11-30 | 1997-11-05 | Lucent Technologies Inc. | Integrated circuit fabrication |
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