JPS5838939B2 - integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an MO8 integrated circuit suitable as a large capacity IC memory.

MO8 integrated circuits are suitable for high-density, large-scale applications, and can realize large-capacity IC memories.

In particular, a one-transistor type IC memory uses a transistor and a capacitive element to provide a memory function, and therefore occupies a small area, and is attracting attention as a high-density memory integrated circuit.

Conventionally, a capacitive element and a transistor are formed separately in an active region, and four elements, the gate electrode of the transistor, two opposite conductivity type regions, and the electrode of the capacitive element, are provided on the active region, but with higher density It is desirable to reduce these elements in order to

Furthermore, it has become a necessary technology to reduce the size of the gate electrode of a transistor so that the gate electrode and the wiring electrode can be reliably coupled to each other in a minute area.

It is an object of the invention to provide a higher density MO8 integrated circuit.

The MO8 integrated circuit of the present invention is an integrated circuit in which the active region is protected with a silicon nitride film by using the selective oxidation property of the silicon nitride film with respect to the surface of a -conductivity type semiconductor, and a thick oxide film is grown on the peripheral semiconductor surface. One end of the gate electrode is inserted between the silicon nitride film for selective oxidation covering one end of the active region and the semiconductor surface, and the electrode on the silicon nitride film forms a capacitive element between the base and the capacitor. The conductive channel coupling between the substrate surface immediately below the element and the opposite conductivity type region provided on the substrate surface at the other end of the active region is performed by the gate electrode.

Such a semiconductor device is, for example, an integrated circuit in which the active region is protected by a silicon nitride film and a thick oxide film is grown on the surrounding semiconductor surface by using the selective oxidation property of the silicon nitride film with respect to the conductive semiconductor surface. , providing a gate electrode across the active region in advance, selectively covering the silicon nitride film and performing selective oxidation, and forming a capacitive element electrode on one end of the silicon nitride film used for the selective oxidation; It can be manufactured by a manufacturing method characterized in that a region of opposite conductivity type is formed at the other end of the active region.

The integrated circuit of the present invention realizes a higher density integrated circuit by removing the opposite conductivity type region on the capacitive element side that causes transistor operation and realizing a memory function with three elements, and the gate electrode is made of silicon. This brings about a miniaturization technology that allows conductive bonding to occur when the nitride film is exposed in the removed portion.

Next, in order to better understand the characteristics of the present invention, embodiments of the present invention will be described using figures.

1 to 5 are cross-sectional views showing the main manufacturing steps of an embodiment of the present invention.

In the MO8 integrated circuit of this embodiment, a gate insulating film 2 of silicon oxide with a thickness of 300 μm is grown by thermal oxidation on one surface of a P-type silicon single crystal substrate 1 with a resistivity of 1Ω, and then phosphorus is added on the upper surface. Added polycrystalline silicon gate electrodes 3, 4 are selectively formed (FIG. 1).

The gate electrodes 3 and 4 are silicon oxide films 5 of about 100λ,
6, silicon nitride films 7 and 8 forming an active region.
The substrate is thermally oxidized to form a 10
A silicon oxide film 9 with a thickness of approximately μm is formed.

In forming the thick silicon oxide film 9 using the silicon nitride films 7 and 8 as masks for selective oxidation, impurities for preventing parasitic effects are introduced into the surface of the inactive region in advance using the silicon nitride films 7 and 8 as masks. Forming concentration P required region 10 (
Figure 2).

Next, a capacitive element electrode 11 of phosphorous-doped polycrystalline silicon is formed on the upper surface of the silicon nitride film 7.8 that has defined the active region, and a silicon oxide film 12 with a thickness of about 5000λ on the electrode is thermally oxidized. Form.

This silicon oxide film 12 is used as an etching mask for the silicon nitride films 7 and 8, and protects the capacitive element electrode 11 and the silicon nitride films 7 and 8 at one end of each active region, and protects the gate electrode 3 at the other end. , 4 and the substrate surface (FIG. 3).

On the surface of the substrate from which the silicon nitride film has been removed, phosphorus is applied to a junction depth of 1 μm and a surface concentration of 103 using polycrystalline silicon as a mask.
Ions are implanted to approximately 9 ca, and N-type regions 13 and 14 are formed at the other end of the active region, and aluminum wiring electrodes 15 are conductively coupled to the exposed surfaces of the gate electrodes 3 and 4.
It is completed as shown in the figure.

In this completed MO8 integrated circuit, a memory cell with a minimum element occupation area is formed in each active region, consisting of a gate electrode, a capacitive element electrode, and an N-type region.

FIG. 5 is a partial top view showing a 4-bit matrix portion of the completed MO8 integrated circuit of FIG.

As shown in this figure, the gate electrode 3 that connects the N-type region 13 of the memory cell and the capacitive element through a conductive channel and the capacitive element electrode 11 overlap, so that the transistor action is improved compared to the conventional one-transistor type memory cell. The area is reduced by removing the N-type region.

Further, the conductive coupling between the gate electrodes 3 and 4 and the wiring electrode 15 is obtained on the etched surface of the silicon nitride film, and since the silicon nitride film has etching selectivity with respect to the silicon oxide film, the conductive coupling between the gate electrodes 3 and 4 and the wiring electrode 15 is achieved by the etching surface of the silicon nitride film. Highly reliable conductive coupling can be obtained on minute exposed surfaces.

Although one embodiment of the present invention has been described above, the present invention is not limited to memory integrated circuits as described above, but can also be applied to logic MOSFETs.
It can also be applied to 8 integrated circuits.

Further, the conductivity type, electrode material, insulator, etc. used may be changed as necessary.

[Brief explanation of drawings]

1 to 4 are sectional views showing the main manufacturing steps of an embodiment of the present invention, and FIG. 5 is a top view of the embodiment of the present invention. 1... P-type silicon single crystal substrate, 2...
・Gate insulating film, 3, 4...Gate electrode, 5,
6...Silicon oxide film, 7,8...Silicon nitride film, 9...Silicon oxide film, 10.
...High concentration P important region, 11...Capacitive element electrode, 12...Silicon oxide film, 13.14.
...N-type region, 15... Wiring electrode.

Claims (1)

[Claims] 1- In an integrated circuit in which a silicon nitride film is grown in an active region on the surface of a conductive type semiconductor, one end of a gate electrode is inserted between the silicon nitride film covering one end of the active region and the semiconductor surface, and the silicon nitride 1. An integrated circuit characterized in that the gate electrode is used to conduct conductive channel coupling between the substrate surface immediately below the electrode on the film and an opposite conductivity type region provided on the substrate surface at the other end of the active region.