JP3340177B2 - Field-effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device,
In particular, it relates to a field-effect transistor formed on an SOI substrate.

[0002]

2. Description of the Related Art In recent years, an integrated circuit (IC) formed by integrating a large number of transistors, resistors and the like so as to achieve an electric circuit and integrating them on one chip has been frequently used in important parts of computers and communication equipment. ing. The performance of the LSI alone can be improved, for example, by increasing the degree of integration and increasing the speed.

FIG. 57 is a sectional view of an element showing a structure of a conventional MOSFET known as a structure advantageous for high-speed operation.

In the figure, reference numeral 801 denotes a silicon support base, on which a single-crystal silicon layer 800 is provided via a silicon oxide film 802. Membrane 8
02 forms an SOI substrate.

A p-type diffusion layer 8 is formed on the surface of the silicon layer 800.
03 is selectively formed, and an n ⁺ -type diffusion layer 804 having a high impurity concentration is selectively formed on the surface of the p-type diffusion layer 803. An n-type drain diffusion layer 805 is formed from a part of the surface of the n ⁺ -type diffusion layer 804 to the surface of the p-type diffusion layer 803, and the n-type drain diffusion layer 805 is formed on the surface of the p-type diffusion layer 803. Separately, an n ⁺ type source diffusion layer 806 is selectively formed.

A gate electrode 808 is provided on the p-type diffusion layer 803 between the n-type drain diffusion layer 805 and the n ⁺ -type source diffusion layer 806 with a gate insulating film 810 interposed therebetween. On the diffusion layer 803, the n ⁺ type diffusion layer 80
4, a drain electrode 809 that contacts the n-type drain diffusion layer 805 and a source electrode 807 that contacts the n ⁺ -type source diffusion layer 806 are provided.

[0007] The MOSFET thus configured has a smaller parasitic capacitance than a normal MOSFET, and thus can operate at high speed.

By the way, the maximum operating frequency of this type of MOSFET is limited by the capacity in the element, especially the output capacity. To reduce the output capacitance, the silicon layer 800
Should be made thinner. This is because the pn junction capacitance accounts for a large proportion of the output capacitance.

However, as the silicon layer 800 becomes thinner, the distance between the n ⁺ -type source diffusion layer 806 and the silicon oxide film 802 becomes smaller, so that the gate electrode 80 becomes thinner.
8, the resistance between the channel region below and the source electrode 807 increases.

When the silicon layer 800 is further thinned, the n ⁺ -type source diffusion layer 806 and the silicon oxide film 802 eventually come into contact with each other, and the electrical connection between the channel region and the source electrode 807 is established. As a result, the potential of the channel region floats, so that normal device operation becomes impossible.

[0011]

As described above, the conventional S
In the case of a MOSFET formed on an OI substrate, if the silicon layer of the SOI substrate is made thinner in order to increase the maximum operating frequency, the resistance between the channel region and the source electrode increases. There is a problem that normal element operation becomes impossible due to floating of the potential of the region.

The present invention has been made in view of the above circumstances, and an object of the present invention is to prevent a device operation defect caused by an abnormal potential in a channel region even when a silicon layer of an SOI substrate is made thinner. To provide a field effect transistor formed on an SOI substrate.

[0013]

To achieve the above object, a field effect transistor according to the present invention comprises a semiconductor layer for forming an element formed on an insulating film and a semiconductor layer formed on the surface of the semiconductor layer for forming an element. A first first conductivity type semiconductor layer selectively formed, a first second conductivity type semiconductor layer selectively formed on the surface of the first first conductivity type semiconductor layer; A first main electrode provided on the second conductive type semiconductor layer, a second second conductive type semiconductor layer selectively formed on the surface of the first first conductive type semiconductor layer, A second main electrode provided on the second second conductivity type semiconductor layer, and the first first electrode between the second second conductivity type semiconductor layer and the first second conductivity type semiconductor layer. A control electrode provided on the conductive semiconductor layer via an insulating film; and a control electrode selectively formed on the surface of the element forming semiconductor layer. And it is characterized in that a second main electrode and the second first-conductivity-type semiconductor layer in contact with the first first-conductivity type semiconductor layer.

[0014]

According to the field effect transistor of the present invention, the SOI
A first first conductivity type semiconductor layer (hereinafter, referred to as a lower portion) below a second main electrode and a control electrode via a second first conductivity type semiconductor layer which is not provided in a conventional field effect transistor formed on a substrate. ,
Channel region).

[0015] Therefore, the thickness of the element-forming semiconductor layer is reduced until the element-forming semiconductor layer and the insulating substrate come into contact with each other.
Even if the channel region is electrically separated from the second second conductivity type semiconductor layer, since the channel region is connected to the second main electrode via the second first conductivity type semiconductor layer, The potential of the channel region does not float.

Therefore, according to the field-effect transistor of the present invention, even if the thickness of the semiconductor layer for element formation is strongly reduced, no element operation failure due to the abnormal potential of the channel region occurs.

[0017]

Embodiments will be described below with reference to the drawings.

FIG. 1 is a diagram showing the structure of a high-frequency MOSFET according to one embodiment of the present invention. FIG. 1 (a) is a plan view, and FIG. 1 (b) is a view of the MOSFET of FIG. 1 (a). BB
FIG.

In FIG. 1, reference numeral 1 denotes a silicon support substrate, and a silicon oxide film 2
(Insulating substrate) is formed. This silicon oxide film 2
A silicon layer 17 is formed thereon. A p-type diffusion layer 5 (first first conductivity type semiconductor layer) reaching the silicon oxide film 2 is selectively formed on the silicon layer 17.
An n-type drain diffusion layer 6 (first second conductivity type semiconductor layer) reaching the silicon oxide film 2 is selectively formed in the n-type diffusion layer 5, and the n-type drain diffusion layer 6 has a high impurity concentration of n ⁺
Drain electrode 11 (first main electrode) via the mold diffusion layer 7
Connected to

Apart from the n-type drain diffusion layer 6 and the n ⁺ -type diffusion layer 7, the p-type diffusion layer 5 has an n-type source diffusion layer 4 (a second second conductivity type semiconductor layer) reaching the silicon oxide film 2. ) Are selectively formed. The n-type source diffusion layer 4 is connected to the source electrode 9 (second main electrode) via the n ⁺ -type diffusion layer 3 having a high impurity concentration.

A gate electrode 10 (control electrode) is provided on the p-type diffusion layer 5 in a region between the n-type drain diffusion layer 6 and the n-type source diffusion layer 4 via a gate insulating film 8. . The channel region c under the gate electrode 10
The p-type diffusion layer 5 serving as h is connected to the source electrode 9 via the p ⁺ -type short-circuit diffusion layer 12 (second first conductivity type semiconductor layer) in contact with the n ⁺ -type diffusion layer 3 and the n-type source diffusion layer 4. Connected to

In the MOSFET configured as described above,
Until the semiconductor layers such as the n-type source diffusion layer 4, the p-type diffusion layer 5, and the n-type drain diffusion layer 6 contact the silicon oxide film 2, the silicon layer 17 is being thinned. Becomes smaller. Therefore, the output capacitance becomes smaller, the maximum operating frequency becomes higher than that of the conventional MOSFET, and higher speed operation becomes possible.

Moreover, the p-type diffusion layer 5 in the channel region ch
Is connected to the source electrode 9 via the p ⁺ -type short-circuit diffusion layer 12, the channel region ch is maintained at a predetermined potential, and the silicon layer 17 is thinned so that the p-type diffusion layer 5 and the n-type source Even if the diffusion layer 4 is electrically separated, no abnormal potential is generated in the channel region ch.

Therefore, according to the present embodiment, it is possible to obtain a MOSFET having a high operating frequency which does not cause a malfunction due to an abnormal potential of the channel region ch.

FIG. 2 is a characteristic diagram showing the relationship between the silicon layer of the SOI substrate and the output capacitance. It can be seen from FIG. 2 that when the film thickness of the silicon layer exceeds 0.3 μm, the output capacity increases rapidly. Therefore, a high-speed MOSFET can be obtained by setting the thickness of the silicon layer to 0.3 μm or less.

FIG. 3 is a characteristic diagram showing the relationship between the output capacitance and the value obtained by dividing the distance (W) between the source electrode and the gate electrode by the thickness (t _ox ) of the silicon oxide film 2. From FIG. 3, W / t _ox ≧ 0.05 μm, for example, _tox is 3 μm
It can be seen that the output capacity sharply increases when the length is shorter than 0.2 μm in the case of about or more. Therefore, W
/ T _ox is preferably at least 0.2 μm.

FIG. 4 is a characteristic diagram showing the relationship between W / _tox and output capacity. From FIG. 4, W / t _ox ≧ 0.5 μm,
For example, when _tox is about 3 μm or more, 1.5 μm
It can be seen that when the length is shorter than the above, the output capacity sharply increases. Therefore, W / _tox is preferably set to 1.5 μm or more.

FIG. 5 is a characteristic diagram showing the relationship between the silicon oxide film of the SOI substrate and the output capacitance. It can be seen from FIG. 5 that when the thickness of the silicon oxide film is less than 2 μm, the output capacity sharply increases. Therefore, by setting the thickness of the silicon oxide film to 2 μm or more, a high-speed MOSF
ET is obtained.

Hereinafter, a MOSF according to another embodiment of the present invention will be described.
ET will be described. In the following drawings, portions corresponding to the MOSFETs in the above-mentioned drawings are denoted by the same reference numerals as those in the above-mentioned drawings, and detailed description thereof will be omitted.

FIG. 6 shows a MOS according to another embodiment of the present invention.
It is a top view of FET.

This is a modification of a part of the MOSFET shown in FIG. 1. The dimensions of the n ⁺ type diffusion layer 3 and the n type source diffusion layer 4 in the channel width direction are smaller than those of the p ⁺ type short diffusion layer 12. It is getting bigger.

According to the MOSFET configured as described above, the effective channel length is longer than that of the previous embodiment, so that a larger current can flow.

FIG. 7 shows a MOS transistor according to another embodiment of the present invention.
It is a top view of FET.

This is a modification of a part of the MOSFET shown in FIG. 1, in which the dimension of the p ⁺ -type short-circuit diffusion layer 12 in the channel length direction is reduced, and the region of the p-type diffusion layer 5 is correspondingly widened. It is.

[0035] In the thus constructed MOSFET, since p ⁺ -type short diffusion layer 12 can not extend to the channel region ch, p ⁺ -type p-type impurity in the short diffusion layer 12 in channel region ch Variation in threshold voltage due to diffusion can be prevented.

FIG. 8 shows a MOS according to another embodiment of the present invention.
It is sectional drawing of FET.

This is an example in which the potential of the silicon support base 1 and the potential of the drain electrode 11 are the same. If the potential of the drain electrode 11 is selected in this manner, the parasitic capacitance does not increase even if the n-type drain diffusion layer 6 and the n ⁺ -type diffusion layer 7 are formed large in order to increase the breakdown voltage. In the figure, 1
Reference numeral 3 denotes an insulating film.

FIG. 9 shows a MOS according to another embodiment of the present invention.
It is sectional drawing of FET.

This is a modification of a part of the MOSFET shown in FIG.
This is an example covered with 4.

According to the MOSFET configured as described above, the portion between the sidewall gate insulating film 14 and the drain electrode 11
By filling the space between the sidewall gate insulating film 14 and the source electrode 7 with a gas such as vacuum or air, and lowering the dielectric constant of the filled portion, the parasitic capacitance can be reduced.

FIG. 10 shows an MO according to another embodiment of the present invention.
It is sectional drawing of SFET.

This is a modification of the MOSFET of FIG. 1 and is an example in which the p-type diffusion layer 5 in the gate electrode portion (channel portion) is reduced. Such a gate electrode portion is
For example, it can be formed by the following method.

First, as shown in FIG. 12A, a thick oxide film 15 is formed on the n-type drain diffusion layer 6.

Next, as shown in FIG.
Using mask 5 as a mask, p-type impurity ions 16 are implanted into n-type drain diffusion layer 6 by oblique ion implantation. At this time, since the p-type impurity ions 16 are not implanted into the n-type drain diffusion layer 6 near the oxide film 15, the p-type diffusion layer 5 as shown in FIG. .

Next, as shown in FIG.
5, a first gate electrode 10a made of a polysilicon film
Is formed, a second gate electrode 10 made of a polysilicon film is formed on the side wall of the gate electrode 10a on the p-type diffusion layer 5 side.
b is formed.

Next, as shown in FIG. 12D, p-type impurity ions 16 are implanted into the p-type diffusion layer 5 by ordinary ion implantation using the gate electrodes 10a and 10b as masks.
After expanding the region of the p-type diffusion layer 5, the n-type impurity ions 17
Is implanted into the p-type diffusion layer 5 to form the n-type source diffusion layer 4.

Next, as shown in FIG. 12E, a sidewall gate insulating film 14 is formed to complete a gate electrode portion.

Also, instead of forming the p-type diffusion layer 5 by the method shown in FIGS. 12A and 12B, for example, FIG.
As shown in (a), a p-type impurity 16b is implanted into the n-type drain diffusion layer 6 by ordinary ion implantation, and the oxide film 15 is formed.
After forming the p-type diffusion layer 5 extending to the lower part in FIG.
As shown in (b), the oxide film 15 is etched by side etching.
May be used.

FIG. 11 shows an MO according to another embodiment of the present invention.
It is sectional drawing of SFET.

This is a modification of the MOSFET shown in FIG. 10, and is an example in which the drain side p-type diffusion layer 5 is reduced.

FIG. 14 shows an MO according to another embodiment of the present invention.
FIG. 2 is a diagram showing a structure of an SFET, wherein FIG.
FIG. 2B is a cross-sectional view of the MOSFET of FIG.

In the MOSFET of this embodiment, a trench 19 is formed under the source electrode 9 so as to reach the silicon support base 1.
Is formed, and the trench 19 is filled with a conductive material having a high thermal conductivity such as Al. In the figure, reference numeral 20 denotes a gate electrode contact hole.

According to the MOSFET configured as described above, the ground wiring on the surface portion of the silicon layer 17 for making the potential of the source electrode 9 the same as that of the silicon support base 1 is unnecessary, and the surface of the silicon layer 17 is not required. It is possible to reduce the parasitic capacitance caused by the source electrode 9 and the ground wiring in the portion.

Another advantage is that heat generated in the silicon layer 17 during operation can be released to the silicon support base 1 through a conductive material having a high thermal conductivity such as Al filled in the trench 19.

FIG. 15 shows an MO according to another embodiment of the present invention.
It is sectional drawing of SFET.

This is a modification of the MOSFET shown in FIG. 14, in which the gate electrode 10 extends above the source electrode 9. Gate electrode 10 and source electrode 9 are electrically separated by oxide film 21. Gate electrode 10
Is formed of, for example, polysilicon, and its surface is silicided.

As described above, according to the MOSFET, the gate resistance is reduced by the extent that the gate electrode 10 is extended. In this embodiment, the gate electrode 10 is extended so as to cover the entire surface of the source electrode 9. However, for example, if the gate electrode 10 extends only up to the n ⁺ type diffusion layer 3, the parasitic capacitance caused by the source electrode 9 and the gate electrode 10 is increased. Can be reduced.

FIG. 16 shows an MO according to another embodiment of the present invention.
FIG. 2 is a diagram showing a structure of an SFET, wherein FIG.
FIG. 2B is a cross-sectional view of the MOSFET of FIG.

The MOSFET of this embodiment is different from that of FIG. 14 in that a trench 22 is formed below the drain electrode 11 to reach the silicon supporting substrate 1. The trench 22 is also filled with a conductive material having a high thermal conductivity, such as Al, as in FIG.

The same effect as that of the MOSFET shown in FIG. 14 can be obtained with the MOSFET having the above-described structure, and heat is more easily generated on the drain side.

FIG. 17 shows an MO according to another embodiment of the present invention.
It is sectional drawing of SFET.

This is a modification of the MOSFET shown in FIG. 16, in which the gate electrode 10 extends above the drain electrode 11. That is, in the MOSFET of FIG. 15, the structure on the source side and the structure on the drain side are interchanged. Note that the gate electrode 10 may be shortened so as not to cover the drain electrode 11 in order to reduce the parasitic capacitance.

FIG. 18 shows an MO according to another embodiment of the present invention.
It is sectional drawing of SFET.

This is a modification of the MOSFET shown in FIG. 16, in which the source electrode 9 extends above the drain electrode 11. Source electrode 9 is electrically separated from gate electrode 10 and drain electrode 11 by oxide film 25.

According to the MOSFET configured as described above, the source resistance is reduced by the extent that the source electrode 9 extends, and furthermore, the source electrode 9 is formed of a conductive material having high thermal conductivity, so that the element portion The temperature distribution can be made uniform, and the heat in the element can be radiated from the source electrode 9.

FIG. 19 shows an MO according to another embodiment of the present invention.
It is sectional drawing of SFET.

This is a modification of a part of the MOSFET shown in FIG. 17, and is an example in which the gate electrode 10 is shortened in order to reduce the parasitic capacitance caused by the gate electrode 10 and the drain electrode 11.

FIG. 20 shows an MO according to another embodiment of the present invention.
It is sectional drawing of SFET.

This is a modification of the MOSFET shown in FIG. 18, and is an example in which the source electrode 9 is shortened in order to reduce the parasitic capacitance between the source electrode 9 and the drain electrode 11.

FIG. 21 shows an MO according to another embodiment of the present invention.
It is sectional drawing of SFET.

The MOSFET according to the present embodiment has the source electrode 9
And the gate electrode 10 extends to the drain electrode 11. An oxide film 26 is formed between the gate electrode 10 and the drain electrode 11.
, And the source electrode 9 and the drain electrode 10 are electrically separated by the oxide film 27.

According to the MOSFET configured as described above, both the gate resistance and the source resistance can be reduced at the same time.

FIG. 22 shows an MO according to another embodiment of the present invention.
It is sectional drawing of SFET.

This is a modification of a part of the MOSFET shown in FIG. 21, in which the source electrode 9 and the drain electrode 10 are shortened in order to reduce the parasitic capacitance. Also,
In order to reduce the gate resistance, the upper part of the gate electrode 10 is silicided.

FIG. 23 shows an MO according to another embodiment of the present invention.
It is sectional drawing of SFET.

This is a modification of the MOSFET of FIG. 21 and is an example in which the gate electrode 10 extends to the drain electrode 11 like the MOSFET of FIG. In the MOSFETs of FIGS. 16 to 23, the structures on the drain side and the source side may be interchanged.

FIG. 24 shows an MO according to another embodiment of the present invention.
It is sectional drawing of SFET.

[0078] This is one obtained by modifying a part of the MOSFET of FIG. 16, to form a wider trench 22, the drain electrode 11 is also an example of forming in the trench. The drain electrode 11 is formed on the side wall of the trench 22 in contact with the n + -type diffusion layer 7 in the trench 22. Since the trench 22 is not completely filled with a conductive material having a high thermal conductivity such as Al , a void 28 is formed.
You .

According to the MOSFET configured as described above, since the contact area between the silicon layer and the drain electrode 11 and the filling material increases, the heat 29 generated in the silicon layer
Can be more effectively dissipated.

FIG. 25 shows an MO according to another embodiment of the present invention.
It is sectional drawing of SFET.

This is an example in which the structures of the drain side and the source side are exchanged in the MOSFET of FIG.

With the MOSFET having the above-described structure, the same effect as that of FIG. 24 can be obtained, and the advantage that the punch-through breakdown voltage is increased because the source electrode 9 approaches the channel region.

FIG. 26 is a plan view showing a wiring structure according to another embodiment of the present invention. FIGS. 27A and 27B are cross-sectional views of the wiring structure shown in FIGS. 26A and 26B, and FIGS.
26 are sectional views taken along line DD ′ of the wiring structure in FIG.
It is E 'sectional drawing.

In the figure, reference numeral 31 denotes a silicon support substrate, and a silicon oxide film 3 is formed on the silicon support substrate 31.
2, a silicon layer 33 is sequentially provided, and the silicon oxide film 32 and the silicon layer 33 form an SOI structure.

The n ⁺ type diffusion layer 3 is formed on the surface of the silicon layer 33.
4 are selectively formed, and the n ⁺ type diffusion layer 34 is surrounded by a trench 35 reaching the silicon oxide film 32 and is separated from another semiconductor layer (not shown) formed in the silicon layer 33.

An oxide film 36 is formed on the surface of silicon layer 33, and n ⁺ -type diffusion layer 34 is provided with first wiring 37, via contact holes 40 and 41 formed in oxide film 36.
It is in contact with the third wiring 39. Further, a second wiring 38 is provided between the first wiring 37 and the third wiring 39.

With such a wiring structure, the first wiring 37 and the third wiring 3 are formed as in the conventional two-layer wiring structure.
Since there is no need to form a second wiring on the insulating film 9 via an insulating film, the number of wiring steps is reduced. With such a wiring structure, the n ⁺ type diffusion layer 34 is
5 and the silicon oxide film 32, the silicon layer 33
Because it is insulated and separated from other semiconductor layers formed in
Parasitic elements such as pn junctions can be eliminated.

FIG. 28 is a plan view showing a wiring structure according to another embodiment of the present invention. FIG. 29 is a cross-sectional view of the wiring structure of FIG. 29, in which FIG.
Are FF 'sectional views of the wiring structure of FIG.
It is G 'sectional drawing.

The difference of the wiring structure of the present embodiment from that of the previous embodiment is that n ⁺
That is, the mold diffusion layer is insulated and separated.

That is, the n ⁺ type diffusion layer 34 is surrounded by the thick silicon oxide film 42 formed by LOCOS that reaches the silicon oxide film 32 and is separated from other semiconductor layers formed on the silicon layer 33.

With such a wiring structure, the same effects as in the previous embodiment can be obtained, and since the silicon oxide film 42 can be formed more easily than the trench 35, it is advantageous in reducing the production cost. This wiring structure is particularly convenient when the silicon layer 33 is thin.

FIG. 30 is a sectional view showing a wiring structure according to another embodiment of the present invention.

This is an example in which a protection diode D is formed in the wiring region. This protection diode D has n
^And a p ⁺ -type diffusion layer 44 selectively formed on the surface of the n ⁺ -type diffusion layer 34.
The p ⁺ -type diffusion layer 44 is connected to the electrode 43 via a contact hole formed in the oxide film 36. The electrode 43 is connected to a ground or a power source serving as a reference potential.

FIG. 31 is a sectional view showing a wiring structure according to another embodiment of the present invention.

[0095] wiring structure of this embodiment is an example which aimed at reducing the contact resistance, it differs from the FIG. 27, n ⁺
A trench is formed in the mold diffusion layer 34, the inside of the trench is filled with a conductive material 45 such as Al or polysilicon, and the wiring 37 is connected to the n ⁺ -type diffusion layer 34 via the conductive material 45. Is to be.

FIG. 32 is a plan view showing a wiring structure according to another embodiment of the present invention.

The wiring structure of this embodiment is also an example in which the contact resistance is reduced, and is different from that of FIG. 26 in that the dimension of the trench groove 35 is increased in the longitudinal direction of the wiring 37, 38, 39, and the contact structure is increased. The area is large.

FIG. 33 shows an SO according to another embodiment of the present invention.
It is a top view showing the structure of the inductor formed in I board. FIG. 34 is a cross-sectional view of the inductor of FIG. 33, and FIGS. 34A and 34B are a cross-sectional view of the inductor of FIG. ing.

The trench 3 is formed on the surface of the silicon layer 33.
A plurality of n ⁺ -type diffusion layers 34 insulated and separated by 2 are selectively formed, and the overall shape of the plurality of n ⁺ -type diffusion layers 34 is a longitudinal ladder-like shape in the drawing. Has become. A high magnetic permeability layer 47 having a higher magnetic permeability than the oxide film 36 is provided on the oxide film 36, and the high magnetic permeability layer 47 is covered with the oxide film 46. A plurality of wirings 48 are provided on the high magnetic permeability layer 47. Both ends of each of the wirings 48 are connected to different n ⁺ -type diffusion layers 34 which are adjacent to each other and are insulated and separated from each other.

That is, an inductor having a structure in which the high magnetic permeability layer 47 is effectively wound by helical wiring (a plurality of wirings 48) is formed. Similar to the above-described embodiment, a trench filled with a conductive material is formed in n ⁺ -type diffusion layer 34, and wiring 48 is connected to n ⁺ through conductive material filled in the trench. It may be connected to the mold diffusion layer 34.

FIG. 35 is a diagram showing a wiring structure according to another embodiment of the present invention. FIG. 35 (a) is a plan view showing the wiring structure, and FIG. 35 (b) is a diagram showing the same. It is a JJ 'sectional view of the wiring structure of (a).

The silicon layer 3 under the wiring 49 is formed by the trench 50 and the silicon oxide film 2 so that the trench 5
It is electrically separated from the other silicon layer 3. Therefore, interference between the wiring 49 in the trench 50 and other wirings and elements outside the trench 50 via the silicon layer 3 can be reduced. Note that LOCOS is used instead of the trench.
May be used.

FIG. 36 is a sectional view showing a wiring structure according to another embodiment of the present invention.

This is a modification of the MOSFET shown in FIG. 35, in which the silicon layer 3 below the wiring 49 is insulated and separated by two trench grooves 50 and 51.

FIG. 37 shows an SO according to another embodiment of the present invention.
FIG. 3 is a diagram showing a structure of an inductor formed on an I substrate;
FIG. 2A is a plan view showing the structure of the inductor.
FIG. 2B is a sectional view taken along line KK ′ of the inductor shown in FIG. FIG. 38 shows an equivalent circuit of the inductor of FIG.

The silicon layer 33 is divided into a plurality of potential independent regions by the trench 35. A spiral wiring 52 is formed on the silicon layer 33 with a silicon oxide film 36 interposed therebetween.

According to the inductor configured as described above, since the silicon layer 33 is divided into a plurality of regions which are electrically independent from each other, the silicon layer 33 is different from the conventional inductor shown in FIGS. capacitive coupling C ₁ wiring 52 between the via is reduced.

In the present embodiment, a capacitive coupling C ₂ between the silicon layers 33 occurs. However, since the coupling C ₂ is sufficiently small, a substantial increase in the capacitive coupling does not occur.

FIG. 41 shows an SO according to another embodiment of the present invention.
FIG. 3 is a diagram showing a structure of an inductor formed on an I substrate;
FIG. 2A is a plan view showing the structure of the inductor.
FIG. 2B is a sectional view taken along line MM ′ of the inductor in FIG.

The silicon layer 33 is divided into a plurality of potential independent regions by the trench 35. A first L-shaped electrode 53 is provided on the silicon layer 33 with a silicon oxide film 36 interposed therebetween. Both ends of each of the first L-shaped electrodes 53 are connected to the silicon layers 33 in adjacent and potential-independent regions different from each other.

On the first L-shaped electrode 53, there is provided a high magnetic permeability layer 55 which is not in direct contact with the first L-shaped electrode 53 by an oxide film 54. On this high magnetic permeability layer 55, an oxide film is provided. 56
, A second L-shaped electrode 57 is provided. Both ends of each second L-shaped electrode 57 are adjacent to each other, and the first L
It is connected to one end of the V-shaped electrode 53.

According to the inductor configured as described above, since the silicon layer 33 is divided into a plurality of regions which are electrically independent from each other, the capacitance between the L-shaped wirings 53 and 57 via the silicon layer 33 is reduced. Dynamic coupling is reduced.

FIG. 42 shows an MO according to another embodiment of the present invention.
FIG. 3 is a plan view illustrating a structure of an SFET. Also, FIG.
42 (a), FIG. 42 (b), and FIG. 42 (c) are cross-sectional views of the MOSFET of FIG. 45 taken along line NN 'and line OO', respectively. , P-
The O 'sectional view is shown.

In the figure, reference numeral 61 denotes a silicon support substrate, and a silicon oxide film 6 is formed on the silicon support substrate 61.
2, a silicon layer 63 is sequentially provided, and the silicon oxide film 62 and the silicon layer 63 form an SOI structure.

A silicon oxide film 62 is formed on the silicon layer 63.
Is formed selectively by LOCOS so that a thick silicon oxide film 72 reaching to
The area of the silicon layer 63 is smaller than that of ET.

That is, most of the silicon layer 63 in a region that does not function as an active region (element operation region) of the MOSFET is converted into a thick silicon oxide film 72.

In the remaining silicon layer 63, a p-type diffusion layer 67, an n-type source diffusion layer 68, and an n-type drain diffusion layer 69, which become channel regions, are formed in the same manner as a normal MOSFET.

A gate electrode 66 is provided on a p-type diffusion layer 67 between an n-type source diffusion layer 68 and an n-type drain diffusion layer 63 via a gate insulating film 70. A source electrode 64 and a drain electrode 65 are provided on the diffusion layer 68 and the n-type drain diffusion layer 69, respectively. Further, the extraction electrode 71 of the gate electrode 66 is also formed on the thick silicon oxide film 72.

The contact between the element operation region and the electrode is partial, for example, the contact between the drain electrode 65 and the remaining silicon layer 63 shown in FIG.

According to the MOSFET configured as described above, since the silicon layer 63 which is not directly involved in the element operation is changed to the thick silicon oxide film 72, the distance between the electrodes and the electrode
The parasitic capacitance between the substrates can be reduced. Therefore, a MOSFET that operates at a higher speed than the conventional MOSFET can be obtained.

FIGS. 44A and 44B are cross sectional views showing the structure of a bipolar transistor according to another embodiment of the present invention. FIGS. 44A and 44B are cross sectional views of FIGS. 43A and 43B, respectively. It corresponds to the figure.

As in the previous embodiment, the silicon layer 63 constituting the SOI structure not directly involved in the device operation is
The OS has changed to a thick silicon oxide film 72, and the remaining silicon layer 63 has n ⁺ -type collector diffusion layers 76 and n
A type offset diffusion layer 75, a p-type base diffusion layer 74, and an n-type emitter diffusion layer 73 are formed.

An oxide film 77 is formed on a region from n ⁺ type collector diffusion layer 76 to n type offset diffusion layer 75, and a base electrode 79 made of polysilicon is formed to cover oxide film 77. . This base electrode 7
9 is silicided, and a side wall insulating film 78 is formed on the side of the base electrode 79 and the side of the oxide film 77. The emitter electrode 80 and the collector electrode 81 are formed so as to cross the island-shaped thick silicon oxide film 72 group.

Even in the bipolar transistor thus configured, the operation speed is higher than that of the conventional bipolar transistor because the silicon layer 63 that does not directly participate in the element operation causing the parasitic capacitance is reduced.

FIG. 45 shows an MO according to another embodiment of the present invention.
FIG. 3A is a diagram showing the structure of an SFET, and FIG.
FIG. 2 is a plan view showing the structure of the FET, and FIG. 2B is a cross-sectional view taken along line QQ ′ of the MOSFET in FIG.

The difference between the MOSFET of this embodiment and that of FIG. 42 is that a thick silicon oxide film 72 surrounding the silicon layer 72 serving as an element operation region is used instead of forming an island-like thick silicon oxide film 72 group by LOCOS. The film 72 is L
It is formed by OCOS.

The source electrode 64 is connected to the n
Type source diffusion layer 68, and the drain electrode 6
5 is connected to the n-type drain diffusion layer 69 via the arm-shaped electrode 82.

In the MOSFET configured as described above,
The parasitic capacitance is reduced, and the source electrode 64 and the drain electrode 65 are entirely formed of a thick silicon oxide film 72.
Since there is no contact with the silicon layer formed on
The parasitic capacitance is smaller than that of the MOSFET of FIG.

FIG. 46 is a diagram showing the structure of a bipolar transistor according to another embodiment of the present invention.
FIG. 2 is a plan view showing the structure of the bipolar transistor, and FIG. 2B is a cross-sectional view of the bipolar transistor of FIG.

In the bipolar transistor of this embodiment,
Like the MOSFET of FIG. 45, a thick silicon oxide film 72 surrounding the silicon layer 72 serving as an element operation region
It is formed by LOCOS. Further, the emitter electrode 80 is connected to the n-type emitter diffusion layer 73 via the arm-shaped electrode 83, and similarly, the collector electrode 81 is connected to the n ⁺ -type collector diffusion layer 76 via the arm-shaped electrode 82. In the drawing, reference numeral 84 denotes an extraction electrode of the base electrode 79.

The bipolar transistor thus configured also has a smaller parasitic capacitance than that of the bipolar transistor of FIG. 44 for the same reason as in the case of the MOSFET of FIG.

FIG. 47 is a diagram showing a structure of a bipolar transistor according to another embodiment of the present invention.
FIG. 3 is a plan view showing the structure of the bipolar transistor, and FIG. 3B is a cross-sectional view of the bipolar transistor shown in FIG.

This is a modification of a part of the bipolar transistor shown in FIG.
2 is an example in which a thin material such as SIMOX is used. The emitter electrode 80 is connected to the n-type emitter diffusion layer 73 via a band electrode 86 instead of the arm-shaped electrode 83, and the collector electrode 81 is similarly connected to the n ⁺ type collector diffusion layer 76 via the band electrode 85. I have.

The bipolar transistor thus configured also has a smaller parasitic capacitance than a conventional bipolar transistor using SIMOX or the like.

FIG. 48 shows an MO according to another embodiment of the present invention.
FIG. 3 is a cross-sectional view illustrating a structure of an SFET.

This is a modification of a part of the MOSFET shown in FIG.
This is an example using a thin material such as IMOX. The source electrode 64 is connected to the n-type source diffusion layer 85 through the strip electrode 86.
Similarly, the drain electrode 65 is connected to the n-type drain diffusion layer 69 via the strip electrode 85.

In the MOSFET configured as described above,
The silicon layer that causes the parasitic capacitance is the conventional SIMOX
Since it is less than the MOSFET using
The operation speed becomes faster.

FIG. 49 shows an SO according to another embodiment of the present invention.
It is a process sectional view showing the formation method of the I substrate.

[0139] First, as shown in FIG. 49 (a), conductivity type as the silicon supporting substrate 91 is p ^- type, plane orientation (10
0) Then, a silicon wafer whose surface is mirror-polished is prepared, and this silicon support base 91 is anodized,
As shown in FIG. 49B, a porous silicon layer 92 is formed on the surface of a silicon support base 91.

More specifically, first, the silicon support base 91
An electrode is formed on the back surface, and a lead wire is connected to this electrode. Next, after protecting the electrodes with an oxidation-resistant tape or wax, the silicon support base 91 is anodized in a mixed solution of hydrofluoric acid and ethanol.

Here, for example, a current density of 20 mA / cm
By performing anodization under the conditions of ² , a porous silicon layer 92 having a thickness of about 10 μm is obtained. This porous silicon layer 9
The thickness of No. 2 can be adjusted over a wide range by changing the conditions of the anodization, and for example, can be set to a thickness exceeding 100 μm.

Further, instead of the method using the electrodes,
Anodization may be performed by a liquid back contact method. Specifically, as shown in FIG. 50, the front and back surfaces of the silicon support base 91 are separated by a partition plate 99 and an O-ring 100, and the back surface of the silicon support base 91 and an anode electrode (back contact electrode) 96 are formed. The space is filled with the back contact electrolyte 98 and the silicon support base 9 is filled.
If the anodization is performed so that the space between the front surface of the first electrode 1 and the cathode electrode 95 is filled with a mixed solution of hydrofluoric acid and ethanol, the above electrode becomes unnecessary.

Thereafter, as shown in FIG. 49C, for example, 1100 in a dry or wet oxygen atmosphere.
The porous silicon layer 92 is converted into an insulating film 93 by thermal oxidation at
Convert to In this oxidation step, it is only necessary to increase the resistance of the porous silicon layer 92 to a required level, and it is not always necessary to convert the porous silicon layer 92 to a complete insulating film.

Here, since the surface of the insulating film 93 may not always have sufficient flatness, the surface of the insulating film 93 is polished as necessary.

Next, as shown in FIG. 49D, the silicon substrate 94 for element formation and the insulating film 93 are bonded. In order to reduce contamination from the bonding interface, it is desirable to form an oxide film on the surface of the silicon substrate 94 on the bonding surface side.

Finally, as shown in FIG. 49 (e), the surface of the silicon substrate 94 is polished to complete an SOI substrate having a device-forming silicon layer of a desired thickness.

According to the above-described forming method, the insulating film 93 is formed.
Is determined by the porous silicon layer 92, which can be easily made thick, and an insulating film 93 having a thickness of 100 μm or more can be obtained.

On the other hand, in the conventional method, the insulating film is formed by thermal oxidation of silicon. In this case, the thickness of the insulating film is limited to 3 μm.

For this reason, according to the present embodiment, a thicker insulating film 93 can be obtained than in the conventional method.
Parasitic capacitance between the semiconductor substrate 91 and the silicon support base 91 can be reduced. Therefore, the high-frequency MO described in the above embodiment is used.
By using the SOI substrate of this embodiment for a transistor requiring high-speed operation such as an SFET, the speed can be further increased.

A large voltage called a power device,
By using the SOI substrate of this embodiment for a device with a large current, a power device with a high withstand voltage can be obtained.

FIG. 51 is a sectional view showing the structure of a coil according to another embodiment of the present invention.

This is an example in which a coil is formed on an in-vehicle small signal processing circuit chip using an SOI substrate obtained by the above method.

This will be described according to the forming process.
At the same time as forming an element such as a transistor (not shown) on the silicon substrate 94 for element formation, a predetermined portion of the coil formation region of the silicon substrate 94 is etched until the insulating film 93 is exposed.

Next, after depositing a metal film in the coil forming region, this metal film is patterned to form a spiral coil 101.

Next, after forming the insulating film 102, the coil 1
A contact hole is opened in a portion of the insulating film 102 corresponding to the other end of the insulating film 102.

Finally, a lead electrode 103 that contacts the coil 101 via the contact hole is formed.

FIG. 52 is a diagram showing an SO according to another embodiment of the present invention.
It is a process sectional view showing the formation method of the I substrate.

As shown in FIG. 52A, after a silicon oxide film 112 and a silicon nitride film 113 are sequentially formed on a silicon support base 111, these insulating films 112 and 113 are formed.
Is patterned to expose a desired region of the silicon support substrate 111.

Next, as shown in FIG. 52B, anodization is performed using the silicon oxide film 112 and the silicon nitride film 113 as a mask, and the porous silicon layer 114 is selectively formed only on the exposed silicon support base 111. Form.

Next, as shown in FIG. 52C, the porous silicon layer 114 is converted into an insulating film 115 by thermal oxidation. As a result, the insulating film 115 is formed only in a desired region.

Next, as shown in FIG. 52D, after the silicon oxide film 112 and the silicon nitride film 113 are removed, as shown in FIG.
17 and the insulating film 115.

Finally, as shown in FIG. 52 (f), the surface of the silicon substrate 117 is polished to complete an SOI substrate having an element forming silicon layer of a desired thickness.

According to the above-described forming method, the capacitance and the dielectric strength of a desired portion between the silicon support base 111 and the silicon substrate 117 can be changed, so that a highly flexible integrated element can be designed. Becomes

FIG. 53 shows an SO according to another embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a main part of a semiconductor integrated circuit using an I substrate.

In the figure, reference numeral 121 denotes a silicon support base 121, on which a silicon oxide film 122 is formed.

In the figure, a silicon layer 120 is formed on the silicon oxide film 122 in the left region 127, and a transistor (MOSFE) is formed in the silicon layer 120.
T) Tr1, transistor (bipolar transistor)
Active elements such as Tr2 and Tr3 are formed. These transistors Tr1, Tr2, Tr3 are formed in the trench 12
5 are insulated from each other.

On the other hand, a porous silicon layer 123 is formed on the silicon oxide film 122 in the region 126 on the right side in the figure, and a passive element such as a wiring or a planar inductor is formed on the porous silicon layer 123. I have.

According to the semiconductor integrated circuit configured as described above, the porous silicon layer 123 is used as an insulating film on the silicon oxide film 122 in the region 126 where the wiring and the planar inductor that cause the parasitic capacitance are formed. Is used, the capacitance between the substrate and the wiring and the parasitic capacitance between the substrate and the inductor can be greatly reduced.

FIG. 54 shows an SO according to another embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a main part of a semiconductor integrated circuit using an I substrate.

This is a modification of a part of the semiconductor integrated circuit shown in FIG. 53, in which the silicon layer 120 and the silicon oxide film 122 in the region 126 are removed, and the exposed silicon support base 12 is removed.
This is an example in which 1 is converted into a porous silicon layer 123, and a wiring, a planar inductor, and the like are formed on the porous silicon layer 123. In the case of this embodiment, the thicker porous silicon layer 1
As a result, the parasitic capacitance can be further reduced.

FIG. 55 shows an SO according to another embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a main part of a semiconductor integrated circuit using an I substrate.

This is because the silicon oxide film 12 is
This is an example in which the porous silicon layer 123 is formed from the surface of the silicon layer without forming the layer 2. In the case of the present embodiment, the step between the region 126 and the region 127 as in the semiconductor integrated circuit of FIG. 54 is eliminated, and the porous silicon layer 123 becomes thicker by the absence of the silicon oxide film 122. The capacity can be greatly reduced.

FIG. 56 shows an SO according to another embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a main part of a semiconductor integrated circuit using an I substrate.

This is a modification of a part of the semiconductor integrated circuit shown in FIG. 55. A transistor (bipolar transistor) Tr4 which is an active element is formed in a region 126 in addition to a passive element such as a planar inductor in a region 126 as in the case of the region 127. This is an example.

Since the parasitic capacitance is small on the porous silicon layer 123, the performance of the semiconductor integrated circuit can be significantly improved by forming a transistor which requires high-speed operation among the transistors in the region 127 in the region 126.

[0176]

As described above, according to the present invention, the second main electrode and the channel region are connected via the second first conductivity type semiconductor layer which is not included in the conventional field effect transistor. Therefore, by thinning the semiconductor layer for element formation,
Even if the channel region is electrically separated from the second second conductivity type semiconductor layer, the potential of the channel region does not float. Therefore, it is possible to prevent a device operation defect due to an abnormal potential in the channel region due to the thinning of the device forming semiconductor layer.

[Brief description of the drawings]

FIG. 1 is a diagram showing a structure of a MOSFET according to one embodiment of the present invention.

FIG. 2 is a characteristic diagram showing a relationship between a silicon layer and an output capacitance.

FIG. 3 is a characteristic diagram showing a relationship between W / _tox and output capacity.

FIG. 4 is a characteristic diagram showing a relationship between W / _tox and output capacity.

FIG. 5 is a characteristic diagram showing a relationship between a silicon oxide film and an output capacitance.

FIG. 6 is a plan view of a MOSFET according to another embodiment of the present invention.

FIG. 7 is a plan view of a MOSFET according to another embodiment of the present invention.

FIG. 8 is a cross-sectional view of a MOSFET according to another embodiment of the present invention.

FIG. 9 is a sectional view of a MOSFET according to another embodiment of the present invention.

FIG. 10 is a cross-sectional view of a MOSFET according to another embodiment of the present invention.

FIG. 11 is a sectional view of a MOSFET according to another embodiment of the present invention.

FIG. 12 is a sectional view of a MOSFET according to another embodiment of the present invention.

FIG. 13 is a process sectional view illustrating a method of forming the gate electrode portion of the MOSFET in FIG. 11;

FIG. 14 is a process cross-sectional view showing another method for forming the gate electrode portion of the MOSFET in FIG. 11;

FIG. 15 is a sectional view of a MOSFET according to another embodiment of the present invention.

FIG. 16 is a sectional view of a MOSFET according to another embodiment of the present invention.

FIG. 17 is a sectional view of a MOSFET according to another embodiment of the present invention.

FIG. 18 is a sectional view of a MOSFET according to another embodiment of the present invention.

FIG. 19 is a sectional view of a MOSFET according to another embodiment of the present invention.

FIG. 20 is a sectional view of a MOSFET according to another embodiment of the present invention.

FIG. 21 is a sectional view of a MOSFET according to another embodiment of the present invention.

FIG. 22 is a sectional view of a MOSFET according to another embodiment of the present invention.

FIG. 23 is a sectional view of a MOSFET according to another embodiment of the present invention.

FIG. 24 is a sectional view of a MOSFET according to another embodiment of the present invention.

FIG. 25 is a sectional view of a MOSFET according to another embodiment of the present invention.

FIG. 26 is a plan view showing a wiring structure according to another embodiment of the present invention.

FIG. 27 is a sectional view of the wiring structure of FIG. 26;

FIG. 28 is a plan view showing a wiring structure according to another embodiment of the present invention.

FIG. 29 is a sectional view of the wiring structure of FIG. 29;

FIG. 30 is a sectional view showing a wiring structure according to another embodiment of the present invention.

FIG. 31 is a sectional view showing a wiring structure according to another embodiment of the present invention.

FIG. 32 is a plan view showing a wiring structure according to another embodiment of the present invention.

FIG. 33 is a plan view showing the structure of an inductor formed on an SOI substrate according to another embodiment of the present invention.

FIG. 34 is a sectional view of the inductor of FIG. 33;

FIG. 35 is a diagram showing a wiring structure according to another embodiment of the present invention.

FIG. 36 is a sectional view showing a wiring structure according to another embodiment of the present invention.

FIG. 37 is a view showing a structure of an inductor formed on an SOI substrate according to another embodiment of the present invention.

FIG. 38 is a diagram showing an equivalent circuit of the inductor of FIG. 35;

FIG. 39 is a diagram showing a structure of an inductor formed on a conventional SOI substrate.

FIG. 40 is a diagram showing an equivalent circuit of the inductor of FIG. 39;

FIG. 41 is a view showing a structure of an inductor formed on an SOI substrate according to another embodiment of the present invention.

FIG. 42 is a plan view showing the structure of a MOSFET according to another embodiment of the present invention.

FIG. 43 is a sectional view of the MOSFET shown in FIG. 42;

FIG. 44 is a sectional view showing the structure of a bipolar transistor according to another embodiment of the present invention.

FIG. 45 is a view showing the structure of a MOSFET according to another embodiment of the present invention.

FIG. 46 is a sectional view showing the structure of a bipolar transistor according to another embodiment of the present invention.

FIG. 47 is a sectional view showing the structure of a bipolar transistor according to another embodiment of the present invention.

FIG. 48 is a view showing the structure of a MOSFET according to another embodiment of the present invention.

FIG. 49 is a process sectional view showing the method for forming the SOI substrate according to another embodiment of the present invention;

FIG. 50 is a view illustrating a method of forming a porous silicon layer by a liquid back contact method.

FIG. 51 is a sectional view showing the structure of a coil formed on an SOI substrate according to another embodiment of the present invention.

FIG. 52 is a process sectional view showing the method for forming the SOI substrate according to another embodiment of the present invention;

FIG. 53 is a sectional view showing a main part of a semiconductor integrated circuit using an SOI substrate according to another embodiment of the present invention.

FIG. 54 is a sectional view showing a main part of a semiconductor integrated circuit using an SOI substrate according to another embodiment of the present invention.

FIG. 55 is a sectional view showing an essential part of a semiconductor integrated circuit using an SOI substrate according to another embodiment of the present invention.

FIG. 56 is a sectional view showing a main part of a semiconductor integrated circuit using an SOI substrate according to another embodiment of the present invention.

FIG. 57 is a sectional view showing the structure of a conventional MOSFET.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon support base 2 ... Silicon oxide film (insulating base) 3 ... n ⁺ type diffusion layer 4 ... n-type source diffusion layer (2nd 2nd conductivity type semiconductor layer) 5 ... p-type diffusion layer (1st first conductivity type semiconductor layer) 6 ... n-type drain diffusion layer (the first second-conductivity type semiconductor layer) 7 ... n ⁺ -type diffusion layer 8 ... gate insulating film (insulating film) 9 ... source electrode (second main electrode 10: gate electrode (control electrode) 11: drain electrode (first main electrode) 12: p ⁺ type short-circuit diffusion layer (second first conductivity type semiconductor layer) 17: silicon layer (element forming semiconductor) layer)

Continuation of the front page (72) Inventor Masayuki Sekimura 1 Tokoba, Komukai Toshiba-cho, Saisaki-ku, Kawasaki City, Kanagawa Prefecture (56) References JP-A-2-214165 (JP, A) JP-A-4 -226082 (JP, A) Japanese Utility Model Showa 61-256 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/786 H01L 21/336

Claims (4)

(57) [Claims] 1. A holding layer comprising a first layer made of an insulating material and a second layer made of a semiconductor material; an active layer made of a semiconductor material formed on the first layer; A base layer formed in the active layer and extending from the surface of the active layer to the first layer; a first conductive layer formed in the active layer and adjacent to the base layer and extending from the surface of the active layer to the first layer A source layer connected to the source layer; a source electrode connected to the source layer; a source electrode formed in the active layer, facing the source layer across the base layer, and extending from the surface of the active layer to the first layer. A first conductivity type drain layer; a drain electrode connected to the drain layer; and a gate for inducing a first conductivity type inversion layer on the surface of the base layer between the source layer and the drain layer. Through the insulating film, A gate electrode facing the source layer; a short-circuit layer formed in the active layer adjacent to the source layer so as to connect the base layer to the source electrode; A connection member made of a conductive and thermally conductive material penetrating the first layer so as to be electrically and thermally connected, and a means for grounding the second layer. Field effect transistor. 2. The semiconductor device according to claim 1, wherein the drain electrode has an extension facing the source electrode with an insulating layer interposed therebetween.
The field effect transistor according to claim 1 . 3. The semiconductor device according to claim 2, wherein the source layer includes a plurality of source layer portions, the short-circuit layer includes a plurality of short-circuit layer portions, and the source layer portions and the short-circuit layer portions are alternately arranged. The field effect transistor according to claim 1 , wherein 4. The field effect transistor according to claim 1 , wherein said connecting member extends into a trench formed in said first layer, and said trench is not completely filled by said connecting member. .