JP2002343964A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device wherein operation of a parasitic transistor can be restrained, and to provide its manufacturing method. SOLUTION: A surface layer of a substrate 1 is subjected to dielectric isolation by using a trench 2 formed by an STI technique and an element isolation insulating film 4 with which the inside of the trench 2 is filled, and an element forming region is formed. A gate oxide film 10 formed on a surface of the substrate 1 in the element forming region is stretched up to a region in which a corner of a surface of the element isolation insulating film 4 is eliminated, and a gate electrode 11 is formed on the gate oxide film 10, so that the gate electrode 11 is also arranged on an upper part of a sidewall of the trench 2, and a parasitic transistor is formed above the trench 2. By forming an ion implanting layer 14 for parasitic Tr adjustment on a channel region 9 of the parasitic transistor, a threshold voltage of the parasitic transistor is adjusted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an STI (Shallow T
1. Field of the Invention The present invention relates to a semiconductor device for performing element isolation using a technique of "rench isolation" and a method of manufacturing the same.

[0002]

2. Description of the Related Art In an integrated circuit in a semiconductor device, a memory transistor, a transistor used for Logic, and the like are formed. FIG. 13 is a schematic cross-sectional view showing a conventional configuration of a transistor used for Logic among such various transistors. As shown in FIG.
If the transistors are isolated by STI technology,
A trench 202 is formed in a surface portion of the semiconductor substrate 201, an oxide film 203 is formed on a side wall of the trench 202, and an element isolation insulating film 204 is embedded in the trench 202. Then, a transistor is formed in the insulated region.

In this transistor, a source region and a drain region are formed in a surface layer portion of an insulated semiconductor substrate 201, and a gate is formed on a surface of the semiconductor substrate 201 on a portion of the semiconductor substrate 201 between the source region and the drain region. An insulating film 205 is formed, and a gate electrode 206 is formed over the gate insulating film 205.

Further, a plurality of transistors are formed on a semiconductor substrate 201, and various voltages are applied to the gate electrodes of the respective transistors according to the required specifications of the product. The gate insulating film has a large thickness.

[0005] For example, in the case of forming two transistors having different gate insulating film thicknesses (hereinafter referred to as first and second transistors, and the transistor shown in FIG. 13 as a second transistor), first, Then, the semiconductor substrate is separated by STI technology. When the gate insulating film (first gate insulating film) of the first transistor is formed, the first region is also formed in the region where the gate insulating film (second gate insulating film) 205 of the second transistor is formed. An insulating film having the same thickness as that of the gate insulating film is formed.

Therefore, when the second gate insulating film 205 is formed, an insulating film having the same thickness as the first gate insulating film in the second transistor is removed by etching, and then the second gate insulating film is formed. 205 is formed with a desired film thickness.

[0007]

However, when the second gate insulating film 205 is formed, the insulating film having the same thickness as the first gate insulating film is removed and the element isolation insulating film is also etched. In particular, when the insulating film is removed by wet etching, the wet etching proceeds isotropically, so that the etching amount at the corner of the element isolation insulating film 204 becomes large. Then, as shown in FIG.
The side wall above the trench 202 in the semiconductor substrate is exposed from the element isolation insulating film 204.

[0008] Then, by forming the second gate insulating film 205 by thermal oxidation or the like in this state, the second gate insulating film 205 is extended to the exposed side wall of the trench 202. Further, since the gate electrode 206 is formed up to the vicinity of the side wall above the trench 202, a transistor is formed also above the trench 202. Less than,
The transistor formed above the trench 202 is called a parasitic transistor.

In this parasitic transistor, compared to the original second transistor using the portion of the second gate insulating film 205 formed on the surface of the semiconductor substrate 201,
The thickness of the gate insulating film is small, and the ion concentration of the ion implantation layer 207 formed in the surface portion of the semiconductor substrate 201 is low in order to adjust the threshold voltage at the gate.

The reason why the thickness of the gate insulating film is small is that the ease with which the insulating film is formed varies depending on the plane orientation of the semiconductor substrate 201, and the insulating film is formed more on the side wall of the trench than on the surface of the semiconductor substrate. It seems that it is hard to be done.
The ion implantation layer 207 is formed for the purpose of adjusting the ion concentration near the surface of the semiconductor substrate 201 in order to adjust the threshold voltage of the transistor portion. Therefore, the ion concentration decreases as the distance from the surface of the semiconductor substrate 201 increases.

As described above, in the parasitic transistor, the threshold voltage is low because the gate insulating film is thin and the ion concentration is low. Therefore, when a voltage is applied to the gate electrode 206, a parasitic transistor operates to cause a kink characteristic of the transistor or a subthreshold leak.

In view of the above problems, an object of the present invention is to provide a semiconductor device capable of suppressing the operation of a parasitic transistor and a method of manufacturing the same.

[0013]

To achieve the above object, according to the first aspect of the present invention, a semiconductor substrate (1) includes:
An STI region formed having a trench (2) formed in the semiconductor substrate and an element isolation insulating film (4) buried in the trench; A gate insulating film formed on the surface of the semiconductor substrate between an element forming region which is a region, a source region (7) and a drain region (8) formed in a surface layer of the element forming region, and a source region and a drain region (1
0, 100) and a transistor portion having a gate electrode (11, 110) formed on the gate insulating film, the element isolation insulating film has a corner portion removed above the trench. The gate insulating film extends to a region from which the corners have been removed, and an ion-implanted layer (14) is formed on a portion of the inner surface of the trench opposite to the portion where the gate insulating film extends. Is formed, and a gate electrode is provided on the opposite side of the ion implantation layer with the gate insulating film interposed therebetween.

Thus, the threshold voltage of the parasitic transistor formed on the side wall of the trench can be adjusted by adjusting the ion concentration of the ion implantation layer. Therefore, a semiconductor device capable of suppressing the operation of the parasitic transistor can be provided.

In this case, according to the second aspect of the present invention, the value of the threshold voltage in the transistor portion is determined by the threshold value in the parasitic transistor formed including the gate insulating film extending above the sidewall of the trench. It is characterized in that it is smaller than the value of the value voltage.

Accordingly, the operation of the parasitic transistor formed on the side wall of the trench can be suitably suppressed.

According to the third aspect of the present invention, a trench forming step of forming a trench (2) in the semiconductor substrate (1), an ion implanting step of implanting ions into at least the inner surface of the side wall of the trench, An isolation step for forming an STI region for insulating and isolating the semiconductor substrate by embedding an element isolation insulating film (4) in the semiconductor substrate, and an element formation region including an upper portion of the sidewall of the trench and insulated by the STI region of the semiconductor substrate Gate insulating film (10, 10
0) and a step of forming a gate electrode (11, 110) on the gate insulating film on the side wall of the trench and on the surface of the element formation region.

Thus, the semiconductor device according to the first aspect can be appropriately manufactured.

In this case, specifically, it is preferable that the ion implantation step is performed between the trench forming step and the isolation step, and the ion implantation is performed from the side wall of the trench.

According to a fifth aspect of the present invention, in the third aspect of the invention, the ion implantation step is performed after the insulation separation step, and ions are implanted from the surface of the semiconductor substrate in a layer substantially parallel to the surface. You may.

Note that the reference numerals in parentheses of the above means indicate the correspondence with specific means described in the embodiments described later.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) The embodiment shown in the drawings will be described below. In the present embodiment, at least the thickness of the gate insulating film is different on the same semiconductor substrate.
A description will be given assuming that the present invention is applied to a semiconductor device in which a transistor (hereinafter simply referred to as a transistor) used for a type of Logic and a memory transistor are formed. First, the configuration of the transistor unit will be described with reference to FIGS. 1 to 3 using one transistor formed in the semiconductor device of the present embodiment. FIG. 1 is a top view showing the layout of the transistor of the present embodiment, and FIG.
3 is a diagram schematically showing an AA section, and FIG. 3 is a diagram schematically showing a BB cross section in FIG.

A trench 2 is formed in a surface layer portion of a semiconductor substrate (hereinafter, simply referred to as a substrate) 1 made of Si or the like, and an element isolation insulating film 4 is buried in the trench 2 to form an STI region. The substrate 1 is insulated and separated by the STI region to form an element formation region.

More specifically, in this STI region, a trench 2 is formed from the surface of the substrate 1 to the middle of the substrate 1, and an oxide film (hereinafter referred to as a sidewall oxide film) 3 is formed on the side wall of the trench 2.
Is formed, and the inside of the trench 2 is filled with the element isolation insulating film 4.

A source region 7 and a drain region 8 are formed in the surface layer of the substrate 1 in the element formation region. A gate oxide film 1 serving as a gate insulating film is formed on the surface of the substrate 1 between the source region 7 and the drain region 8.
0 is formed. Hereinafter, a portion of the substrate 1 between the source region 7 and the drain region 8 is referred to as a channel region 9.
That.

On the gate oxide film 10, a gate electrode 11 is formed. Thus, the gate oxide film 10
The channel region 9 and the gate electrode 11 are arranged to face each other with a via formed therebetween, and a transistor portion is formed.

The corners of the element isolation insulating film 4 buried in the trenches 2 are removed at the upper portions of the trenches 2, and the sidewall oxide films 3 are also removed in the regions where the corners are removed. Then, the gate oxide film 1 is extended to a region where the corner is removed, that is, to the upper portion of the side wall of the trench 2.
0 is extended. Hereinafter, a portion of the gate oxide film 10 above the sidewall of the trench 2 is referred to as a sidewall gate oxide film 10a.
That.

Further, as shown in FIG. 1, the gate electrode 11 extends on the element isolation insulating film 4 in a direction perpendicular to the direction of current flow in the channel region 9. The gate electrode 11 also extends to a portion of the element isolation insulating film 4 where the corner is removed.

In other words, at a portion of the side wall of the trench 2 below the gate electrode 11 where the corner of the element isolation insulating film 4 is removed, the side wall of the trench 2 and the gate electrode 11 are interposed via the side wall gate oxide film 10a. Are placed facing each other. That is, a parasitic transistor is formed on the side wall of the trench 2.

Further, ions are implanted into the channel region 9 to adjust the threshold value between the gate electrode 11 and the substrate 1 in the transistor portion. An ion implantation layer 14 is formed on at least a portion of the inner surface of the trench 2 facing the side wall gate oxide film 10a, that is, a channel region (hereinafter referred to as a parasitic channel region) 13 of the parasitic transistor. Therefore, the gate electrode 11 is arranged on the opposite side of the ion implantation layer 14 with the side wall gate oxide film 10a interposed therebetween.

The ion implantation layer 14 is formed to adjust the threshold voltage of the parasitic transistor, and is hereinafter referred to as a parasitic Tr adjustment ion implantation layer. In this embodiment, as shown in FIG. 2, the parasitic Tr adjusting ion-implanted layer 14 extends not only from the parasitic channel region 13 but also from the parasitic channel region 13 to the depth of the trench 2 along the inner surface of the trench 2. Is formed.

The thickness of the gate oxide film 10 and the channel concentration of each are adjusted so that the threshold value of the gate voltage in the transistor section is smaller than the threshold value of the gate voltage of the parasitic transistor. . These specific numerical values and the like will be described in a manufacturing method described later.

A well region 5 is formed in a surface layer portion of the substrate 1 in the element formation region, and a retrograde well 6 is formed at a depth immediately below the trench 2.
An ion implantation layer 12 for preventing punch-through is formed below the channel region 9.

An insulating film 15 is formed on the gate electrode 11, an interlayer insulating film 16 having a different composition from that of the insulating film 15 is formed on the insulating film, and an Al film is formed on the interlayer insulating film 16.
Wiring (not shown) is formed, and the interlayer insulating film 1 is formed.
6, a contact hole 16a is formed. The contact hole 16a is filled with a wiring member 17a, and the wiring is electrically connected to the source region 7 and the drain region 8, respectively. Further, a protective film 18 is formed on the wiring. Thus, a semiconductor device in which a transistor is formed is configured.

Next, a method of manufacturing a semiconductor device having such a configuration will be described with an example in which two types of transistors having different thicknesses of the gate oxide film 10 and a memory transistor are formed on the same substrate 1. 4 to 11 are process diagrams showing a method of manufacturing a semiconductor device in a cross-sectional configuration of each transistor. 4 to 11, the left region is a memory formation region A for forming a memory transistor, the center region is an NchTr formation region B for forming an N-channel transistor, and the right region is a P-channel region. This is a PchTr formation region C where a transistor is formed. In addition, FIG.
The transistor illustrated in FIG. 3 corresponds to a P-channel transistor.

[Step shown in FIG. 4A] First, the substrate 1
Is prepared, an oxide film 21 is formed on the surface of the substrate 1, and a nitride film 22 is formed on the oxide film 21. Then, a resist 23 is formed such that a portion where the trench 2 is to be formed is opened.

[Step shown in FIG. 4B] Resist 23
Is used as a mask to pattern oxide film 22 and nitride film 23 to expose the surface of substrate 1 at a portion where trench 2 is to be formed. Then, the trench 2 is formed in the substrate 1 by performing etching or the like using the nitride film 23 as a mask. As described above, the steps shown in FIGS. 4A and 4B are trench forming steps.

[Step shown in FIG. 5A] After the sidewall oxide film 3 is formed on the sidewall of the trench 2, ions are implanted obliquely into the inner surface of the trench 2 to form the ion implantation layer 14 for adjusting the parasitic Tr. (Ion implantation step). This parasitic T
The ion implantation layer 14 for r adjustment does not necessarily need to be formed on the entire inner surface of the trench 2, but may be formed on at least the parasitic channel region 13. Specifically, depending on the depth at which the corners of the element isolation insulating film 4 are removed, ions are implanted into the inner surface of the trench 2 to a depth of about 500 nm from the surface of the substrate 1.

The carrier concentration of the parasitic channel region 13 is equal to or higher than the carrier concentration of the channel region 9 in the transistor portion. In addition, these ions change the conductivity type of the implanted region to N-type, and for example, phosphorus can be used.

[Step shown in FIG. 5B] Next, a resist 24 is formed on the substrate 1 in the memory formation region A and the NchTr formation region B. Then, in the PchTr formation region C, similarly to the step shown in FIG.
Are implanted into the inner surface of the substrate to form a parasitic Tr adjusting ion implantation layer 14 (ion implantation step). These ions make the conductivity type of the implanted region P-type, and for example, boron can be used.

[Step shown in FIG. 6A] The element isolation insulating film 4 is buried in the trench 2, the element isolation insulating film 4 is flattened using the nitride film 22 as a stopper, and an STI region for insulating and isolating the substrate 1 is formed. (Insulation separation step).

[Step shown in FIG. 6B] After the nitride film 22 is removed, first, the PchTr formation region C is covered with a resist, and the P-type well region 5 is formed in the memory formation region A and the NchTr formation region B. A retrograde well 6 is formed. Next, the memory formation region A and the NchTr formation region B are covered with a resist 25, and an N-type well region 5 and a retrograde well 6 are formed in the PchTr formation region C. The carrier concentration of these well regions 5 is 1% lower than the carrier concentration of channel region 9 of the transistor portion.
It is thinner than an order of magnitude.

[Step shown in FIG. 7A] The NchTr formation region B and the PchTr formation region C are covered with a resist 26, and an ion implantation layer 12 for preventing punch-through is formed in the memory formation region A. In addition, ions are implanted into the memory channel region 9 in the surface layer of the substrate 1.

[Step shown in FIG. 7B] Resist 26
Is removed, a gate oxide film for memory (hereinafter, referred to as a memory gate oxide film) 100 is formed by thermal oxidation or the like. At this time, an oxide film 27 having the same thickness as the memory gate oxide film 100 is formed also in the NchTr formation region B and the PchTr formation region C.

Then, a floating gate 110 is formed of polysilicon or the like on the memory gate oxide film 100, and an insulating film 160 such as an ONO film is formed on the floating gate 110. At this time, the floating gate 110 and the insulating film 160 are also formed in the NchTr formation region B and the PchTr formation region C.

[Step shown in FIG. 8A] A resist 28 is formed on the insulating film 160 in the memory formation region A,
The insulating film 160 and the floating gate 110 in the NchTr formation region B and the PchTr formation region C are removed. Then, the oxide film 27 formed when the memory gate oxide film 100 is formed is removed.

The removal of the oxide film 27 is performed by wet etching. At this time, since the etching in the wet etching proceeds isotropically, the amount of etching is particularly large at the corners of the element isolation insulating film 4 and the corners are removed. Further, the side wall oxide film 3 is also removed at the portion where the corner is removed, and the substrate 1 is exposed.

Thereafter, a gate oxide film 29 is formed on the surface of the element forming region of the substrate 1 including the upper part of the side wall of the trench 2 and insulated by the STI region (step of forming a gate oxide film). That is, since the step of forming the gate oxide film is performed in a state where the substrate 1 is exposed above the side wall of the trench 2, the gate oxide film is extended to above the side wall of the trench 2, and the side wall gate oxide film is formed. Is done.

The gate oxide film 29 is formed by thermal oxidation or the like so as to have a thickness suitable for the Nch transistor. However,
In the Nch transistor, when the gate oxide film in the Pch transistor is formed in the later-described [step shown in FIG. 9A], the thickness of the gate oxide film is further increased. From the film thickness of Pch
This gate oxide film 29 is formed with a thickness obtained by subtracting the thickness of the oxide film formed when the gate oxide film 10 of the transistor is formed. In addition, an oxide film 30 having a thickness suitable for the Nch transistor is formed not only in the NchTr formation region B but also in the PchTr formation region C.

Next, in each of the regions B and C, the ion implantation layer 12 for preventing punch-through is formed at a carrier concentration suitable for each of the Nch transistor and the Pch transistor.
Is formed, and ions are implanted into the channel region 9 to adjust the threshold voltage. The carrier concentration of these channel regions 9 is about 1 × 10 ^{16 to} 5 × 10 ¹⁷ / cm ³ . These channel regions 9 are formed, for example, to a depth of about 100 nm from the surface of the substrate 1.

[Step shown in FIG. 8B] A resist 31 is formed on the memory formation region A and the NchTr formation region B, and the oxide film 30 formed in accordance with the Nch transistor is removed in the PchTr formation region C. I do. As a result, the substrate 1 is exposed above the sidewall of the trench 2 in the PchTr formation region C in the same manner as in the step shown in FIG.

[Step shown in FIG. 9A] Resist 31
Is removed, the gate oxide film 10 of the Pch transistor is removed.
Is formed by thermal oxidation or the like (step of forming a gate oxide film). Thus, also in the Pch transistor, the side wall gate oxide film 10a is formed in the same manner as in the step shown in FIG.

Also, an oxide film is formed on the gate oxide film 29 of the Nch transistor, and the gate oxide film of the Nch transistor becomes thicker than the thickness formed in the above-described step shown in FIG. The gate oxide film 10 has a desired thickness. As a result, for example, the gate oxide film 10 of the Nch transistor has a thickness of about 10 to 40 nm,
The gate oxide film 10 of the Pch transistor has a thickness of 3 to 1
0 nm.

As a result, in the completed semiconductor device, N
The threshold voltage of the transistor portion in the chTr formation region B and the PchTr formation region C is about 0.4 to 1.0 V, and the threshold voltage of the parasitic transistor in the NchTr formation region B and the PchTr formation region C is lower than that of the transistor portion. It is equal to or higher than the threshold voltage.

[Step shown in FIG. 9B] A polysilicon layer is formed on the insulating film 160 in the memory formation region A and on the gate oxide film 10 on the NchTr formation region B and the PchMOSFET formation region C. The gate electrode 11 is formed by patterning the layer (step of forming a gate electrode). Thus, a gate electrode 11 is formed on the gate oxide film 10 above the sidewalls of the trench 2 and on the surface of the element formation region.

[Step shown in FIG. 10A] An insulating film 15 is formed on the gate electrode 11, and an interlayer insulating film 16 having a component different from that of the insulating film 15 is formed.

[Step shown in FIG. 10B] A conductive film such as Al is formed on the interlayer insulating film 16, and the wiring 17 is formed by patterning the conductive film.

[Step shown in FIG. 11] A protective film 18 is formed on the interlayer insulating film 16 including the wiring 17. Thus, the semiconductor device of the present embodiment is completed.

As described above, when the transistor is formed by using the STI technique, the corner of the element isolation insulating film 4 is removed when the oxide film formed on the surface of the element forming region is removed. A parasitic transistor is formed on the side wall of the parasitic transistor.
The threshold voltage of the gate voltage of the parasitic transistor can be adjusted by adjusting the ion concentration. Therefore, when a voltage is applied to the gate electrode 11, the operation of the parasitic transistor can be suppressed, and the occurrence of kink characteristics and sub-threshold leakage in the transistor can be suppressed.

In particular, in the present embodiment, the threshold value of the gate voltage of the parasitic transistor is set to be equal to or higher than the threshold value of the gate voltage of the transistor portion. Therefore, the operation of the parasitic transistor can be suitably suppressed.

However, if the carrier concentration in the parasitic channel region 13 is too high, the avalanche breakdown voltage may decrease. Therefore, even if the threshold value of the gate voltage of the parasitic transistor is not necessarily set to be equal to or higher than the threshold value of the gate voltage of the transistor portion, the operation of the parasitic transistor is suppressed while suppressing a decrease in the avalanche withstand voltage.
In order to suppress generation of kink characteristics and sub-threshold leakage, a parasitic channel region 13 is formed.
May be adjusted.

Further, in order to adjust the threshold value of the parasitic transistor, ions are implanted only into the inner surface of the side wall of the trench 2. Can be suppressed.

Since the memory transistor is formed before the other transistors, and the oxide film does not need to be removed many times, the corners of the element isolation insulating film 4 that separates the memory transistor from each other are formed. Has been reduced. Therefore, the possibility that the floating gate 110 is arranged up to the side wall of the trench 2 is small. However, even in the memory formation region A, the removal amount of the element isolation insulating film 4 is increased by forming the parasitic Tr adjusting ion implantation layer 14 on the inner surface of the side wall of the trench 2 as in the present embodiment. However, the operation of the parasitic transistor in the memory transistor can be suppressed.

(Second Embodiment) FIG. 12 is a schematic sectional view of a portion where a transistor is formed in a semiconductor device according to the present embodiment. This embodiment is different from the first embodiment in the arrangement of the ion implantation layer 14 for adjusting the parasitic Tr. Hereinafter, parts different from the first embodiment will be mainly described, and in FIG. 12, the same parts as those in FIG. 2 will be denoted by the same reference numerals and description thereof will be omitted.

In this embodiment, in order to adjust the ion concentration of the parasitic channel region 13, the parasitic Tr adjusting ion implantation layer 14 is formed in a layer substantially parallel to the surface of the substrate 1 immediately below the channel region 9 of the transistor portion. Is formed.
The parasitic Tr adjusting ion implantation layer 14 is formed at a depth such that the end of the parasitic Tr adjusting ion implantation layer 14 is disposed in the parasitic channel region 13.

Thus, by adjusting the carrier concentration of the parasitic channel region 13, the threshold value of the parasitic transistor can be adjusted and the operation of the parasitic transistor can be suppressed.

As described above, in the case where the parasitic Tr adjusting ion implantation layer 14 is formed in a layer shape with respect to the channel region 9, an insulation separation process is performed after the trench formation process, and then a process of implanting ions into the channel region 9 is performed. Substrate 1 in the same process as
May be formed by implanting ions from the surface of the substrate.

[Brief description of the drawings]

FIG. 1 is a partial top view of a transistor according to a first embodiment of the present invention.

FIG. 2 is a diagram schematically showing an AA cross section in FIG. 1;

FIG. 3 is a view schematically showing a BB section in FIG. 1;

FIG. 4 is a process drawing schematically showing a cross section of the method for manufacturing the transistor according to the first embodiment of the present invention.

FIG. 5 is a process chart showing a manufacturing step following FIG. 4;

FIG. 6 is a process chart showing a manufacturing step following FIG. 5;

FIG. 7 is a process chart showing a manufacturing process following FIG. 6;

FIG. 8 is a process diagram showing a manufacturing process following FIG. 7;

FIG. 9 is a process diagram showing a manufacturing process following FIG. 8;

FIG. 10 is a process chart showing a manufacturing process following FIG. 9;

FIG. 11 is a schematic sectional view showing a manufacturing step following FIG. 10;

FIG. 12 is a schematic sectional view of a transistor according to a second embodiment of the present invention.

FIG. 13 is a schematic sectional view of a conventional transistor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Substrate (semiconductor substrate), 2 ... Trench, 4 ... Element isolation insulating film, 7 ... Source region, 8 ... Drain region, 10 ... Gate insulating film, 11 ... Gate electrode, 14 ... Ion implantation layer for parasitic Tr adjustment, 100 ... memory gate oxide film, 110 ...
Floating gate.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (reference) H01L 27/115 H01L 27/08 321C 29/788 29/792 F term (reference) 5F032 AA35 AA44 AA45 BA01 CA17 DA24 DA43 DA53 5F048 AB01 AC03 BA01 BB05 BB16 BC06 BD04 BE03 BG01 BG13 BH07 DA25 5F083 EP02 EP23 EP49 NA01 NA08 PR37 5F101 BA01 BA29 BB05 BD14 BD36 5F140 AA16 AB03 AC32 BA01 BB13 BC06 BC07 BE07 BF01 BF04 CB42 BG04 CB04

Claims (5)

[Claims] An STI region formed having a semiconductor substrate (1), a trench (2) formed in the semiconductor substrate, and an element isolation insulating film (4) embedded in the trench. An element formation region which is a region of the semiconductor substrate which is insulated and separated by the STI region; a source region (7) and a drain region (8) formed in a surface layer of the element formation region; A gate insulating film (10, 10) formed on the surface of the semiconductor substrate between drain regions
0), and a gate electrode (11, 1) formed on the gate insulating film.
10) In the semiconductor device provided with the transistor portion having the above, a corner of the element isolation insulating film is removed at an upper portion of the trench, and the gate insulating film extends to a region where the corner is removed. An ion-implanted layer (14) is formed on a portion of the inner surface of the trench opposite to the portion on which the gate insulating film is extended, and the ion-implanted layer is formed with the gate insulating film interposed therebetween. A semiconductor device, wherein the gate electrode extends on the opposite side of the layer. 2. A threshold voltage value of the transistor portion is smaller than a threshold voltage value of a parasitic transistor formed on the sidewall of the trench and including the extended gate insulating film. The semiconductor device according to claim 1, wherein: A trench forming step of forming a trench in the semiconductor substrate; an ion implanting step of implanting ions into at least an inner surface of a side wall of the trench; An insulating isolation step of forming an STI region that insulates and separates the semiconductor substrate, and including an upper portion of a sidewall of the trench and a surface of an element forming region of the semiconductor substrate that is insulated by the STI region. Forming a gate insulating film (10, 100); and forming a gate electrode (11, 1) on the gate insulating film on the side wall of the trench and on the surface of the element formation region.
Forming a semiconductor device. 4. The method according to claim 3, wherein the ion implantation step is performed between the trench forming step and the insulation separation step, and the ion implantation is performed from a side wall of the trench. 5. The semiconductor device according to claim 3, wherein the ion implantation step is performed after the insulation separation step, and the ions are implanted from a surface of the semiconductor substrate into a layer substantially parallel to the surface. Manufacturing method.