JP2001160623A - Semiconductor device and method for manufacturing semiconductor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device for eliminating the deterioration of transistor characteristics due to a bump phenomenon. SOLUTION: An active area 101 is formed in an area decided by an element separating film 106 formed by a trench element separating method, and an MOSFET is formed in the active area 101 so that this semiconductor device can be constituted. A channel edge part 104 at the lower part of a gate 102 of the MOSFET is constituted so as to be formed outside an area 103 into which high density impurity ion is injected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a stable threshold voltage in a MOSFET formed by a trench isolation method and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, an isolation method between devices has been simplified because the process is simplified.
idation of Silicon; LOCOS) methods have been used. However, in recent high-density products, instead of the LOCOS method, an insulator such as an oxide film is buried in the trench to isolate the element from each other.
lation; STI) method has come to be used. In the STI method, unlike the LOCOS method, the formation of the element isolation film does not rely on the thermal oxidation step, so that various problems due to the thermal oxidation step can be reduced. Further, by adjusting the depth of the trench, the element isolation width can be further reduced.

FIG. 5 is a plan view of a MOS transistor. Further, in the BB cross section of FIG. 5, each manufacturing process of element isolation by the STI method is shown in FIGS.

Next, referring to these figures, a conventional ST will be described.
A method of manufacturing an element isolation by the I method will be described.

First, after a pad oxide film 305 and a silicon nitride film 306 are sequentially laminated on a semiconductor substrate 308,
Etching is performed so that the semiconductor substrate in the inactive region is exposed by the patterned photoresist 307 (FIG. 6), and the photoresist 307 is stripped (FIG. 7). Next, using the silicon nitride film 305 as a mask, the semiconductor substrate 308 is etched to a depth of about 4000 ° to form a trench 309 for element isolation (FIG. 8). After the formed trench 309 is completely buried with an insulator 310 such as several thousand angstroms of SiO ₂ (FIG. 9), chemical mechanical polishing (Chemical Mechanical Polling) is performed.
The silicon nitride film 306 is formed using an ishing (CMP) method or the like.
Until is exposed, the insulator 310 is planarized by etching (FIG. 10). Then, the silicon nitride film 30
6 and the pad oxide film 305 are sequentially removed by wet etching (FIGS. 11 and 12), whereby the element isolation film 3 is removed.
14 is formed. Subsequently, after impurity ions for adjusting the threshold voltage of the transistor are implanted into the channel formation region of the active region 301, a gate oxide film 315 and a gate electrode 302 are sequentially formed (FIG. 13). To form a region 3 with a high concentration of impurity ions.
03 to form a MOS transistor (FIG. 1
4).

[0006] Silicon nitride film 306 and pad oxide film 3
In the etching process of 05, the boundary portion 311 between the element isolation film 314 and the semiconductor substrate is etched, and a depression 312 is generated. In addition, if the adhesion between the silicon nitride film 306 and the buried insulating film 310 is poor, the depression 312 may be even larger. Further, according to the element isolation forming method using the STI method, there is a problem that a sharp edge portion 313 is formed in an active region adjacent to the trench 309. Further, in the case of an NMOS transistor, boron is used as impurity ions implanted into the active region 301 for adjusting the threshold voltage, so that the segregation effect causes a heat treatment in a later process.
There is a property that boron is easily absorbed into the element isolation film 314 which is an oxide film. Therefore, the channel edge unit 304
Has a problem that the impurity ion concentration of the channel region is lower than that of other channel regions.

When a voltage is applied to the gate electrode 302 of the transistor due to the recess 312 at the edge of the element isolation film and the sharp shape 313 at the edge of the active region, the intensity of the electric field at the channel edge 304 originally increases. Channel edge portion 30
At 4, an inversion layer is formed first. Similarly,
The reduction of the impurity ion concentration in the channel edge portion 304 also occurs first in the inversion layer. As a result, what originally should have the characteristics as shown in FIG. 15A has characteristics with a hump as shown in FIG. 15B, and the threshold voltage of such a transistor changes during operation. , Causing a current hump phenomenon in the sub-threshold region. Therefore, the leakage current of the transistor is increased and the on / off characteristics are deteriorated. Such a problem becomes more conspicuous as the channel width of the transistor is reduced, that is, as the integration degree is increased.

In order to solve such a problem, various devices have been devised in manufacturing.

That is, by applying a heat treatment before and after embedding an insulating material in a trench, a sharp edge can be rounded,
The effect can be reduced by increasing the adhesion between the trench and the buried insulating material. Further, by adding a manufacturing process for selectively providing a high-concentration p-type impurity region in a region in contact with the element isolation film, a decrease in impurity concentration at a channel edge portion can be prevented.

[0010] With the above measures, the occurrence of the hump phenomenon is suppressed as small as possible, so that the level is no problem in a digital circuit using a normal CMOS circuit. However, there are quite a few circuits that operate using a threshold voltage, and in such a circuit, even a slight hump phenomenon can affect the effects of delay, malfunction, and a decrease in output voltage level. Therefore, further measures are needed.

[0011]

SUMMARY OF THE INVENTION It is an object of the present invention to improve the above-mentioned disadvantages of the prior art, in particular, to reduce the adverse effects caused by the hump phenomenon, and to improve the problems such as delay, malfunction, and lower output voltage level. A new semiconductor device and a method for manufacturing the same are provided.

[0012]

SUMMARY OF THE INVENTION The present invention basically employs the following technical configuration to achieve the above object.

That is, in a first aspect of the semiconductor device according to the present invention, an active region is formed in a region defined by an element isolation film formed by a trench element isolation method, and an M region is formed in the active region.
In the semiconductor device in which the OSFET is formed, the channel edge portion under the gate of the MOSFET at the end of the active region is configured to be outside the region into which high-concentration impurity ions for forming source / drain regions are implanted. In a second aspect, an active region is formed in a region defined by an element isolation film formed by a trench element isolation method, and a MOSFE is formed in the active region.
T and the MOS at the end of the active region.
The channel edge portion under the gate of the FET is configured so as to be outside of a region into which high-concentration impurity ions for forming source / drain regions are implanted.
A plurality of MOSFETs connected in this way are connected in series,
It is characterized in that a constant current is applied to this circuit, and a reference voltage is taken out from this circuit.
In a third aspect, an active region is formed in a region defined by an element isolation film formed by a trench element isolation method, a MOSFET is formed in the active region, and the MOSFET at an end of the active region is formed. That the channel edge portion under the gate of the semiconductor device is outside the region into which high-concentration impurity ions for forming source / drain regions are implanted, and that a pair of MOSFETs thus configured is cross-connected to each other. In the fourth aspect, the width of the active region sandwiching the gate at the channel edge portion is set to be greater than the width of the active region sandwiching the gate at the center portion of the channel. It is characterized by being formed small.

In another aspect of the method of manufacturing a semiconductor device according to the present invention, an active region is formed in a region defined by an element isolation film formed by a trench element isolation method, and a MOSFET is formed in the active region. In the method of manufacturing a semiconductor device, when a high concentration impurity ion is implanted to form a source / drain region, the MOSFE at an end of the active region is formed.
It is characterized in that ions are implanted into the channel edge portion below the gate of T so that high-concentration impurity ions are not implanted.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In a semiconductor device according to the present invention, an active region is formed in a region defined by an element isolation film formed by a trench element isolation method, and a MOSFE is formed in the active region.
In the semiconductor device in which T is formed, a channel edge portion below a gate of the MOSFET at an end of the active region is configured to be outside a region into which high-concentration impurity ions for forming source / drain regions are implanted. It is characterized by the following.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A specific example of a semiconductor device and a method of manufacturing the same according to the present invention will be described below in detail with reference to the drawings.

FIGS. 1 to 3 show the structure of a semiconductor device according to a first embodiment of the present invention, and FIGS. An active region 101 is formed in a region defined by an element isolation film 106 formed by an isolation method, and an MO is formed in the active region 101.
In a semiconductor device in which an SFET is formed, a channel edge portion 104 below a gate 102 of the MOSFET at an end of the active region 101 is formed in a region 10 into which high concentration impurity ions for forming source / drain regions are implanted.
3 shows a semiconductor device characterized in that the semiconductor device is configured so as to be outside.

Also, an active region 101 is formed in a region defined by an element isolation film 107 formed by a trench element isolation method, a MOSFET is formed in the active region 101, and an end of the active region 101 is formed. The MOSFET
The channel edge portion 104 under the gate 102 is located outside the region 103 into which high-concentration impurity ions for forming source / drain regions are implanted, and the source / drain of the MOSFET 10 thus configured is connected. In addition, there is shown a semiconductor device in which a plurality of MOSFETs 10 connected in this way are connected in series, a constant current 11 is applied to the circuit, and a reference voltage 12 is extracted from the circuit. An active region is formed in a region defined by the element isolation film thus formed, a MOSFET is formed in the active region, and a channel edge portion below a gate of the MOSFET at an end of the active region is formed as a source region. It is configured so as to be outside the region where high-concentration impurity ions for forming the drain region are implanted. A pair of configured to MOSFET13
A semiconductor device is shown in which A and 13B are cross-connected to each other.

Hereinafter, the first example will be described in more detail.

FIG. 1 is a plan view of a MOS transistor of the present invention, FIG. 2 is a cross-sectional view taken along line AA of FIG. 1, and FIG. 3 is a circuit diagram showing an example of a circuit using the MOSFET of the present invention. is there.

The MOS transistor of the present invention comprises an active region 101, a gate electrode 102, and a high-concentration impurity ion implantation region 103 for forming a source / drain. An element isolation film 106 is formed around the active region 101 by using the STI method. After that, a gate oxide film 107 and a gate electrode 102 are sequentially formed. continue,
A source / drain is formed in the high-concentration impurity ion-implanted region 103 using the gate electrode 102.
Set to be outside of. The positional accuracy of the ion-implanted region is not so good, and the variation is x0.
Then, the impurity ion-implanted region 103 is at least x0 + α from the channel edge 104 (a margin that does not allow the flannel edge to enter the impurity ion-implanted region even if it varies by x0 in the channel edge direction).
Set inside from. This description is for a single drain structure.

At present, generally, in order to improve the breakdown voltage and the reliability, a lightly doped drain (LDD) structure is used for a MOS transistor. In this case, after the gate electrode 102 is formed, low-concentration impurity ions are implanted into the entire surface of the wafer, and the n − region is formed in the active region 101.
After being formed on the entire surface, an n + source / drain region 105 is formed using the gate electrode 102, and the other region becomes the n− region 108 (FIG. 2B). Also in this case, the positional accuracy of the ion-implanted region is not so good.
From the high-concentration impurity ion implantation region 103 necessary to avoid the effect of the hump phenomenon caused by
Assuming that the distance calculated from the resistance values up to 4 is x1, the impurity ion implanted region 103 is set at (x0 + x1) or more inside the channel edge 104 from the channel edge 104.

When a MOS transistor having a single drain structure is used (FIG. 2A), the channel edge 10
4 exists outside the operation region of the MOS transistor, so that the hump phenomenon does not occur.

When the MOS transistor having the LDD structure is used (FIG. 2B), the channel edge portion 104 is n-type.
Although it becomes a part of the region 108 and has an electrical connection relationship with the n + region 105, the layer resistance of the n + region 105 is generally several tens to several hundreds ohms, while the n− region 1
08 has a thickness of several thousand ohms, so that M is not easily affected by a change in transistor characteristics due to the hump phenomenon.
An OS transistor can be made.

FIG. 3 shows an example of a circuit which is effective by using a MOS transistor which does not cause such a hump phenomenon or which is less affected by a change in transistor characteristics due to a decrease in hump.

FIG. 3A shows a circuit for generating a reference voltage, which directly uses the value of the threshold voltage Vt. The reference voltage is based on the number of MOS transistors 10 and the threshold voltage Vt.
Multiplied by In the case of a conventional circuit, a change in the transistor characteristics due to the hump characteristic also affects the output reference voltage, which adversely affects the characteristics of a circuit using this reference voltage.

FIG. 3B shows a cross-coupled amplifier which is well known as a sense amplifier for a DRAM. However, if the threshold voltages of the paired transistors 13A and 13B greatly vary due to the hump characteristic, the operation will be described. There is a possibility that a malfunction may occur due to delay and inversion.

(Second Specific Example) FIGS. 4A and 4B show a second specific example of the present invention. In these figures, the active region 101 sandwiching the gate at the center of the channel is shown.
The width 101a of the active region 101 with the gate 102 interposed therebetween at the channel edge portion.
Is shown in which a semiconductor device is formed small.

Hereinafter, the second specific example will be described in more detail.

In a first embodiment, the present invention is applied to a general MOS transistor.
This is applied to a rectangle which is the shape of a transistor.
In this case, the effective size of the transistor is not determined by the shape surrounded by the element isolation film 106, but
Although it is determined by the high-concentration impurity ion implantation region 103, the position accuracy of the ion implantation region is not so good, and an error x0 occurs. Thus, the smaller the transistor size, the greater the effect.

In the second embodiment, the variation in the transistor size is significantly reduced as compared with the first embodiment, and at the same time, the influence of the change in transistor characteristics due to the hump phenomenon is also reduced. Is shown in FIG.

Constant region x including channel edge portion 104
2, the distance x3 between the gate electrode 102 and the element isolation film 106 is made smaller than the normal region, and the MOS is formed so that the high-concentration impurity ion-implanted region 103 overlaps the error x0 or more and does not include the channel edge portion 104. A transistor is formed.

In such a configuration, the constant region x2 including the channel edge portion 104 has a higher resistance than the first specific example. Therefore, even if the high-concentration impurity ion-implanted region 103 varies, the set transistor size is not changed. And the resistance from the high-concentration impurity ion-implanted region 103 to the channel edge 104 is also high, so that the effect of the change in transistor characteristics due to the hump phenomenon can be further reduced.

[0034]

Since the semiconductor device and the method of manufacturing the same according to the present invention are constructed as described above, deterioration of transistor characteristics due to the bump phenomenon can be improved.

[Brief description of the drawings]

FIG. 1 is a plan view of a first specific example of a semiconductor device according to the present invention.

FIG. 2 is a sectional view taken along line AA of FIG.

FIG. 3 is a diagram illustrating a circuit example using the semiconductor device of the present invention.

FIG. 4 is a plan view of a second specific example.

FIG. 5 is a plan view of a conventional example.

FIG. 6 is a view showing a manufacturing process of a conventional example.

FIG. 7 is a view showing a manufacturing step following FIG. 6;

FIG. 8 is a view illustrating a manufacturing step following FIG. 7;

FIG. 9 is a view showing a manufacturing step following FIG. 8;

FIG. 10 is a view showing a manufacturing step following FIG. 9;

FIG. 11 is a view showing a manufacturing step following FIG. 10;

FIG. 12 is a view showing a manufacturing step following FIG. 11;

FIG. 13 is a view showing a manufacturing step following FIG. 12;

FIG. 14 is a view showing a manufacturing step following FIG. 13;

15A is a characteristic diagram of a transistor without a bump, and FIG. 15B is a characteristic diagram of a transistor with a bump.

[Explanation of symbols]

 10, 13A, 13B MOSFET 11 Constant current power supply 12 Reference voltage 101 Active region 102 Gate electrode 103 High-concentration impurity ion implantation region 104 Channel edge portion 105 Source / drain region (n + region) 106 Element isolation film 107 Gate oxide film 108 n− region

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F038 BB02 5F040 DC01 EA08 EA09 EF01 EF02 EK01 EK05 FB02 FB04 FC10 5F083 AD00 GA11 GA30 LA03 NA01 PR36

Claims (5)

[Claims] 1. A semiconductor device in which an active region is formed in a region defined by a device isolation film formed by a trench device isolation method, and a MOSFET is formed in the active region, wherein the MOSFET at an end of the active region is provided. Wherein the channel edge portion below the gate is outside the region into which high-concentration impurity ions for forming source / drain regions are implanted. 2. An active region is formed in a region defined by an element isolation film formed by a trench element isolation method, a MOSFET is formed in the active region, and a gate of the MOSFET at an end of the active region is formed. The lower channel edge portion is configured to be outside a region where high concentration impurity ions for forming source / drain regions are implanted,
The source and the drain of the MOSFET thus configured are connected, a plurality of MOSFETs connected in this way are connected in series, a constant current is applied to the circuit, and a reference voltage is extracted from the circuit. Semiconductor device. 3. An active region is formed in a region defined by an element isolation film formed by a trench element isolation method, a MOSFET is formed in the active region, and the MOSFET at an end of the active region is formed. That the channel edge portion under the gate of the semiconductor device is outside the region into which high-concentration impurity ions for forming source / drain regions are implanted, and that a pair of MOSFETs thus configured is cross-connected to each other. Characteristic semiconductor device. 4. The width of the active region sandwiching the gate at the channel edge portion is smaller than the width of the active region sandwiching the gate at a central portion of the channel. Item 4. The semiconductor device according to any one of Items 1 to 3. 5. A method for manufacturing a semiconductor device in which an active region is formed in a region defined by an element isolation film formed by a trench element isolation method, and a MOSFET is formed in the active region. Forming a source / drain region by implanting ions into a channel edge portion below a gate of the MOSFET at an end of the active region so as not to implant high-concentration impurity ions. Method.