KR20160002352A - Thin film transistor of display device - Google Patents

Abstract

The present invention relates to a thin film transistor of a display device, which can decrease screen failure by reducing leakage of current due to a hump. The thin film transistor of a display device according to an embodiment of the present invention comprises an active layer and a gate electrode by having a gate insulating film disposed therebetween. The gate electrode is disposed so that the gate electrode is divided into multiple wires to be overlapped with the active layer. The active layer comprises one or multiple channel regions disposed between a source electrode and a drain electrode; a dummy region whose length is elongated at an edge part of the channel region; and multiple link regions which are formed between the multiple channel regions to connect the multiple channel regions as one pattern. The multiple link regions are disposed to be overlapped with a part corresponding to a space between the multiple wires.

Description

[0001] THIN FILM TRANSISTOR OF DISPLAY DEVICE [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor, and more particularly, to a thin film transistor of a display device capable of reducing a leakage current due to a hump to reduce a screen defect.

In the organic light emitting diode (OLED), an organic light emitting layer is formed between two electrodes (an anode electrode and a cathode electrode). Electrons and holes are injected from the two electrodes into the organic light emitting layer to generate an exciton resulting from the combination of electrons and holes. Further, it is a device using the principle that light is generated when the generated excitons fall from the excited state to the ground state.

In the organic light emitting display device, a plurality of pixels are arranged in a matrix form. Each pixel of the organic light emitting display device includes an organic light emitting diode (OLED) emitting light by an input data current Ioled, and a pixel circuit (PC) for driving the organic light emitting diode (OLED). In addition, a plurality of lines for supplying driving power and signals to the organic light emitting diode (OLED) and the pixel circuit (PC) are formed.

An organic light emitting diode (OLED) and a pixel circuit are constituted by the plurality of pixels, and the organic light emitting diode (OLED) of each pixel is emitted according to an input image signal to display a screen.

Here, the pixel circuit PC includes a scan TFT, a sensing TFT, a driving TFT, and a storage capacitor Cst. The plurality of lines include a data line DL, a gate line GL, a driving power supply line PL, a sense signal line SL, and a reference power supply line RL.

1 shows a gate driver for supplying a scan signal to pixels of an organic light emitting display device, and shows one scan circuit.

Referring to FIG. 1, a scan circuit of a gate driver generates a scan signal and supplies a scan signal to a scan TFT of a pixel circuit through a gate line.

Here, among the buffer TFTs, the full-up TFT outputs a high voltage (gate high voltage) to the gate line, and the pull-down TFT T1 outputs a low voltage (gate low voltage) to the gate line. The switching TFT T2 is a reset TFT for erasing the voltage charged in the Q node to a low voltage (for example, ground or VGL).

When the threshold voltage Vth of the switching TFT T2 is lowered, the off current Ioff is increased, so that the voltage of the Q node is lowered and the output voltage Vgout is lowered. In addition, when the threshold voltage Vth of the pull-down TFT (T1) is lowered, the off current (Ioff) is increased and accordingly the output voltage (Vgout) to be outputted to the VGH level is lowered. Here, the output voltage Vgout means a high voltage outputted when the pull-up TFT is turned on.

That is, when the pull-up TFT is turned on, the output voltage Vout must be output to the VGH level, but the output voltage Vout becomes lower than the normal voltage due to the off current Ioff of the pull-down TFT T1 and the switching TFT T2 do. As described above, when the output voltage Vgout of the scan circuit is lowered, the switching TFT of the pixel circuit is not normally turned on and a screen failure occurs.

2A is a diagram showing a plan layout of a pull-down TFT configured in a scan circuit, FIG. 2B is a diagram showing a plan layout of a reset TFT configured in a scan circuit, and FIG. 2C is a diagram showing a plan layout of a driving TFT configured in a pixel circuit . FIG. 3 is a view showing a pull-down TFT and a reset TFT cross-section along a line A1-A2 shown in FIG. 2A and FIG. 2B, and a problem that a hump is generated in a pull-down TFT and a reset TFT. The pull-down TFT and the reset TFT are formed in a coplanar top gate type. The cross section of the pull-down TFT and the reset TFT is similar to that of the driving TFT, so that the cross section of the driving TFT is not shown.

2 (A), the pull-down TFT T1 is formed to have a larger area than other TFTs, the gate electrode 2 is formed in a two-wire structure, and the active layer 1 is formed in the gate electrode 2) to form a multi-channel. The channel region of the active layer 1 is in contact with the source electrode 3 and the drain electrode 4.

As shown in Fig. 2B, the switching TFT T2 is formed in a smaller area than the pull-down TFT (T1), and the gate electrode 2 is formed in a double wiring structure in order to form multi-channel . The active layer 1 is formed in one pattern and is contacted with the source electrode 3 and the drain electrode 4. [

As shown in Fig. 2 (C), the driving TFT of the pixel circuit has the gate electrode 2 formed in a single wiring structure, the active layer 1 formed in one pattern, and the source electrode 3 and the drain And is then brought into contact with the electrode 4.

As shown in FIG. 3, a gate insulating layer 5 is formed between the active layer 1 and the gate electrode 2. Parasitic TFTs are formed because the left and right edge portions of the active layer 1 are tapered. That is, the tapered shapes of the left and right edge portions of the active layer 1 overlap with the gate electrodes 2 to form parasitic TFTs.

Although the cross section of the driving TFT is not shown in Fig. 3, since the left and right edge portions of the active layer 1 are tapered in the same or similar manner as the pull down TFT (T1) and the switching TFT (T2) Can be formed.

A channel is formed in a region where the gate electrode 2 and the active layer 1 overlap. Here, the threshold voltages Vth1 and Vth3 of the parasitic TFT formed in the left and right edge portions of the active layer 1 are formed to be lower than the threshold voltage Vth2 of the channel portion. As described above, when the threshold voltages Vth1 and Vth3 are lowered by the parasitic TFTs, a strong electric field is formed in the left and right edge portions of the active layer 1.

It is necessary to linearly increase the current in the interval of 0 [V] to 3 [V] as shown in the transfer curve characteristic showing the change of the drain current according to the gate voltage change, but a strong electric field is formed in the edge region of the active layer A hump is generated in which the current is changed in a non-linear manner. As described above, when the hump is generated, the on and off time delays of the TFT become longer and the switching characteristics are lowered.

As described above, there is a problem that a leakage current (or an off current) is generated due to the hump along the parasitic TFTs of the left and right edge portions of the active layer 1, and the output voltage Vgout of the scan circuit is lowered. Further, there is a problem that the switching TFT of the pixel circuit does not normally operate (turn on and turn off), resulting in screen failure.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is a technical object to provide a TFT capable of reducing leakage current due to a hump.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned problems, and it is an object of the present invention to prevent a display failure of a display device by preventing a fall of an output voltage Vgout of a scan circuit due to a hump of a TFT constituted in a scan circuit of a gate driver do.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is a technical object to prevent a leakage current (or an off current) due to a hump of a driving TFT constituted in a pixel circuit, thereby preventing a display failure of the display device.

Other features and advantages of the invention will be set forth in the description which follows, or may be learned by those skilled in the art from the description and the claims.

A thin film transistor of a display device according to an embodiment of the present invention includes an active layer and a gate electrode disposed with a gate insulating film therebetween. The gate electrode is branched to a plurality of wirings and arranged so as to overlap with the active layer. Wherein the active layer has one or a plurality of channel regions disposed between the source electrode and the drain electrode, a dummy region having a length elongated at an edge portion of the channel region, And a plurality of link regions formed between the plurality of channel regions and connecting the plurality of channel regions in one pattern, wherein the plurality of link regions overlap each other in a portion corresponding to a space between the plurality of lines, Area.

The thin film transistor according to the embodiment of the present invention can prevent the occurrence of the hump and reduce the leakage current.

The present invention prevents the occurrence of a hump by changing the active layer pattern of the TFT configured in the scan circuit of the gate driver, thereby preventing the fall of the output voltage (Vgout) of the scan circuit, thereby preventing a display failure of the display device .

The present invention prevents generation of a leakage current (or an off current) due to a hump by changing the active layer pattern of the driving TFT formed in the pixel circuit, thereby preventing a display failure of the display device.

Other features and effects of the present invention may be newly understood through the embodiments of the present invention in addition to the features and effects of the present invention mentioned above.

1 shows a gate driver for supplying a scan signal to pixels of an organic light emitting display device, and shows one scan circuit.
2A is a diagram showing a plane layout of a pull-down TFT configured in a scan circuit.
2B is a diagram showing a plane layout of the reset TFT configured in the scan circuit.
2C is a diagram showing a plane layout of a driving TFT configured in a pixel circuit.
FIG. 3 is a cross-sectional view of a pull-down TFT and a reset TFT according to the line A1-A2 shown in FIG. 2A and FIG. 2B, and a problem in which a hump is generated in a pull-down TFT and a reset TFT.
4 is a view schematically showing an organic light emitting display device to which a TFT according to an embodiment of the present invention is applied.
5 is a view showing one pixel among a plurality of pixels arranged in an organic light emitting display device.
6 shows a planar layout of a TFT according to the first embodiment of the present invention, and is a diagram showing a plane layout of a pull-down TFT among buffer TFTs configured in a scan circuit of a gate driver.
Fig. 7 shows a planar layout of a TFT according to a second embodiment of the present invention, and is a view showing a plane layout of a pull-down TFT among buffer TFTs configured in a scan circuit of a gate driver.
8A is a cross-sectional view of a pull-down TFT along lines B1-B2 and line C1-C2 shown in FIG.
8B is a cross-sectional view of the pull-down TFT along lines B1-B2 and line D1-D2 shown in FIG.
Fig. 9 shows a planar layout of a TFT according to a third embodiment of the present invention, which is a diagram showing a planar layout of a switching TFT constituted in a switching TFT or a pixel circuit constituted in a scanning circuit of a gate driver.
Fig. 10 shows a planar layout of a TFT according to a fourth embodiment of the present invention, which is a diagram showing a planar layout of a switching TFT constituted in a switching TFT or a pixel circuit constituted in a scanning circuit of a gate driver.
11A is a cross-sectional view of a switching TFT or a switching TFT configured in a pixel circuit configured in a scan circuit according to the E1-E2 line shown in FIG.
11B is a cross-sectional view of a switching TFT configured in a scan circuit according to the line F11-F2 shown in FIG. 10 or a switching TFT configured in a pixel circuit.
12 is a view showing an improvement of the output characteristics of the TFT and an effect of improving the hump by changing the pattern of the active layer of the TFT according to the first to fourth embodiments of the present invention.
Fig. 13 shows a planar layout of a TFT according to a fifth embodiment of the present invention, and is a diagram showing a planar layout of a driving TFT configured in a pixel circuit.
14 is a cross-sectional view of a driving TFT taken along a line G1-G2 shown in Fig.
15 is a diagram showing a channel formed in the active layer and a switching TFT (reset TFT) of a scan circuit or a switching TFT of a pixel circuit in a pull-down TFT or a scan circuit of a scan circuit formed in a single gate (top gate) structure.
FIG. 16 is a diagram showing an effect of improving the output characteristics of the driving TFT and improving the hump by changing the pattern of the active layer of the driving TFT according to the fifth embodiment of the present invention.
FIG. 17 shows a planar layout of a TFT according to a sixth embodiment of the present invention, and is a diagram showing a plane layout of a pull-down TFT among buffer TFTs configured in a scan circuit of a gate driver.
18A is a view showing a gate electrode in the plan layout of the pull-down TFT shown in FIG.
18B is a view showing the active layer among the plane layout of the pull-down TFT shown in FIG.
18C is a view showing a source electrode and a drain electrode in the plane layout of the pull-down TFT shown in FIG.
Fig. 19A is a view showing a cross section along a line I1-I2 shown in Fig. 17;
Fig. 19B is a cross-sectional view taken along the line I3-I4 shown in Fig. 17;
20 shows a planar layout of a TFT according to a seventh embodiment of the present invention, in which a pull-down TFT of a scan circuit is formed in a double gate structure and a plane showing a plurality of channels formed in the active layer.
21A is a cross-sectional view of a pull-down TFT of a scan circuit according to J1-J2 line shown in FIG.
21B is a cross-sectional view of a pull-down TFT of a scan circuit according to J3-J4 line shown in FIG.
FIG. 22 is a diagram showing an improvement of the output characteristics of the pull-down TFT and an improvement of the hump by changing the pattern of the active layer of the pull-down TFT according to the seventh embodiment of the present invention.

Hereinafter, a thin film transistor of a display device of the present invention will be described with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. To fully disclose the scope of the invention to a person skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. In the case where the word 'includes', 'having', 'done', etc. are used in this specification, other parts can be added unless '~ only' is used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In describing embodiments of the present invention, when it is described that a structure (electrode, line, wiring layer, contact) is formed "over, on, under, or under" another structure, But also to the case where a third structure is interposed between these structures.

In the case of a description of a temporal relationship, for example, if the temporal relationship is described by 'after', 'after', 'after', 'before', etc., May not be continuous unless they are not used.

The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

It is to be understood that each of the features of the various embodiments of the present invention may be combined or combined with each other, partially or wholly, technically various interlocking and driving, and that the embodiments may be practiced independently of each other, It is possible.

FIG. 4 is a view schematically showing an organic light emitting display device to which a TFT according to an embodiment of the present invention is applied, and FIG. 5 is a view showing one pixel among a plurality of pixels arranged in the organic light emitting display device.

Referring to FIGS. 4 and 5, an organic light emitting display device to which a TFT according to an exemplary embodiment of the present invention is applied includes a display panel and a driving circuit for driving the display panel.

The driving circuit portion includes a data driver, a gate driver, a timing controller, and a memory.

The timing controller operates the data driver and the gate driver in the driving mode based on the timing synchronization signal (TSS) to display the input image. The timing controller operates the data driver and the gate driver in the sensing mode based on the timing synchronization signal TSS so that the threshold voltage / mobility sensing of the driving TFT DT of each pixel is performed.

The gate driver generates a scan signal (scan) and a sense signal (sense) in accordance with a gate control signal (GCS) supplied from the timing controller. Outputs the scan signal to the gate line GL, and outputs the generated sense signal to the sense signal line SL. For example, the gate driver generates a scan signal (scan drive signal) of a gate-on voltage level every one horizontal period based on the gate control signal GCS. The gate driver sequentially supplies the generated scan signal (scan) to the plurality of gate lines GL.

Such a gate driver may be formed on a substrate of a display panel in a GIP (gate in panel) manner. A GIP type gate driver is formed in a non-display region on the substrate. A gate driver may be formed in the non-display area on the left or right side of the display panel by the GIP method. A gate driver may be formed in the non-display area on the left and right sides of the display panel by the GIP method.

The scan signal (scan, gate drive signal) has a gate-on voltage level during the data charging period of each pixel P. On the other hand, the scan signal (scan) has a gate-off voltage level during the light emission period of each pixel P. The gate driver may be a shift register that sequentially outputs a scan signal (scan). The gate driver is connected to each of the plurality of driving power supply lines PL1 to PLm and supplies the driving power supply voltage VDD to the plurality of driving power supply lines PL1 to PLm. When the gate driver outputs the driving power supply voltage VDD, the plurality of driving power supply lines PL1 to PLm may be arranged in the horizontal direction within the display panel. 4, a plurality of driving power lines PL1 to PLm are arranged in the horizontal direction within the display panel.

The data driver converts the input image data into a data voltage (Vdata) and supplies the data voltage to the data line DL. At this time, the initial compensation data and the real-time compensation data are reflected and a data voltage (Vdata) according to the image data reflecting the compensation data stored in the memory is generated.

In the above description, the gate driver outputs the driving power supply voltage VDD. However, the present invention is not limited to this, and the driving power supply voltage VDD may be output from the data driver. In this case, the data driver is connected to each of the plurality of driving power supply lines PL1 to PLm, and the driving power supply line VDD can be supplied to the plurality of driving power supply lines PL1 to PLm. When the driving power VDD is outputted from the data driver, the plurality of driving power lines PL1 to PLm may be arranged in the vertical direction within the display panel.

The display panel includes a plurality of gate lines GL, a plurality of sensing signal lines SL, a plurality of data lines DL, a plurality of driving power supply lines PL, and a plurality of reference voltage lines RL. A plurality of pixels P are defined by these lines GL, SL, DL, PL, and RL. The plurality of pixels P include an organic light emitting diode (OLED) and a pixel circuit (PC) for causing the organic light emitting diode (OLED) to emit light.

Each of the plurality of pixels P may be either a red pixel, a green pixel, a blue pixel, or a white pixel. When one unit pixel for displaying an image is composed of four colors, a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel ) Can be constituted by one unit pixel.

The plurality of gate lines GL and the plurality of sensing signal lines SL may be formed in parallel in the first direction (e.g., the horizontal direction) in the display panel. At this time, a scan signal (gate drive signal) is applied from the gate driver to the gate line GL. A sensing signal sense is applied to the sensing signal line SL from the gate driver.

A plurality of driving power supply lines PL may be formed in parallel with the gate lines GL. Voltage driving power supply VDD to the pixel P through the driving power supply line PL.

The plurality of data lines DL may be formed in a second direction (e.g., vertical direction) so as to intersect the plurality of gate lines GL and the plurality of sensing signal lines SL. At this time, the data voltage (Vdata) is supplied from the data driver to the data line DL. The data voltage Vdata has a voltage level to which a compensation voltage corresponding to the shift of the threshold voltage Vth of the driving TFT DT of the pixel P is added

A plurality of reference voltage lines RL are formed in parallel with each of the plurality of data lines DL. The reference voltage line RL may be selectively supplied with a reference voltage or a sensing precharging voltage from the data driver.

5, the pixel circuit PC of each pixel P includes a first switching TFT ST1, a second switching TFT ST2, a driving TFT DT, and a storage capacitor Cst . Here, the TFTs constituted in the TFTs ST1, ST2 and DT constituted in the pixel circuit and the scan circuit of the gate driver can be formed in N type or P type in which the active layer is formed of LTPS (Low-Temperature Poly Silicon). However, the present invention is not limited to this, and the TFTs of the pixel circuit and the TFTs of the scan circuit such as an amorphous silicon (a-Si) TFT, a poly-Si TFT, an Oxide TFT, .

The first switching TFT ST1 is turned on according to the scan signal of the gate-on voltage level supplied to the gate line GL. When the first switching TFT ST1 is turned on, the data voltage Vdata supplied to the data line DL is supplied to the gate electrode of the driving TFT DT.

The second switching TFT ST2 is turned on according to the sensing signal sense of the gate-on voltage level supplied to the sensing signal line SL. When the second switching TFT ST2 is turned on, a display reference voltage or a sensing precharging voltage supplied to the reference voltage line RL is supplied to the node between the driving TFT DT and the OLED.

The driving TFT DT controls the amount of current flowing from the first driving power supply VDD to the organic light emitting diode OLED by being turned on by the voltage charged in the capacitor Cst every emission period.

The organic light emitting diode OLED emits light with a data current Ioled supplied from the driving TFT DT of the pixel circuit PC to emit monochromatic light having a luminance corresponding to the data current Ioled.

6 shows a planar layout of a TFT according to the first embodiment of the present invention, and is a diagram showing a plane layout of a pull-down TFT among buffer TFTs configured in a scan circuit of a gate driver. 8A is a cross-sectional view of a pull-down TFT along lines B1-B2 and line C1-C2 shown in FIG. 6. FIG.

Referring to Figs. 6 and 8A, the TFT 100 according to the first embodiment of the present invention can be applied to buffer TFTs (pull-up TFT and pull-down TFT) of a scan circuit. Hereinafter, one example in which the TFT 100 according to the first embodiment of the present invention is applied to a pull-down TFT (T1 in FIG. 1) among the buffer TFTs of the scan circuit will be described.

The pull-down TFT of the scan circuit is formed in a large area compared with general switching TFTs to withstand the deterioration due to high voltage and long driving. In the TFT 100 according to the first embodiment of the present invention, the gate electrode 120 is formed in a two-wire structure in order to form multi-channels, and the active layer 110 is patterned so that a plurality of channels are formed.

The TFT 100 according to the first embodiment of the present invention is formed in a top gate structure. An active layer 110 is formed on a substrate, and a gate insulating layer 150 is formed on the active layer 110. A gate electrode 120 is formed on the gate insulating layer 150.

The gate electrode 120 is branched from the gate line to two wirings and is formed long in one direction. The source electrode 130 is disposed on the lower side of the gate electrode 120 on the plane and the drain electrode 140 is disposed on the upper side of the gate electrode 120. However, the present invention is not limited to this, and the drain electrode 140 may be disposed on the lower side of the gate electrode 120 in a plan view, and the source electrode 130 may be disposed on the upper side of the gate electrode 120.

  The active layer 110 is formed so as to overlap with the gate electrode 120 and the channel region of the active layer 110 is in contact with the source electrode 130 and the drain electrode 140. The gate electrode 120 and the active layer 110 do not overlap each other, and the gate electrode 120 and the active layer 110 are partially overlapped.

Here, the source electrode 130 and the drain electrode 140 are disposed at both ends of the active layer 110. The source electrode 130 is connected to the data line through the contact metal formed in the contact hole and the drain electrode 140 is connected to the anode electrode (or signal line) of the OLED.

The active layer 110 includes a plurality of channel regions 112, a dummy region 114 formed in the left and right edge portions of the channel region 112, and a plurality of link regions 116 ).

Here, the active layer 110 may be formed of LTPS (Low-Temperature Poly Silicon). However, the present invention is not limited thereto, and the active layer 110 may be formed of amorphous silicon (a-Si), polysilicon (poly-Si), oxide, or organic material.

A plurality of channel regions 112 are overlapped with the gate electrode 120 to form a multi-channel region, and a channel region is disposed between the source electrode 130 and the drain electrode 140.

A plurality of link regions 116 are disposed between the plurality of channel regions 112 to connect the plurality of channel regions 112. That is, the plurality of channel regions 112 are connected by a plurality of link regions 116 in one pattern.

Each of the plurality of link regions 116 includes a slit, and the slit is disposed so as to overlap the portion corresponding to the space between the two wirings of the gate electrode 120.

When forming the active layer 110, a plurality of channel regions 112 and a plurality of link regions 116 are formed by patterning a conductive transparent material (e.g., ITO) layer. Therefore, the plurality of channel regions 112 and the plurality of link regions 116 are formed of the same material.

Here, the width of each of the plurality of link regions 116 is formed smaller than the width of each of the two wirings of the gate electrode 120 in the longitudinal direction.

The dummy region 114 extends from the left and right edge portions of the channel region 112 to beyond the end of the gate electrode 120 to the outside. That is, the dummy region 114 protrudes from the left and right edge portions of the channel region 112 and is formed to the left and right outlines of the channel region 112. As a result, the left and right edge portions of the active layer 110 are not overlapped with the gate electrode 120.

The end of the dummy region 114 is positioned at a predetermined distance from the edge of the gate electrode 120. The end of the dummy region 114 is located outside the gate electrode 120. That is, the edge of the gate electrode 120 is arranged at a predetermined distance from the end of the dummy region 114.

For example, the dummy region 114 protrudes to the outer periphery of the gate electrode 120 by a length W2 corresponding to 10 to 30% of the width W1 of the gate electrode 120. That is, the end of the dummy region 114 is located from the edge of the gate electrode 120 with an interval of W2 as long as 10 to 30% of the width W1 of the gate electrode 120.

As another example, the dummy region 114 may be formed in the outer periphery of the gate electrode 120 by a length W2 corresponding to 10 to 30% of the width W1 of the portion where the gate electrode 120 and the active layer 110 are overlapped. . That is, the gate electrode 120 and the active layer 110 are separated from the edge of the gate electrode 120 by an interval of W2 corresponding to 10 to 30% of the width W1 of the overlapping portion, 114 are positioned.

The length of the protrusion of the dummy region 114 is set in consideration of the overlap margin between the gate electrode 120 and the active layer 110. The width of the portion where the gate electrode 120 and the active layer 110 are overlapped with each other is equal to or greater than the width W1 of the width W1 of the gate electrode 120, (W2), which is a length corresponding to 10 to 30% of the total length (W2).

The protruding length of the dummy region 114 is set to be too small (for example, less than 10% of the width W1 of the gate electrode 120 or the width of the overlapping portion of the gate electrode 120 and the active layer 110) (Less than 10% of the width W1), the dummy region 114 may not protrude to the outer periphery of the gate electrode 120. That is, the dummy region 114 may not be normally formed.

On the other hand, if the protruding length of the dummy region 114 is set too large (for example, more than 30% of the width W1 of the gate electrode 120 or the gate electrode 120 is overlapped with the active layer 110) (More than 30% of the width W1 of the portion), the total size of the TFT is increased due to the increase of the size of the dummy region 114. [ Therefore, it is possible to eliminate the problem that all the TFTs can not be designed in the limited space, that is, the lack of the design space.

Therefore, in consideration of the design and manufacturing margin of the TFT, the inventors of the present application have found that the dummy region 114 is formed in the gate electrode 120 by a length W2 corresponding to at most 30% of the width W1 of the gate electrode 120, As shown in Fig. The inventors of the present application have found that by considering the design and fabrication margin of the TFTs, the inventors of the present application found that, by considering the design and manufacturing margin of the TFT, the dummy gate electrode 120 and the active layer 110 are stacked, The region 114 is set so as to protrude to the outer periphery of the gate electrode 120.

As shown in FIG. 8A, a gate insulating layer 150 is formed on the left and right ends of the active layer 110. However, the gate electrode 120 does not exist above the left and right end portions of the active layer 110 (end portions of the dummy region 114). Therefore, since the edge portion of the active layer 110 and the gate electrode 120 are not overlapped, parasitic TFTs due to superposition of the gate electrode and the edge portion of the active layer are not formed in the conventional art. Even if a parasitic TFT is formed, it is formed very small.

Thus, it is possible to prevent or improve the hump caused by the formation of the parasitic TFT in the buffer TFT of the scan circuit, thereby improving the output characteristics of the buffer TFT of the scan circuit. If the output characteristics of the buffer TFT of the scan circuit are improved, display quality can be improved by preventing display device screen failure.

Fig. 7 shows a planar layout of a TFT according to a second embodiment of the present invention, and is a view showing a plane layout of a pull-down TFT among buffer TFTs configured in a scan circuit of a gate driver. Fig. 8B is a view showing a section of a pull-down TFT along lines B1-B2 and line D1-D2 shown in Fig. 7;

7 and 8B, the TFT 100 according to the second embodiment of the present invention has a structure in which the gate electrode 120 is formed in a two-wire structure in order to form multi-channels, (110) is patterned.

The gate electrode 120 is branched from the gate line to two wirings and is formed long in one direction. The source electrode 130 is disposed on the lower side of the gate electrode 120 on the plane and the drain electrode 140 is disposed on the upper side. The active layer 110 is disposed so as to overlap with the gate electrode 120 and the active layer 110 is contacted with the source electrode 130 and the drain electrode 140. However, the present invention is not limited to this, and the drain electrode 140 may be disposed on the lower side of the gate electrode 120 in a plan view, and the source electrode 130 may be disposed on the upper side of the gate electrode 120.

A plurality of channel regions 112 of the active layer 110 are overlapped with the gate electrode 120 to form a plurality of channels and a plurality of channel regions 112 are formed between the source electrode 130 and the drain electrode 140 . The gate electrode 120 and the active layer 110 do not overlap each other, and the gate electrode 120 and the active layer 110 are partially overlapped.

A plurality of link regions 116 of the active layer 110 are formed between the channel regions 112 to connect the plurality of channel regions 112. That is, the plurality of channel regions 112 are connected by a plurality of link regions 116 in one pattern. At this time, the width of each of the plurality of link regions 116 is formed to be larger than the width of each of the two wirings of the gate electrode 120 in the longitudinal direction.

Each of the plurality of link regions 116 includes a slit, and the slit is disposed so as to overlap the portion corresponding to the space between the two wirings of the gate electrode 120.

The dummy region 114 of the active layer 110 starts from the left and right edge portions of the channel region 112 and extends beyond the end of the gate electrode 120 to the outside. That is, the dummy region 114 protrudes from the left and right edge portions of the channel region 112, and the end of the dummy region 114 is disposed on the left and right outer edges of the channel region 112. Thus, the left and right edge portions (dummy region 114) of the active layer 110 are not overlapped with the gate electrode 120.

The end of the dummy region 114 is positioned at a predetermined distance from the edge of the gate electrode 120. The end of the dummy region 114 is located outside the gate electrode 120.

For example, the dummy region 114 protrudes to the outer periphery of the gate electrode 120 by a length W2 corresponding to 10 to 30% of the width W1 of the gate electrode 120. That is, the end of the dummy region 114 is located at an interval of W2 as long as 10 to 30% of the width W1 of the gate electrode 120 from the edge of the gate electrode 120.

As another example, the dummy region 114 may be formed in the outer periphery of the gate electrode 120 by a length W2 corresponding to 10 to 30% of the width W1 of the portion where the gate electrode 120 and the active layer 110 are overlapped. . That is, a distance of W2 from the edge of the gate electrode 120 corresponding to 10 to 30% of the width W1 of the portion where the gate electrode 120 and the active layer 110 are overlapped, 114 are positioned.

The length of the dummy region 114 protruding from the channel region 112 is not limited to 10 to 30% of the width W1 of the gate electrode 120. However, the inventors of the present application have considered that the dummy region 114 has a length corresponding to 30% of the width of the gate electrode 120 in consideration of the design and manufacturing process margin of the pull-down TFT constituting the scan circuit, As shown in Fig.

The length of the dummy region 114 protruding from the channel region 112 is not limited to 10 to 30% of the width W1 of the portion where the gate electrode 120 and the active layer 110 overlap. However, the inventors of the present application have found that, considering the design and fabrication process margin of the pull-down TFT constituting the scan circuit, the dummy region 114 (W2) is formed by a length W2 corresponding to at most 30% of the width W1 of the gate electrode 120 Is protruded to the outer periphery of the gate electrode 120.

As shown in FIG. 8B, a gate insulating layer 150 is formed on the left and right ends of the active layer 110. However, the gate electrode 120 does not exist above the left and right end portions of the active layer 110 (end portions of the dummy region 114). Therefore, since the edge portion of the active layer 110 and the gate electrode 120 are not overlapped, parasitic TFTs due to superposition of the gate electrode and the edge portion of the active layer are not formed in the conventional art. Even if a parasitic TFT is formed, it is formed very small.

Thus, it is possible to prevent or improve the hump caused by the formation of the parasitic TFT in the buffer TFT of the scan circuit, thereby improving the output characteristics of the buffer TFT of the scan circuit. If the output characteristics of the buffer TFT of the scan circuit are improved, display quality can be improved by preventing display device screen failure.

The TFTs according to the first and second embodiments of the present invention including the above-described configuration can prevent or minimize the generation of parasitic TFTs at the left and right ends of the active layer 110. [ Here, the pattern of the active layer 110 is changed so that the edge portion of the active layer 110 is extended to the outer edge of the gate electrode 120, that is, the dummy region 114 is arranged, Removed or minimized.

The edge portions of the gate electrode 120 may be positioned in the diagonal direction from the left and right edge portions (dummy region 114) of the active layer 110. However, distances between the left and right edge portions (dummy region 114) of the active layer 110 and the gate electrode 120 are set to be distant from each other with the gate insulating film 150 therebetween. Therefore, even if a parasitic TFT is generated, it is formed so as to be very small to prevent or reduce the occurrence of a hump by the parasitic TFT.

The threshold voltages Vth1 and Vth3 of the parasitic TFT do not overlap with the threshold voltage Vth1 of the channel region 112 of the active layer 110 because the left and right edge portions of the active layer 110 do not overlap the gate electrode 120 Vth2).

Since the parasitic TFTs on the left and right edge portions of the active layer 110 are formed small and the threshold voltages Vth1 and Vth3 of the parasitic TFTs are large, The hump generated in the portion is improved, and a strong electric field is not formed in the edge region of the active layer.

By applying the TFTs according to the first and second embodiments of the present invention to the buffer TFTs of the scan circuit of the gate driver, specifically, the pull-down TFT, it is possible to prevent the occurrence of leakage current (or off current) The current (or the OFF current) can be reduced. Thus, the output of the Q node and the QB node of the scan circuit can be normally performed, thereby preventing a display failure of the display device.

Fig. 9 shows a planar layout of a TFT according to a third embodiment of the present invention, which is a diagram showing a planar layout of a switching TFT constituted in a switching TFT or a pixel circuit constituted in a scanning circuit of a gate driver. 11A is a cross-sectional view of a switching TFT or a switching TFT configured in a pixel circuit configured in a scan circuit according to the E1-E2 line shown in FIG.

Referring to Figs. 9 and 11A, the TFT 200 according to the third embodiment of the present invention can be applied to the switching TFT (to T2 in Fig. 1 (to the reset TFT)) of the scan circuit. The switching TFT of the scan circuit must be operated at a high speed with respect to the input signal, so that it is formed with an area smaller than that of the buffer TFT. Further, the TFT 200 according to the third embodiment of the present invention can be applied to the switching TFT of the pixel circuit. The switching TFT of the pixel circuit must be operated at a high speed with respect to the input signal, so that it is formed with an area smaller than that of the driving TFT.

In the TFT 200 according to the third embodiment of the present invention, the active layer 210 is patterned so that the gate electrodes 220 are arranged in a two-wire structure to form a plurality of channels in order to form multi-channels.

The gate electrode 220 is branched from the gate line into two wirings and is formed long in one direction. The source electrode 230 is disposed on the lower side of the gate electrode 220 on the plane and the drain electrode 240 is disposed on the upper side. However, the present invention is not limited thereto, and the drain electrode 240 may be disposed on the lower side of the gate electrode 220 in a plan view, and the source electrode 230 may be disposed on the upper side of the gate electrode 220.

 The active layer 210 is formed so as to overlap with the gate electrode 220 and the active layer 210 is contacted with the source electrode 230 and the drain electrode 240. A channel region is disposed between the source electrode 130 and the drain electrode 140. The gate electrode 120 and the active layer 110 do not overlap each other, and the gate electrode 120 and the active layer 110 are partially overlapped.

11A, since the TFT 200 according to the third embodiment of the present invention is formed in a top gate structure, the active layer 210 is formed on the substrate, and the gate 200 is formed on the active layer 210, An insulating film 250 is formed. A gate electrode 220 is formed on the gate insulating layer 250.

The active layer 210 includes a channel region 212 and a dummy region 214 disposed at the right edge portion of the channel region 212. 9 and 11A show that the dummy region 214 is disposed at the right edge portion of the channel region 212, this is an example. As another embodiment of the present invention, the dummy region 214 may be disposed at the left edge portion of the channel region 212. [

Here, the active layer 210 may be formed of LTPS (Low-Temperature Poly Silicon). However, the present invention is not limited thereto, and the active layer 210 may be formed of amorphous silicon (a-Si), polysilicon (poly-Si), oxide, or organic material.

A channel region 212 is formed between the source electrode 230 and the drain electrode 240 to overlap the gate electrode 220 to form a multi-channel. The gate electrode 220 is arranged in the form of two wirings and the active layer 210 is arranged in such a way that the gate electrode 220 overlaps the two wirings so that a multi-channel is formed in the channel region 212.

The dummy region 214 starts from the right edge portion of the channel region 212 and is disposed to the outer edge of the gate electrode 220. That is, the dummy region 214 protrudes from one edge (right edge) portion of the channel region 212, and an end of the dummy region 214 is formed at one side outer side (right outer side) of the channel region 212. Thus, the edge portion on the right side of the active layer 210 is not overlapped with the gate electrode 220.

Here, the end of the dummy region 214 is located at the outer edge of the gate electrode 220. Thus, the end of the dummy region 214 is spaced apart from the edge of the gate electrode 220 by a predetermined distance.

For example, the dummy region 214 may extend to the outer periphery of the gate electrode 220 by a length W4 corresponding to 10 to 30% of the width W3 of the portion where the gate electrode 220 and the active layer 210 are overlapped. Respectively. That is to say, the distance from the edge of the gate electrode 220 to the width W4 of the portion corresponding to 10 to 30% of the width W3 of the portion where the gate electrode 220 and the active layer 210 are overlapped, 214 are positioned at the ends of the first and second plates.

The length of the dummy region 214 protruding from the channel region 212 is not limited to 10 to 30% of the width W3 of the portion where the gate electrode 220 and the active layer 210 are overlapped. However, the inventors of the present application have considered that the width W3 of the portion where the gate electrode 220 and the active layer 210 are overlapped with each other is at most 30% in consideration of the designing and manufacturing process margin of the switching TFT constituting the scan circuit The dummy region 214 is protruded to the outer periphery of the gate electrode 220 by a length W4 of the gate electrode 220. [

A gate insulating layer 250 is formed on the upper portion of the right end of the active layer 210. However, the gate electrode 220 is not present above the right end of the active layer 210. Therefore, the parasitic TFT formed by overlapping the gate electrode and the edge portion of the active layer in the prior art is not formed in the present invention. Even if a parasitic TFT is formed, it can be formed very small.

Fig. 10 shows a planar layout of a TFT according to a fourth embodiment of the present invention, which is a diagram showing a planar layout of a switching TFT constituted in a switching TFT or a pixel circuit constituted in a scanning circuit of a gate driver. 11B is a cross-sectional view of a switching TFT configured in a scanning circuit according to the line F11-F2 shown in Fig. 10 or a switching TFT configured in a pixel circuit.

10 and 11B, in the TFT 300 according to the fourth embodiment of the present invention, the gate electrodes 320 are arranged in a two-wire structure in order to form multi-channels. In addition, the active layer 310 is patterned to form a plurality of channels.

The gate electrode 320 is branched from the gate line to two wirings and is formed long in one direction. The source electrode 330 is disposed on the lower side of the gate electrode 302 on the plane and the drain electrode 340 is disposed on the upper side. However, the present invention is not limited to this, and the drain electrode 330 may be disposed on the lower side of the gate electrode 302 on the plane, and the source electrode 340 may be disposed on the upper side.

  The active layer 310 is formed so as to overlap with the gate electrode 320 and the channel region of the active layer 310 is in contact with the source electrode 330 and the drain electrode 340. A channel region is disposed between the source electrode 330 and the drain electrode 340, overlapping the two wirings of the active layer 310 and the gate electrode 320 to form a multi-channel. The gate electrode 320 and the active layer 310 do not overlap each other and the gate electrode 320 and the active layer 310 are partially overlapped.

The dummy region 314 of the active layer 310 starts from the left and right edge portions of the channel region 312 and is disposed to the outer edge of the gate electrode 320. That is, the dummy region 314 protrudes from the left and right edge portions of the channel region 312, and the ends of the dummy region 314 are formed on the left and right outer edges of the channel region 312. As a result, the left and right edge portions of the active layer 310 are not overlapped with the gate electrode 320.

When the end of the dummy region 314 is located at the outer edge of the gate electrode 320, the end of the dummy region 314 is located a predetermined distance away from the left and right edges of the gate electrode 320.

For example, the dummy region 314 may extend to the outer periphery of the gate electrode 320 by a length W6 corresponding to 10 to 30% of the width W5 of the portion where the gate electrode 320 and the active layer 310 are overlapped. Respectively. That is to say, the gate electrode 320 and the active layer 310 are overlapped with each other by a distance W6 equal to 10 to 30% of the width W5 of the portion overlapping the gate electrode 320 and the active layer 310 from the edge of the gate electrode 320, 314 are positioned.

The length of the dummy region 314 protruding from the channel region 312 is not limited to 10 to 30% of the width W5 of the portion where the gate electrode 320 and the active layer 310 are overlapped. However, the inventors of the present application have found that the width of a portion where the gate electrode 320 and the active layer 310 are overlapped with each other (for example, The dummy region 314 is set to protrude to the outer periphery of the gate electrode 320 by a length W6 corresponding to at most 30%

The TFTs according to the third and fourth embodiments of the present invention including the above-described configuration can prevent generation of parasitic TFTs at the left and right ends of the active layer 210 or reduce the size of the parasitic TFTs. Here, the pattern of the active layer 310 is changed so that the edge portion of the active layer 310 extends to the outer edge of the gate electrode 320, thereby eliminating or minimizing the area where the parasitic TFT can be generated.

The edge portion of the gate electrode 320 may be positioned in the diagonal direction from the left and right edge portions (dummy region 314) of the active layer 310. However, the distance between the left and right edge portions (the dummy region 314) of the active layer 310 and the gate electrode 320 is set to be large with the gate insulating film 350 therebetween. Therefore, even if a parasitic TFT is generated, it is formed so as to be very small to prevent or reduce the occurrence of a hump by the parasitic TFT.

The threshold voltages Vth1 and Vth3 of the parasitic TFT do not overlap with the threshold voltage of the channel region 312 of the active layer 310 because the left and right edge portions of the active layer 310 do not overlap with the gate electrode 320 Vth2).

Since the parasitic TFTs on the left and right edge portions of the active layer 310 are formed small and the threshold voltages Vth1 and Vth3 of the parasitic TFTs have large values, The occurrence of the hump that has occurred in the portion of the active layer is prevented or improved, and a strong electric field is not formed in the edge region of the active layer.

When the TFTs according to the third and fourth embodiments of the present invention are applied to the switching TFT of the scan circuit of the gate driver, the leakage current (or off current) of the switching TFT is reduced and the output of the Q- Is normally performed. As a result, it is possible to prevent a display abnormality in the display device.

Further, when the TFT according to the third and fourth embodiments of the present invention is applied to the switching TFT of the pixel circuit shown in Fig. 5, the leakage current (or off current) of the switching TFT of the pixel circuit is reduced, It is possible to prevent the motor from being driven abnormally. Thus, it is possible to prevent the data voltage from being supplied to the driving TFT DT during the OFF period of the OLED, thereby causing the display abnormal defect to occur.

12 is a view showing an improvement of the output characteristics of the TFT and an effect of improving the hump by changing the pattern of the active layer of the TFT according to the first to fourth embodiments of the present invention. The output characteristics of the TFT shown in Fig. 12 are measured values under the conditions of Vds = 0.1 V and Vds = 10 V. Here, Vth [V] and mobility [cm ² / Vs] are measured values under the condition of Vds = 0.1 V, and Vfb [V], S-factor [V / dec], Ion [uA] pA] is the result of measurement under the condition of Vds = 10V.

12, the TFT according to the first and second embodiments of the present invention is applied to a pull-down TFT (T1 in FIG. 1) of a scan circuit, and the TFT according to the third and fourth embodiments of the present invention is scanned (T2 in Fig. 1) of the circuit and the switching TFT (ST1, ST2 in Fig. 5) of the pixel circuit. In this case, the threshold voltage (Vth) and the flat band voltage (Vfb) of the TFT can be increased. In addition, the on-current Ion can be improved. Further, it is possible to improve the hump due to the generation of strong electric field at the edge portion of the active layer of the TFT, thereby reducing the leakage current, thereby preventing display defects of the display device, thereby improving display quality.

Fig. 13 shows a planar layout of a TFT according to a fifth embodiment of the present invention, and is a diagram showing a planar layout of a driving TFT configured in a pixel circuit. 14 is a cross-sectional view of the driving TFT along the line G1-G2 shown in Fig.

Referring to Figs. 13 and 14, the TFT 400 according to the fifth embodiment of the present invention can be applied to a driving TFT (DT in Fig. 5) of a pixel circuit.

The gate electrode 420 of the TFT 400 is formed by branching from the gate line. A source electrode 430 is formed on the lower side of the gate electrode 420 on the plane, and a drain electrode 440 is formed on the upper side. However, the present invention is not limited to this, and the drain electrode 440 may be formed on the lower side of the gate electrode 420 on the plane, and the source electrode 430 may be formed on the upper side. An active layer 410 is formed so as to overlap with the gate electrode 420.

The TFT 400 according to the fifth embodiment of the present invention has a top gate structure. An active layer 410 is disposed on the substrate, and a gate insulating layer 450 is disposed on the active layer 410. A gate electrode 420 is disposed on the gate insulating film 450.

The active layer 410 includes a channel region 412 and a dummy region 414 disposed at an edge portion of the channel region 412. Here, the active layer 410 may be formed of LTPS (Low-Temperature Poly Silicon). However, the present invention is not limited thereto, and the active layer 410 may be formed of amorphous silicon (a-Si), polysilicon (poly-Si), oxide, or organic material.

A portion of the active layer 410 overlapping with the gate electrode 420 becomes a channel region 412. That is, the channel region 412 overlaps the gate electrode 420. A channel region 412 is disposed between the source electrode 430 and the drain electrode 440.

The dummy region 414 of the active region 410 starts from the right edge portion of the channel region 412 and is disposed to the outer edge of the gate electrode 420. That is, the dummy region 414 protrudes from one edge (right edge) portion of the channel region 412, and the end of the dummy region 414 is disposed on one side outer side (right outer side) of the channel region 412. Thus, the edge portion on the right side of the active layer 410 is not overlapped with the gate electrode 420.

The dummy region 414 may protrude from the left edge portion of the channel region 412 and the end of the dummy region 414 may be disposed on the left outside of the channel region 412. [ In this case, the left edge portion of the active layer 410 is not overlapped with the gate electrode 420.

Since the end of the dummy region 414 is located outside the left or right edge portion of the gate electrode 420, the end of the dummy region 414 is spaced a predetermined distance from the left or right edge portion of the gate electrode 420 Away.

For example, the dummy region 414 may have a length W8 corresponding to 50 to 100% of the width W7 of the overlapping portion of the gate electrode 420 and the active layer 410, And protrudes beyond the outer surface. That is, at the end of the gate electrode 320, a distance of W8 corresponding to 50 to 100% of the width W7 of the overlapping portion of the gate electrode 420 and the active layer 410, 414 are disposed.

The length of the dummy region 414 protruding from the channel region 412 is not limited to 50 to 100% of the width W7 of the portion where the gate electrode 420 and the active layer 410 are overlapped. However, the inventors of the present application have found that, considering the designing and manufacturing process margin of the driving TFT constituting the pixel circuit, the width W7 of the portion where the gate electrode 420 and the active layer 410 overlap The dummy region 414 is set to protrude to the outer periphery of the gate electrode 420 by the length W8 of the gate electrode 420. [

A gate insulating layer 450 is formed on the upper portion of the right end of the active layer 410. However, the gate electrode 420 does not exist above the right end portion of the active layer 410. Therefore, since the edge portion of the active layer 410 and the gate electrode 420 are not overlapped, the parasitic TFT due to overlapping of the edge portion of the active layer and the gate electrode is not formed in the prior art. Even if a parasitic TFT is formed, it is formed very small.

The TFT according to the fifth embodiment of the present invention including the above-described structure can prevent or minimize generation of parasitic TFTs at one end of the active layer 410. [ That is, the pattern of the active layer 410 is changed so that the edge portion of the active layer 410 extends to one side of the gate electrode 420, thereby eliminating or minimizing the region where the parasitic TFT can be generated.

An edge portion of the gate electrode 420 may be positioned in a diagonal direction from an edge portion of one side of the active layer 410. However, since the interval between the active layer 410 and the gate electrode 420 is long with the gate insulating film 450 therebetween, the parasitic TFT is formed small.

The threshold voltage Vth1 of the parasitic TFT is larger than the threshold voltage Vth2 of the channel region 412 of the active layer 410 because the edge portion of one side of the active layer 410 does not overlap with the gate electrode 420 .

Since the parasitic TFT at one edge portion of the active layer 410 is small and the threshold voltage Vth1 of the parasitic TFT has a large value as described above, Is improved. In addition, a strong electric field is not formed in the edge region of the active layer 410.

By applying the TFT according to the fifth embodiment of the present invention to the driving TFT (DT in Fig. 5) of the pixel circuit, it is possible to prevent or improve the hump caused by the formation of the parasitic TFT in the driving TFT of the pixel circuit, Can be improved. In addition, the leakage current (or off current) of the driving TFT is reduced, thereby preventing defective display due to light emission during the period in which the OLED is off, and improving the display quality of the display device.

15 is a view showing a channel formed in the active layer and a switching TFT (reset TFT) of a scan circuit or a switching TFT of a pixel circuit in a pull-down TFT or a scan circuit of FIG. 15 in a single gate (top gate) structure. The substrate of the display device is not shown in Fig.

Referring to FIG. 15, the TFTs according to the first to fifth embodiments of the present invention can be formed into a top gate structure in which one gate electrode is disposed on the active layer. Specifically, an active layer 110 is disposed on an insulator, and a gate insulating layer 150 is disposed on the active layer 110. A gate electrode 120 is disposed on the gate insulating layer 150. At this time, the gate electrode 120 is arranged to overlap the active layer 110, and the channel 170 is formed on the upper surface of the active layer 110.

The pull-down TFT of the scan circuit, the switching TFT of the scan circuit, and the switching TFT of the pixel circuit described in the first to fourth embodiments of the present invention can be formed by a top gate structure in which one gate electrode is disposed on the active layer. In this case, as shown in Fig. 12, the threshold voltage (Vth) and the flat band voltage (Vfb) of the pull-down TFT of the scan circuit, the switching TFT of the scan circuit, and the switching TFT of the pixel circuit can be increased. In addition, the on-current Ion can be improved. Further, it is possible to improve the hump due to the generation of strong electric field at the edge portion of the active layer of the TFT, thereby reducing the leakage current, thereby preventing display defects of the display device, thereby improving display quality.

Then, the driving TFT of the pixel circuit described in the fifth embodiment of the present invention can be formed into a top gate structure in which one gate electrode is disposed on the active layer.

16 is a diagram showing an improvement in the output characteristics of the driving TFT and an effect in which the hump is improved by changing the pattern of the active layer of the driving TFT according to the fifth embodiment of the present invention. The output characteristics of the TFT shown in Fig. 16 are measured values under the conditions of Vds = 0.1 V and Vds = 10 V. Here, Vth [V] and mobility [cm ² / Vs] are measured values under the condition of Vds = 0.1 V, and Vfb [V], S-factor [V / dec], Ion [uA] pA] is the result of measurement under the condition of Vds = 10V.

Referring to Fig. 16, when the TFT according to the fifth embodiment of the present invention is applied to a driving TFT (DT in Fig. 5) of a pixel circuit, the threshold voltage Vth and the flat band voltage Vfb of the TFT are increased, - It is possible to improve the current (Ion). Thus, it is possible to improve the hump due to the generation of the strong electric field at the edge portion of the active layer 410 of the TFT, thereby reducing the leakage current and preventing display defects of the display device, thereby improving the display quality.

FIG. 17 shows a planar layout of a TFT according to a sixth embodiment of the present invention, and is a diagram showing a plane layout of a pull-down TFT among buffer TFTs configured in a scan circuit of a gate driver.

FIG. 18A is a view showing a gate electrode in the plan layout of the pull-down TFT shown in FIG. 17, FIG. 18B is a view showing an active layer in the plan layout of the pull-down TFT shown in FIG. 17, And the source electrode and the drain electrode in the plane layout of the pull-down TFT. Fig. 19A is a cross-sectional view taken along line I1-I2 shown in Fig. 17, and Fig. 19B is a cross-sectional view taken along line I3-I4 shown in Fig.

17 to 19B, the TFT 500 according to the sixth embodiment of the present invention can be applied to buffer TFTs (pull-up TFT and pull-down TFT) of a scan circuit. In the following description, it is assumed that the TFT 100 according to the sixth embodiment of the present invention is applied to a pull-down TFT (T1 in FIG. 1) among the buffer TFTs of the scan circuit.

The pull-down TFT of the scan circuit is formed in a large area compared with general switching TFTs to withstand the deterioration due to high voltage and long driving. In the TFT 500 according to the sixth embodiment of the present invention, the gate electrode 520 is formed in the structure of two wirings 520a and 520b to form multi-channel.

The first wiring 520a and the second wiring 520b of the gate electrode 520 are electrically connected to each other and are electrically connected to the first wiring 520a and the second wiring 520b of the gate electrode 520, (510) are disposed to form multi-channels.

The TFT 500 according to the sixth embodiment of the present invention is formed in a top gate structure. An active layer 510 is formed on the insulating layer and a gate insulating layer 550 is formed on the active layer 510. A gate electrode 520 is formed on the gate insulating film 550.

The gate electrode 520 is branched into two wirings 520a and 520b in the gate line and is formed long in one direction. A source electrode 530 is disposed on the lower side of the gate electrode 520 on the plane and a drain electrode 540 is disposed on the upper side of the gate electrode 520. However, the present invention is not limited to this, and the drain electrode 540 may be disposed on the lower side of the gate electrode 520 on the planar surface, and the source electrode 530 may be disposed on the upper side of the gate electrode 520.

The active layer 510 is formed so as to overlap with the gate electrode 520 and the channel region 512 of the active layer 510 is in contact with the source electrode 530 and the drain electrode 540. The gate electrode 520 and the active layer 510 do not overlap each other and the gate electrode 520 and the active layer 510 are partially overlapped.

Here, the source electrode 530 and the drain electrode 540 are disposed at both ends of the active layer 510. The source electrode 530 is connected to the data line through the contact metal formed in the contact hole and the drain electrode 540 is connected to the anode electrode (or signal line) of the OLED.

The active layer 510 includes a plurality of channel regions 512, a dummy region 514 formed in the left and right edge portions of the channel region 512, and a plurality of link regions 516 ).

Here, the active layer 510 may be formed of LTPS (Low-Temperature Poly Silicon). However, the present invention is not limited thereto, and the active layer 110 may be formed of amorphous silicon (a-Si), polysilicon (poly-Si), oxide, or organic material.

A plurality of channel regions 512 are overlapped with the gate electrode 520 to form a multichannel and a channel region 512 is disposed between the source electrode 530 and the drain electrode 540.

A plurality of link regions 516 are disposed between the plurality of channel regions 512 to connect the plurality of channel regions 512. That is, the plurality of channel regions 512 are connected by a plurality of link regions 516 in one pattern.

  When forming the active layer 510, a plurality of channel regions 512 and a plurality of link regions 516 are formed by patterning a conductive transparent material (e.g., ITO) layer. Therefore, the plurality of channel regions 512 and the plurality of link regions 516 are formed of the same material.

As an example, the vertical width of each of the plurality of link regions 516 is formed larger than the width of each of the two wirings 520a and 520b of the gate electrode 520 in the vertical direction. As another example, the width of each of the plurality of link regions 516 is formed smaller than the width of the gate electrode 520, but the vertical width of the first wiring 520a of the gate electrode 520 and the vertical width of the second wiring 520b Of the plurality of link regions 516 is larger than the sum of the vertical widths of the link regions 516.

  In the first and second embodiments shown in Figs. 6 and 7, the link region is not formed at the portion corresponding to the empty space between the two wirings of the gate electrode. On the other hand, in the sixth embodiment shown in FIG. 17, a link region 516 is also formed in a portion corresponding to the empty space between the two wirings 520a and 520b of the gate electrode 520. [

When the display device has a resolution of QHD (Quad High Definition) or higher (for example, 4K resolution or 8K resolution), the channel length of the TFT of the pixel circuit and the buffer TFT of the scan circuit decreases do. For example, when the vertical width of each of the two wirings 520a and 520b of the gate electrode 520 is 3um or less, an empty space between the two wirings 520a and 520b of the gate electrode 520, as shown in Fig. 17, The link region 516 is formed. In this way, a channel region 512, a dummy region 514, and a link region 516 for improving the hump of the TFT can also be applied to a high-resolution (QHD, 4K, 8K) display device.

Particularly, when the vertical width of each of the two wirings 520a and 520b of the gate electrode 520 is 1um or less, the width of the two wirings 520a and 520b of the gate electrode 520 corresponding to the vacant space between the two wirings 520a and 520b of the gate electrode 520 A plurality of channel regions 512 may be formed by forming a link region 516 in a portion. As a result, a channel region 512, a dummy region 514, and a link region 516 for improving the hump of the TFT can also be applied to the high-resolution display device.

The dummy region 514 is disposed at the left and right edge portions of the channel region 512. That is, the dummy region 514 protrudes from the left and right edge portions of the channel region 512. For example, the dummy area 514 is protruded by a length corresponding to 10 to 30% of the width of one channel region 512. Here, the length of the dummy region 514 protruding from the channel region 512 is not necessarily limited to 10 to 30% of the width of one channel region 512. However, the inventors of the present application have considered that the dummy region 514 is protruded by a length corresponding to at most 30% of the width of one channel region 512 in consideration of the design and manufacturing process margin of the pull-down TFT constituting the scan circuit Respectively.

As another example, the dummy region 514 may protrude by a length corresponding to 10 to 30% of the width of the gate electrode 520. The length of the dummy region 514 protruding from the channel region 512 is not limited to 10 to 30% of the width of the gate electrode 520. However, the inventors of the present application set the dummy region 514 to protrude by a length corresponding to at most 30% of the width of the gate electrode 520 in consideration of the design and manufacturing process margin of the pull-down TFT constituting the scan circuit .

As another example, the dummy region 514 may protrude by a length corresponding to 10 to 30% of the width of the overlapping portion of the gate electrode 520 and the active layer 510. The length of the dummy region 514 protruding from the channel region 512 is not limited to 10 to 30% of the width of the portion where the gate electrode 520 and the active layer 510 are overlapped. However, the inventors of the present application have found that, considering the design and manufacturing process margin of the pull-down TFT constituting the scan circuit, the gate electrode 520 and the active layer 510 have a length corresponding to at most 30% So that the dummy area 514 is projected.

As another example, in addition to the pull-down TFT and the switching TFT constituting the scan circuit, in the case of the driving TFT of the pixel circuit, 50 to 100% of the width of the overlapping portion of the gate electrode 520 and the active layer 510 The dummy area 514 may be protruded by a length. The length of the dummy region 514 protruding from the channel region 512 is not limited to 50 to 100% of the width of the overlapping portion of the gate electrode 520 and the active layer 510. However, the inventors of the present application have found that, considering the designing and manufacturing process margins of the driving TFTs constituting the pixel circuit, the inventors of the present application have found that the length of the portion overlapping the gate electrode 520 and the active layer 510 is 100% So that the dummy area 514 is projected.

The TFT 500 according to the sixth embodiment of the present invention including the above-described structure can prevent or minimize generation of parasitic TFTs at the left and right ends of the active layer 510. [ Even if a parasitic TFT is formed, the parasitic TFT is formed in the buffer TFT of the scan circuit so as to prevent or improve the hump, so that the output characteristics of the buffer TFT of the scan circuit can be improved. If the output characteristics of the buffer TFT of the scan circuit are improved, display quality can be improved by preventing display device screen failure.

The application of the TFT 500 according to the sixth embodiment of the present invention to the buffer TFTs of the scan circuit of the gate driver, specifically, the pull-down TFT prevents generation of leakage current (or off current) in the scan circuit, The current (or the OFF current) can be reduced. Thus, the output of the Q node and the QB node of the scan circuit can be normally performed, thereby preventing a display failure of the display device.

20 shows a planar layout of a TFT according to a seventh embodiment of the present invention, in which a pull-down TFT of a scan circuit is formed in a double gate structure and a plane showing a plurality of channels formed in the active layer. 21A is a cross-sectional view of a pull-down TFT of a scan circuit according to J1-J2 line shown in FIG. 21B is a cross-sectional view of a pull-down TFT of a scan circuit according to J3-J4 line shown in FIG.

Referring to FIGS. 20 to 21B, a pull-down TFT 500 may be formed with a double gate structure in which gate electrodes 560 and 580 are disposed under and over the active layer 570. Here, the pull-down TFT 500 of the scan circuit is formed to have a larger area than general switching TFTs so as to withstand the deterioration due to high voltage and long driving.

Specifically, an active layer 570 is disposed on an insulator, and a gate insulating film 550 is disposed on the active layer 570. An upper gate electrode 560 (first gate electrode) is disposed on the gate insulating film 550. A lower gate electrode 580 (second gate electrode) is disposed under the insulating film. Although not shown in the drawing, the upper gate electrode 560 and the lower gate electrode 580 are electrically connected to each other through a contact.

And the upper gate electrode 560 is formed in a structure of two wirings 560a and 560b. The first wiring 560a and the second wiring 560b of the upper gate electrode 560 are electrically connected to each other so as to overlap the first wiring 560a and the second wiring 560b of the upper gate electrode 560. [ An active layer 570 is disposed to form multi-channels.

Further, the lower gate electrode 580 is formed in a structure of two wirings 580a and 580b. The first and second wirings 580a and 580b of the lower gate electrode 580 are electrically connected to each other and overlap the first and second wirings 580a and 580b of the lower gate electrode 580. [ An active layer 570 is disposed to form multi-channels.

The upper gate electrode 560 and the lower gate electrode 580 may be formed in the same shape and disposed with the active layer 570 therebetween. In this case, the distance from the edge of the upper gate electrode 560 to the end of the dummy region 574 and the distance from the edge of the lower gate electrode 580 to the end of the dummy region 574 may be the same.

However, the present invention is not limited thereto, and the upper gate electrode 560 and the lower gate electrode 580 may be formed in different shapes. In this case, the end of the dummy region 574 and the end of the upper gate electrode 560 are spaced apart from each other by a first distance, and the end of the dummy region 574 and the end of the lower gate electrode 580 are spaced apart from each other by a second distance Can be spaced apart. That is, the distance from the end of the upper gate electrode 560 to the end of the dummy region 574 may be different from the distance from the end of the lower gate electrode 580 to the end of the dummy region 574.

The active layer 570 includes a plurality of channel regions 572 and a plurality of link regions 576 disposed between the plurality of channel regions 572.

Here, the active layer 570 may be formed of LTPS (Low-Temperature Poly Silicon). However, the present invention is not limited thereto, and the active layer 570 may be formed of amorphous silicon (a-Si), polysilicon (poly-Si), oxide, or organic material. A plurality of channel regions 572 are disposed between the upper gate electrode 560 and the lower gate electrode 580.

A plurality of link regions 576 are disposed between the plurality of channel regions 572 to connect the plurality of channel regions 572. That is, the plurality of channel regions 572 are connected by a plurality of link regions 576 in one pattern. A plurality of channel regions 572, a plurality of dummy regions 574 and a plurality of link regions 176 are formed by patterning a layer of a conductive transparent material (e.g., ITO) when forming the active layer 570. Therefore, the plurality of channel regions 572, the plurality of dummy regions 574, and the plurality of link regions 576 are formed of the same material.

A top gate electrode 560 is disposed on top of the active layer 570 so that a first channel 570a is formed on the top surface of the active layer 570. A lower gate electrode 580 is disposed on the lower portion of the active layer 570 so that the second channel 570b is formed on the lower surface of the active layer 570. That is, if the pull-down TFT of the scan circuit is formed in the double gate structure, the active layer 570 can have a plurality of channels 570a and 570b since channels are formed on the lower and upper surfaces of the active layer 570, respectively.

However, the present invention is not limited to this, and a double gate structure can be applied to a switching TFT (reset TFT) of a scan circuit, a switching TFT of a pixel circuit, and a driving TFT of a pixel circuit. This makes it possible to form channels on the lower and upper surfaces of the active layer in the switching TFT (reset TFT) of the scan circuit, the switching TFT of the pixel circuit, and the driving TFT of the pixel circuit.

In comparison with a TFT having a single gate structure, the number of channels of the double-gate TFT is doubled, that is, the channel width is doubled, so that the output characteristics of the TFT can be improved.

22 is a diagram showing an improvement in the output characteristics of the pull-down TFT and an improvement in the hump by changing the pattern of the active layer of the pull-down TFT according to the seventh embodiment of the present invention. The output characteristics of the TFT shown in Fig. 22 are measured values under the conditions of Vds = 0.1 V and Vds = 10 V. [ Here, Vth [V] and mobility [cm ² / Vs] are measured values under the condition of Vds = 0.1 V, and Vfb [V], S-factor [V / dec], Ion [uA], Ioff [pA] Is a result of measurement under the condition of Vds = 10V.

Referring to FIG. 22, it is possible to prevent or improve the occurrence of a hump in the pull-down TFT of the scan circuit. Specifically, the threshold voltage (Vth) and the flat band voltage (Vfb) of the TFT can be increased. In addition, the on-current Ion can be improved.

The output characteristic curve of the TFT is shown in Fig. The output characteristic curve is largely composed of the area (1) indicating low current output characteristics and the area (2) indicating high current output characteristics. When the hump occurs in the TFT, the output characteristic curve (a) shifts to the low voltage side (shifts to the left) in the region (1). In the region (2), the output characteristic curve (b) shifts to the high voltage side (shifts to the right).

By changing the pattern of the active layer in the pull-down TFT of the scan circuit, the switching TFT (reset TFT) of the scan circuit, the switching TFT of the pixel circuit, and the driving TFT of the pixel circuit, the hump was not generated in the TFT.

It can be seen that the output characteristic curve (a) which has been shifted (shifted to the left) from the region to the low voltage side is shifted to the position of the normal voltage (shifted to the right). In addition, it can be seen that the output characteristic curve (b) which has been shifted (shifted to the right) toward the high voltage in the region (2) is shifted (shifted to the left) to the position of the normal voltage. By doing so, the output of the pull-down TFT of the scan circuit is made normally so that the display quality of the display device can be improved.

The dummy region of the thin film transistor of the display device according to the embodiments of the present invention protrudes from one side or both edge portions of the channel region and is disposed at the outer periphery of the gate electrode.

Further, the end of the dummy region and the gate electrode do not overlap.

Further, the dummy region protrudes from one or both edge portions of the channel region.

Also, the dummy region protrudes by a length corresponding to at most 30% of the width of the gate electrode.

Also, the dummy region is protruded by a length corresponding to at most 30% of the width of a portion where the gate electrode and the active layer overlap each other.

In addition, the dummy region is protruded by a length corresponding to at most 100% of the width of a portion where the gate electrode and the active layer overlap each other.

In addition, the dummy region protrudes by a length corresponding to at most 30% of the width of one channel region.

Also, a first threshold voltage of the dummy region is formed to be higher than a second threshold voltage of the channel region.

Further, the vertical width of each of the plurality of link regions is larger than the vertical width of each of the plurality of wiring lines.

Further, the vertical width of each of the plurality of link regions is larger than the sum of the vertical widths of the plurality of wirings.

It will be understood by those skilled in the art that the present invention can be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

100, 200, 300, 400, 500: Thin film transistor (TFT)
110, 210, 310, 410, 510: active layer
112, 212, 312, 412, 512: channel region
114, 214, 314, 414, 514:
116, 516: Link area
120, 220, 320, 420, 520: gate electrode
520a: first wiring of the gate electrode
520b: second wiring of the gate electrode
130, 230, 330, 430, 530: source electrode
140, 240, 340, 440, 540: drain electrode
150, 250, 350, 450, 550: gate insulating film
560: upper gate electrode
560a: first wiring of the upper gate electrode
560b: second wiring of the upper gate electrode
570: active layer
570a: first channel
570b: the second channel
580: lower gate electrode
580a: first wiring of the bottom gate electrode
580b: second wiring of the bottom gate electrode
Vth1, Vth3: threshold voltage of the edge region of the active layer
Vth2: Threshold voltage of the channel region of the active layer

Claims (9)

An active layer disposed on the substrate;
A gate electrode branched to a plurality of wirings and arranged to overlap the active layer;
A gate insulating film disposed between the active layer and the gate electrode; And
And a source electrode and a drain electrode disposed at both ends of the active layer,
The active layer includes one or more channel regions disposed between the source electrode and the drain electrode; A dummy region having a length elongated at an edge portion of the channel region; And a plurality of link regions formed between the plurality of channel regions and connecting the plurality of channel regions in one pattern,
Wherein the plurality of link regions are disposed so as to overlap a portion corresponding to a space between the plurality of wirings. The method according to claim 1,
Wherein the dummy region protrudes from one or both edge portions of the channel region. 3. The method of claim 2,
Wherein the dummy region protrudes by a length corresponding to at most 30% of the width of the gate electrode. 3. The method of claim 2,
Wherein the dummy region protrudes by a length corresponding to at most 30% of a width of a portion where the gate electrode and the active layer overlap each other. 3. The method of claim 2,
Wherein the dummy region is protruded by a length corresponding to at most 100% of a width of a portion where the gate electrode and the active layer overlap each other. 3. The method of claim 2,
Wherein the dummy region protrudes by a length corresponding to at most 30% of a width of one channel region. The method according to claim 1,
Wherein a first threshold voltage of the dummy region is higher than a second threshold voltage of the channel region. The method according to claim 1,
Wherein the vertical width of each of the plurality of link regions is larger than the vertical width of each of the plurality of wiring lines. The method according to claim 1,
Wherein a vertical width of each of the plurality of link regions is larger than a sum of vertical widths of the plurality of wirings.

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