JP2006128160A - Semiconductor apparatus and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve electrical characteristics by effectively reducing a leakage current. <P>SOLUTION: A semiconductor apparatus includes a semiconductor layer 40, a gate insulating layer 50 provided above the semiconductor layer 40, a gate electrode 60 provided above the gate insulating layer 50, first impurity regions 70 and 72 which are formed in a region exposed from the gate electrode 60 in the semiconductor layer 40 and constitute a source region or a drain region, and second impurity regions 80 and 82 formed in a region exposed from the gate electrode 60 in the semiconductor layer 40 and made of different conductivity type from the first impurity regions 70 and 72. At least one end 62 of the gate electrode 60 covers the first and second end faces 42 and 44 of the semiconductor layer 40. The first impurity region 70 is arranged in contact with one of the first end faces 42 of the semiconductor layer 40, and the second impurity region 80 is arranged in contact with the other of the first end faces 42 of the semiconductor layer 40. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

2. Description of the Related Art A field effect transistor having an SOI (Silicon on Insulator) structure that is capable of low power consumption and high speed operation is known as a semiconductor device. According to a conventional SOI type semiconductor device, a parasitic MOS transistor having a threshold value lower than a design threshold value may be formed due to the concentration of an electric field on the end face of a semiconductor layer. When such a parasitic MOS transistor is formed, the leakage current of the semiconductor device increases and it becomes difficult to obtain excellent electrical characteristics. As an improvement measure, it is known to suppress the concentration of the electric field on the end face of the semiconductor layer by doping impurities or forming a thick gate insulating layer, but not only the process becomes complicated, but also leakage current is reduced. Effective reduction may not be achieved.
JP 2001-53284 A

  An object of the present invention is to provide a semiconductor device capable of effectively reducing leakage current and improving electrical characteristics, and a method for manufacturing the same.

(1) A semiconductor device according to the present invention includes a semiconductor layer,
A gate insulating layer provided above the semiconductor layer;
A gate electrode provided above the gate insulating layer;
A first impurity region formed in a region exposed from the gate electrode in the semiconductor layer and constituting a source region or a drain region;
A second impurity region formed in a region exposed from the gate electrode in the semiconductor layer and having a conductivity type different from that of the first impurity region;
Including
At least one end of the gate electrode covers the end surface of the semiconductor layer,
The first impurity region is disposed adjacent to one of the end surfaces of the semiconductor layer, and the second impurity region is disposed adjacent to the other of the end surfaces of the semiconductor layer.

  According to the present invention, the first and second impurity regions adjacent to the end face of the semiconductor layer covered with the gate electrode have different conductivity types. As a result, even when the electric field is concentrated and a parasitic channel is generated on the end face of the semiconductor layer, the current passing through the end face of the semiconductor layer can be cut off, and the leakage current can be effectively reduced. it can.

  In the present invention, the B layer is provided above the specific A layer means that the B layer is provided directly on the A layer and the B layer via another layer on the A layer. Is provided. The same applies to the following inventions.

(2) In this semiconductor device,
At least one end of the gate electrode covers the first and second end faces of the semiconductor layer,
The second impurity region is disposed between the first and second end faces of the semiconductor layer;
The first impurity region constituting the source region is disposed on the first end face of the semiconductor layer adjacent to the side opposite to the second impurity region,
The first impurity region constituting the drain region may be disposed on the second end face of the semiconductor layer adjacent to the side opposite to the second impurity region.

  According to this, the first end surface of the semiconductor layer covered with the gate electrode, the second impurity region, and the second end surface of the semiconductor layer covered with the gate electrode are between the source region and the drain region. Arranged in order. Therefore, among the current flowing between the source and the drain, the current passing through the end face of the semiconductor layer can be cut off, and the leakage current can be effectively reduced.

(3) In this semiconductor device,
At least one end portion of the gate electrode includes a first branch portion that covers the first end surface of the semiconductor layer, and a second branch portion that covers the second end surface of the semiconductor layer. You may have.

(4) In this semiconductor device,
The second impurity region is formed in a region including at least a tip of a convex portion extending with a shorter width than the rectangular portion from the rectangular portion in which the first impurity region is formed,
At least one end of the gate electrode may be extended with a width larger than the width of the tip of the projection, avoiding the tip of the projection.

(5) In this semiconductor device,
The semiconductor layer may be an SOI (Silicon on Insulator) layer.

(6) A method for manufacturing a semiconductor device according to the present invention includes:
(A) forming a gate insulating layer above the semiconductor layer;
(B) forming a gate electrode above the gate insulating layer and having at least one end covering the end face of the semiconductor layer;
(C) In the region exposed from the gate electrode in the semiconductor layer, a first impurity region constituting a source region or a drain region, and a second impurity region having a conductivity type different from that of the first impurity region are formed. Forming,
Including
In the step (c), the first impurity region is formed at a position adjacent to one of the end faces of the semiconductor layer, and the second impurity region is formed at a position adjacent to the other end face of the semiconductor layer. Form.

  According to the present invention, the first and second impurity regions adjacent to the end face of the semiconductor layer covered with the gate electrode have different conductivity types. As a result, even when the electric field is concentrated and a parasitic channel is generated on the end face of the semiconductor layer, the current passing through the end face of the semiconductor layer can be cut off, and the leakage current can be effectively reduced. it can.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a plan view of a semiconductor device according to a first embodiment to which the present invention is applied. 2 is a cross-sectional view taken along line II-II in FIG. 1, FIG. 3 is a cross-sectional view taken along line III-III in FIG. 1, FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. It is a VV sectional view taken on the line. Semiconductor device 100 according to the present embodiment includes a semiconductor layer 40, a gate insulating layer 50, and a gate electrode 60.

  As shown in FIG. 2, the semiconductor layer 40 is an SOI (Silicon on Insulator) layer. Specifically, the semiconductor device 100 includes an SOI type semiconductor substrate 10 in which a support substrate 20, an insulating layer 30, and a semiconductor layer 40 are sequentially stacked. In the case of the SOI type semiconductor substrate 10, a plurality of semiconductor layers 40 are patterned in an island shape on the insulating layer 30. Further, an element isolation region is formed between the semiconductor layers 40. The form of the element isolation region may be mesa type isolation, STI (Shallow Trench Isolation) type isolation, or LOCOS (Local Oxidation of Silicon) type isolation. Examples of the semiconductor layer 40 include a single crystal silicon layer, an amorphous silicon layer, a polycrystalline silicon layer, or a silicon germanium layer.

  A gate insulating layer 50 is provided on the semiconductor layer 40, and a gate electrode 60 is provided on the gate insulating layer 50. In the semiconductor layer 40, a channel region is formed below the gate electrode 60 (gate insulating layer 50).

  In the semiconductor layer 40, a first impurity region 70 constituting a source region and a first impurity region 72 constituting a drain region are formed (see FIG. 4). The first impurity regions 70 and 72 are exposed from the gate electrode 60. The first impurity regions 70 and 72 are formed in the respective regions sandwiching the gate electrode 60 and are disposed to face each other. Specifically, the first impurity region 70, the gate electrode 60, and the first impurity region 72 are sequentially provided in the direction along the gate length (channel length). The first impurity regions 70 and 72 are of the first conductivity type (for example, n-type).

  In the semiconductor layer 40, second impurity regions 80 and 82 are formed in a region exposed from the gate electrode 60 (see FIG. 2). In the example shown in FIG. 1, the second impurity regions 80 and 82 are formed in respective regions sandwiching the gate electrode 60 in the direction orthogonal to the arrangement direction of the source / drain regions. Specifically, the second impurity region 80, the gate electrode 60, and the second impurity region 82 are sequentially provided in the direction along the gate width (channel width). The second impurity regions 80 and 82 have a second conductivity type (for example, p-type) different from that of the first impurity regions 70 and 72. The second impurity regions 80 and 82 are intended to reduce the leakage current of the semiconductor device.

  At least one of the end portions 62 and 64 of the gate electrode 60 is formed so as to cover the end surface of the semiconductor layer 40. In the gate electrode 60, both end portions 62 and 64 along the direction orthogonal to the arrangement direction of the source / drain regions may each cover the end surface of the semiconductor layer 40. Here, the end surface of the semiconductor layer 40 means a side surface when a surface of the semiconductor layer 40 in contact with most of the gate electrode 60 is an upper surface, and is not limited to a vertical surface but is an inclined surface. The boundary between the upper surface and the side surface may or may not be clear. Further, the end surface of the semiconductor layer 40 is not limited to a flat surface, and may be a smooth curved surface.

  For example, one end 62 of the gate electrode 60 may cover the first and second end faces 42 and 44 of the semiconductor layer 40. A second impurity region 80 is disposed between the first and second end portions 42 and 44. A first impurity region 70 that constitutes a source region is disposed on the first end face 42 so as to be adjacent to the side opposite to the second impurity region 80. Further, a first impurity region 72 constituting a drain region is disposed on the second end face 44 adjacent to the side opposite to the second impurity region 80. That is, each end face is adjacent to the first impurity region 70 (or the first impurity region 72) on one side and the second impurity region 80 on the other side.

  The other end portion 64 of the gate electrode 60 may also cover the first and second end surfaces 46 and 48 of the semiconductor layer 40. A second impurity region 82 is disposed between the first and second end portions 46 and 48. Other configurations correspond to the matters described for the end portion 62 described above.

  In the example shown in FIG. 1, the semiconductor layer 40 has a rectangular portion in which the first impurity regions 70 and 72 are formed, and at least the tip 41 of the convex portion extending from the rectangular portion with a shorter width than the rectangular portion ( A second impurity region 80 (second impurity region 82) is formed in a region including the tip 43). The end portion 62 (end portion 64) of the gate electrode 60 has a width larger than the tip 41 (tip 43) of the convex portion, avoiding the tip 41 (tip 43) of the convex portion in plan view of the semiconductor layer 40. It is extended by. According to this, since the width of the end portion 62 (end portion 64) of the gate electrode 60 is large, it is easy to form a contact portion (not shown) for connecting to the upper wiring. Note that the first and second end faces 42 and 44 (or the first and second end faces 46 and 48) may be two adjacent side faces constituting the corners, respectively (FIGS. 1 and 3). And FIG. 5).

  According to the present embodiment, the first and second impurity regions 70 and 80 adjacent to the end face (for example, the first end face 42) of the semiconductor layer 40 covered with the gate electrode 60 have different conductivity types. ing. Thereby, even when a parasitic channel is generated on the end face (for example, the first end face 42) of the semiconductor layer 40 due to concentration of the electric field, the electric field passes through the end face (for example, the first end face 42) of the semiconductor layer 40. The current can be cut off, and the leakage current can be effectively reduced. For example, in the example shown in FIG. 1, the first end face of the semiconductor layer 40 covered with the gate electrode 60 is provided between the source region (first impurity region 70) and the drain region (first impurity region 72). 42 and the 2nd end surface 44 are arrange | positioned in order. Therefore, among the current flowing between the source and the drain, the current passing through the end face of the semiconductor layer 40 can be cut off, and the leakage current can be effectively reduced.

  Next, a method for manufacturing a semiconductor device according to the present embodiment will be described. 6A to 6C are views for explaining a method for manufacturing a semiconductor device according to the present embodiment. 6A to 6C are cross-sectional views in the same direction as FIG. 2 described above.

  (1) First, as shown in FIG. 6A, an SOI substrate is prepared. The SOI substrate is configured by sequentially stacking a support substrate 20, an insulating layer 30, and a semiconductor layer 40.

  (2) Next, as shown in FIG. 6B, an element isolation region is formed. In the example shown in FIG. 6B, the form of the element isolation region is mesa type isolation, but is not limited to this, and may be known STI type isolation or LOCOS type isolation. In the case of mesa type separation, a plurality of island-shaped semiconductor layers 40 can be obtained by patterning the semiconductor layer 41. An element isolation region is formed between the semiconductor layers 40.

  (3) Thereafter, the surface of the semiconductor layer 40 is thermally oxidized, for example, to form the gate insulating layer 50, and the gate electrode 60 such as a polysilicon layer is formed on the gate insulating layer 50. At least one end of the gate electrode 60 (both ends 62 and 64 in FIG. 1) is an end face of the semiconductor layer 40 (first end 42 and 46 and second end 44 and 48 in FIG. 1). ) To cover. The gate electrode 60 can be patterned using a photolithography technique and an etching technique as necessary.

  (4) As shown in FIG. 6C, impurities of a specific conductivity type are implanted into the semiconductor layer 40 by ion implantation. Specifically, a first impurity region 70 constituting a source region and a first impurity region 72 constituting a drain region are formed by implanting a first conductivity type (for example, n-type) impurity, and a second impurity region 72 is formed. Second impurity regions 80 and 82 are formed by implanting impurities of a conductivity type (for example, p-type). The step of forming the second impurity regions 80 and 82 can be performed simultaneously with the step of forming the other source / drain regions of the second conductivity type (for example, p-type). By doing so, it is not necessary to provide an impurity implantation step anew, so that the process can be simplified. In addition, since the second impurity regions 80 and 82 are formed by implanting impurities having a conductivity type different from that of the first impurity regions 70 and 72, the impurity concentration is made higher so that the leakage current is as much as possible. Can be reduced.

  Alternatively, the second impurity regions 80 and 82 may have the same concentration as the semiconductor layer 40 before the impurity is implanted (for example, the same concentration as the channel region). That is, by forming the first conductivity type (for example, n-type) impurity regions 70 and 72 in the second conductivity type (for example, p-type) semiconductor layer 40, the second impurity regions 80 and 82 are indirectly connected. It may be formed automatically. Even in this case, the leakage current can be effectively reduced.

  The other details of the end face of the semiconductor layer 40 covered with the first impurity regions 70 and 72, the second impurity regions 80 and 82, and the gate electrode 60 and the positional relationship thereof are as described above.

(Second Embodiment)
FIG. 7 is a plan view of a semiconductor device according to the second embodiment to which the present invention is applied. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 7, and FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. In the semiconductor device 200 according to this embodiment, the configurations of the semiconductor layer 140 and the gate electrode 160 are different from those of the above-described embodiment.

  As shown in FIG. 1, the planar shape of the semiconductor layer 140 is not limited, and may be rectangular, for example. The semiconductor layer 140 may be an SOI layer. The semiconductor device 200 includes an SOI type semiconductor substrate in which a support substrate 120, an insulating layer 130, and a semiconductor layer 140 are sequentially stacked. A gate insulating layer 150 is provided over the semiconductor layer 140, and a gate electrode 160 is provided over the gate insulating layer 150. The semiconductor layer 140 is formed with first impurity regions 170 and 172 of the first conductivity type (for example, n-type) for constituting source / drain regions, respectively.

  In the present embodiment, one end 162 of the gate electrode 160 is formed so as to cover the first and second end surfaces 142 and 144 of the semiconductor layer 140 (see FIG. 9). In the example illustrated in FIG. 7, the end portion 162 of the gate electrode 160 includes first and second branch portions 162 a and 162 b. Both the first and second branch portions 162a and 162b extend to the outside of the semiconductor layer 140 and cover the first and second end faces 142 and 144 of the semiconductor layer 140, respectively. As shown in FIG. 7, the planar shape of the end portion 162 of the gate electrode 160 may be U-shaped. A second impurity region 180 is disposed between the first and second end faces 142 and 144. As shown in FIG. 8, the second impurity region 180 has a second conductivity type (for example, p-type), and the details thereof are as described in the first embodiment.

  The other end 164 of the gate electrode 160 may also cover the first and second end surfaces 146 and 148 of the semiconductor layer 140. Specifically, the end portion 164 of the gate electrode 160 has first and second branch portions 164a and 164b, whereby the first and second end surfaces 146 and 148 of the semiconductor layer 140 are respectively covered. . A second impurity region 182 is disposed between the first and second end faces 146 and 148. Other configurations correspond to the matters described for the end portion 162 of the gate electrode 160.

  Also in this embodiment, the same effects as those of the above-described embodiment can be obtained. Note that the method described in the above embodiment can be applied to the method for manufacturing a semiconductor device according to this embodiment, except that the patterning steps of the semiconductor layer 140 and the gate electrode 160 are different.

  Although the SOI type semiconductor substrate is used in the above example, the present invention can also be applied to a semiconductor device using a bulk type semiconductor substrate (including a semiconductor layer). In that case, the end surface of the semiconductor layer covered with the gate electrode may be a boundary surface with the element isolation region.

  The present invention is not limited to the above-described embodiments, and various modifications can be made. For example, the present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same purposes and results). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that achieves the same effect as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

FIG. 1 is a plan view of the semiconductor device according to the first embodiment of the present invention. 2 is a cross-sectional view taken along line II-II in FIG. 3 is a cross-sectional view taken along line III-III in FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. FIG. 5 is a cross-sectional view taken along line VV in FIG. 6A to 6C are views showing a method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 7 is a plan view of a semiconductor device according to the second embodiment of the present invention. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 9 is a cross-sectional view taken along line IX-IX in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 40 ... Semiconductor layer 42, 46 ... 1st end surface 42, 48 ... 2nd end surface 50 ... Gate insulating layer 60 ... Gate electrode 62, 64 ... End part 70, 72 ... 1st impurity region 80, 82 ... 2nd 140. Semiconductor layer 150 ... Gate insulating layer 160 ... Gate electrode 162, 164 ... End 162a, 164a ... First branch 162b, 164b ... Second branch 180, 182 ... Second impurity region

Claims (6)

A semiconductor layer;
A gate insulating layer provided above the semiconductor layer;
A gate electrode provided above the gate insulating layer;
A first impurity region formed in a region exposed from the gate electrode in the semiconductor layer and constituting a source region or a drain region;
A second impurity region formed in a region exposed from the gate electrode in the semiconductor layer and having a conductivity type different from that of the first impurity region;
Including
At least one end of the gate electrode covers the end surface of the semiconductor layer,
The semiconductor device, wherein the first impurity region is disposed adjacent to one of the end surfaces of the semiconductor layer, and the second impurity region is disposed adjacent to the other of the end surfaces of the semiconductor layer. The semiconductor device according to claim 1,
At least one end of the gate electrode covers the first and second end faces of the semiconductor layer,
The second impurity region is disposed between the first and second end faces of the semiconductor layer;
The first impurity region constituting the source region is disposed on the first end face of the semiconductor layer adjacent to the side opposite to the second impurity region,
The semiconductor device, wherein the first impurity region constituting the drain region is disposed on the second end face of the semiconductor layer adjacent to the side opposite to the second impurity region. The semiconductor device according to claim 2,
At least one end portion of the gate electrode includes a first branch portion that covers the first end surface of the semiconductor layer, and a second branch portion that covers the second end surface of the semiconductor layer. A semiconductor device. The semiconductor device according to claim 2,
The second impurity region is formed in a region including at least a tip of a convex portion extending with a shorter width than the rectangular portion from the rectangular portion in which the first impurity region is formed,
At least one end of the gate electrode is extended by a width larger than the width of the tip of the projection, avoiding the tip of the projection. The semiconductor device according to any one of claims 1 to 4,
The semiconductor device is a semiconductor device which is an SOI (Silicon on Insulator) layer. (A) forming a gate insulating layer above the semiconductor layer;
(B) forming a gate electrode above the gate insulating layer and having at least one end covering the end face of the semiconductor layer;
(C) In the region exposed from the gate electrode in the semiconductor layer, a first impurity region constituting a source region or a drain region, and a second impurity region having a conductivity type different from that of the first impurity region are formed. Forming,
Including
In the step (c), the first impurity region is formed at a position adjacent to one of the end faces of the semiconductor layer, and the second impurity region is formed at a position adjacent to the other end face of the semiconductor layer. A method for manufacturing a semiconductor device.

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