JP5172264B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a MIS field effect transistor having a three-dimensional structure.

  Currently, it is a type of MIS field effect transistor (hereinafter referred to as MISFET) having a three-dimensional structure. A single crystal silicon layer of an SOI substrate is cut into a strip shape to form a protruding region, and a gate electrode is formed in the protruding region. Double gate type Fully Depleted-SOI MOSFETs have been proposed that are three-dimensionally crossed and have the upper and side surfaces of the protruding regions as channels (see, for example, Non-Patent Documents 1 and 2 and Patent Documents 1 and 2).

  The MOSFET is promising as an element to be used in future LSIs because it realizes a high current driving capability, is more space-saving in the gate width W direction than the conventional one, and suppresses the short channel effect.

  FIG. 13A to FIG. 13C are a layout view and a cross-sectional view showing the configuration of the conventional MOSFET described above. An insulating film 102 is formed on the semiconductor substrate 101, and a silicon fin layer 103 is formed on the insulating film 102. On the silicon fin layer 103, a source 105 and a drain 106 are formed on the left and right sides through an insulating film 104, respectively.

  Further, an insulating film 108 for insulating the source 105 and drain 106 and the gate electrode 107 is formed on the source 105 and drain 106. An insulating film 109 for insulating the source 105 and drain 106 from the gate electrode 107 is formed on the side surface in the groove between the source 105 and drain 106. Further, a gate electrode 107 is formed between these insulating films 109.

  However, since it is necessary to use an expensive SOI substrate to realize this element, an increase in cost is inevitable for an LSI that is premised on mass production. Further, there is a concern about reliability deterioration due to the quality of the SOI substrate.

  Further, an element that performs the same operation as the element having the SOI structure shown in FIGS. 13A to 13C can be formed using a normal bulk substrate. An element using a bulk substrate has a substrate projection serving as an element region, and is realized by selectively oxidizing the lower portion of the element region.

  FIG. 14 is a perspective view of an element using the above-described conventional bulk substrate, and FIG. 15 is a sectional view of the element. As shown in FIGS. 14 and 15, an insulating film 112 is formed on the semiconductor substrate 111. A source 113 and a drain 114 are formed on the insulating film 112, and a gate electrode 116 is formed on the semiconductor layer 110 between the source 113 and the drain 114 so as to cross three-dimensionally through a gate insulating film 115. Has been.

  However, in the elements shown in FIGS. 14 and 15, when the element region is miniaturized, it is difficult to control the thickness of the oxide film, and distortion due to high-temperature thermal oxidation may affect the element performance. Is done.

  Further, although common to the two elements described above, if an SOI structure is formed, the thermal conductivity of the insulating film existing below the silicon layer is smaller than that of crystalline silicon, and therefore, Joule heat generated by the drain current Id. It is known that heat generation due to the phenomenon occurs (self-heating) and causes the drain current Id to deteriorate. Therefore, these elements shown in FIG. 13, or FIG. 14 and FIG. 15 are not necessarily in a state where the performance can be sufficiently exerted for use in an LSI or the like.

  In the SOI device, particularly in an n-channel field-effect transistor, the hole generated by impact ionization in the channel loses the escape field and accumulates in the lower part of the channel region layer, so-called a substrate floating effect. cause. For this reason, there is a concern about the influence of the substrate floating effect on the operation of an element that switches at a high speed.

  Further, as a MISFET having a three-dimensional structure using a bulk substrate, there is a MISFET described in US Pat. No. 5,844,278. In this MISFET, a bulk substrate is processed into a projection shape to form a substrate projection (projection shape), and the substrate projection has a gate electrode structure as in the conventional example described above.

  16 and 17 are cross-sectional views in the manufacturing process of the MISFET.

  As shown in FIG. 16, a protruding region 121A is formed on the semiconductor substrate 121, and a gate insulating film 122 is formed on the protruding region 121A. An insulating film 123 is formed on both sides of the protruding region 121A, and a mask material 124 is formed on the insulating film 123.

  In the MISFET, in order to prevent punch-through that occurs deep in the source / drain diffusion layer, ion implantation is performed in the structure shown in FIG. 16, and a high-concentration impurity region 125 is formed at the bottom of the protruding region 121A. Yes.

  Further, as shown in FIG. 17, the source / drain impurity diffusion layer 126 formed on the upper and side surfaces of the protruding region 121A is formed with a shallow depth so that the upper and side surfaces are almost independent of each other. It is characterized by operation.

  In the MISFET, not the SOI structure but the protruding region 121A and the lower semiconductor substrate 121 are connected to each other, so that the above-described heating (self-heating) due to Joule heat and the substrate floating effect are reduced. There is.

However, when the gate length is reduced (for example, 0.1 μm or less) and it is intended to operate as a fully depleted element, it becomes difficult to realize the structure shown in FIGS. 16 and 17 in a process. come. Therefore, it is desired to develop an element having a new structure corresponding to a generation having such a gate length of 0.1 μm or less.
JP-A-2-263473 Japanese Patent Publication No. 2-2768719 D. Hisamoto et al .: IEDM 1998 P.1032 X.Huang et al.:IEDM 1999 P.67

  Therefore, the present invention has been made in view of the above problems, and even when the gate length is miniaturized, it can be operated as a fully depleted element, and the heat generation and substrate floating effect due to Joule heat can be reduced. An object is to provide a semiconductor device.

The semiconductor device according to the first embodiment is formed on a first conductivity type semiconductor substrate, formed with a protrusion having a first conductivity type semiconductor layer, and at least a side surface of the protrusion via a gate insulating film. A gate electrode, a source region and a drain region of the second conductivity type formed in the semiconductor layer of the protrusion so as to sandwich the gate electrode, and the semiconductor substrate formed on the semiconductor substrate so as to sandwich the protrusion. First and second element isolation insulating films, a first impurity region of a first conductivity type formed in the semiconductor substrate under the first element isolation insulating film, and the semiconductor under the second element isolation insulating film A second impurity region of a first conductivity type formed in the substrate, wherein the first impurity region and the second impurity region are formed by ion implantation of impurities, respectively, and the impurity is the semiconductor substrate under the protrusion Diffuse in It said first and second impurity regions are connected within said semiconductor substrate of said projections subordinates, the source region and the drain region and the first and second impurity regions through the semiconductor layer directly below are arranged, The height and width direction perpendicular to the channel length of the protrusion formed on the side surface of the gate electrode are orthogonal to the channel length of the protrusion where the source region and drain region are formed. It is characterized by being shorter than the height and the length in the width direction.

  According to the present invention, it is possible to provide a semiconductor device that can be operated as a fully depleted element even when the gate length is miniaturized and that can reduce heat generation due to Joule heat and a substrate floating effect. .

  A three-dimensional MIS field effect transistor (MISFET) will be described below as a semiconductor device according to an embodiment of the present invention with reference to the drawings.

[First Embodiment]
FIG. 1 is a perspective view showing the configuration of the semiconductor device according to the first embodiment of the present invention.

  As shown in FIG. 1, a p-type silicon semiconductor substrate 11 is formed with a substrate protrusion 11A formed by processing this substrate into a protrusion shape. The substrate protrusion 11A is an element region, and the semiconductor substrate 11 on both sides of the substrate protrusion 11A is an element isolation region. An element isolation insulating film 12 is formed on the semiconductor substrate 11 in the element isolation region. Here, for example, the thickness of the substrate protrusion 11A (corresponding to the thickness in the direction orthogonal to the channel length) is about 0.1 μm or less, and the height of the substrate protrusion 11A from the substrate 11 is 0.5 μm to It is about 1.0 μm or less. Note that the height is not limited to about 1.0 μm or less, and may be higher if possible in terms of manufacturing technology.

  Further, gate insulating films 13 are formed on both side surfaces and the upper surface of the substrate protrusion 11A. That is, the gate insulating film 13 is formed so as to cover the substrate protrusion 11A. The gate insulating film 13 is made of, for example, a silicon oxide film formed by thermal oxidation.

  A gate electrode 14 is formed on a part of the gate insulating film 13 covering the substrate protrusion 11A, and a gate electrode 14 is also formed on a part of the element isolation insulating film 12. A source diffusion layer 15 and a drain diffusion layer 16 having a conductivity type (n-type) opposite to the conductivity type of the substrate are formed in both front and back side surfaces of the substrate protrusion 11A in the drawing. The source diffusion layer 15 and the drain diffusion layer 16 are formed in a self-aligned manner using the gate electrode pattern as a mask after the formation of the gate electrode 14, and are formed on both side surfaces of the substrate protrusion 11 </ b> A except under the gate electrode 14. Then, phosphorus (P) or arsenic (As) is introduced by ion implantation.

  Here, the source diffusion layer 15 and the drain diffusion layer 16 are formed only on both side surfaces of the substrate protrusion 11A. However, the source diffusion layer 15 and the drain diffusion are also formed on the upper surface of the substrate protrusion 11A as necessary. The layer 16 may be formed, and the diffusion layers 15 and 16 in the upper surface may be in contact with the wiring layer.

  Further, a high-concentration impurity region 17 having the same conductivity type (p-type) as that of the substrate is formed in the semiconductor substrate 11 below the element isolation insulating film 12 and the substrate protrusion 11A. That is, the impurity regions 17 formed by ion implantation in the semiconductor substrate 11 under the element isolation insulating film 12 on both sides of the substrate protrusion 11A are connected in the semiconductor substrate 11 under the substrate protrusion 11A.

  The element isolation insulating film 12 is provided with a contact 18 for obtaining an electrical connection between the semiconductor substrate 11 and a wiring layer (not shown). In the formation of the contact 18, the impurity region 17 is formed in the upper layer of the semiconductor substrate 11 in contact with the contact. Therefore, the contact 18, the semiconductor substrate 11, and the impurity 18 are not implanted again when the contact 18 is formed. Ohmic contact can be obtained between the two.

  The semiconductor device of this embodiment shown in FIG. 1 realizes a function equivalent to that of the MISFET using the conventional SOI substrate described above by the MISFET using the bulk substrate. Since the gate electrode 14 requires a contact region (not shown) connecting the gate electrode 14 and the wiring layer, the gate electrode 14 is also used in the element isolation region other than the active region (channel portion and source / drain portion) of the MISFET. There is an overlapping region between the electrode 14 and the substrate 11.

  Further, in this semiconductor device, in order to maintain the insulation between the elements, the short channel effect caused by the parasitic MISFET is suppressed, and the element isolation region is formed in a portion where the gate electrode 14 and the lower substrate 11 overlap. It is necessary to ensure that the parasitic MISFETs are always turned off within the actual operating voltage.

  Therefore, here, the impurity region 17 is formed by doping the substrate of the element isolation region including the portion immediately below the gate electrode 14 with an impurity of a conductivity type (p-type) opposite to the carrier in the channel. Further, a thick element isolation insulating film 12 is formed on the substrate 11 in the element isolation region, and the thickness of the insulating film that effectively acts as the gate insulating film is increased at the overlapping portion of the gate electrode 14 and the substrate 11. Yes. Thus, by increasing the threshold voltage of the parasitic MISFET formed in the element isolation region, the parasitic MISFET is always turned off. For example, when an n-channel MISFET is formed, boron (B) is introduced into the element isolation region, and the impurity region 17 becomes a p + type region as described above.

  Here, if the thickness of the substrate protrusion 11A (thickness in the direction orthogonal to the channel length) is made narrower than the width Wd of the maximum depletion layer formed in the substrate protrusion 11A when the gate voltage is applied, During operation, the entire region in the substrate protrusion 11A is filled with the depletion layer. As a result, the MISFET of this embodiment operates in the same manner as a fully depleted SOI element. In this case, even if the impurity concentration in the substrate projection 11A is low, the potential in the channel is controlled by the gate electrodes 14 on both sides of the substrate projection 11A, so that it is compared with a conventional planar MISFET. It is possible to easily suppress the short channel effect.

  Furthermore, when the operation equivalent to that of the SOI element is performed, the impurity concentration of the substrate protrusion 11A can be set low, and as a result, the vertical electric field formed by the substrate impurity is smaller than that of a normal planar MISFET. Thus, the carrier mobility expressed as a function of the vertical electric field is larger than that of the planar element. Therefore, in the MISFET of this embodiment, even when the operation voltage is the same and the gate width W is equivalent, a high current driving capability can be obtained as compared with the planar element.

  Further, when the thickness of the substrate protrusion 11A becomes thinner, the impurities ion-implanted perpendicularly to the substrate 11 in the element isolation region diffuse in the lateral direction, so that all the substrate 11 under the substrate protrusion 11A is doped. Will come to be. That is, the impurity regions 17 on both sides are connected in the substrate 11 below the substrate projection 11A, and the impurity regions 17 are also formed below the substrate projection 11A. Therefore, in the semiconductor device of this embodiment, since the impurity can be doped not only in the element isolation region but also in the lower part of the substrate projection 11A, the element isolation resistance can be improved. That is, the occurrence of punch-through of elements can be prevented, and the adjacent elements can be prevented from being turned on erroneously.

  In addition, the channel portion is not separated from the lower substrate 11 by an insulating film having a low thermal conductivity while operating in the same manner as a fully depleted SOI device, so that the heat dissipation characteristics can be improved, resulting from Joule heat. Current degradation due to self-heating can be minimized.

[Second Embodiment]
In general, in the case of a MISFET using an SOI substrate, when an extremely short channel element is formed while reducing the impurity concentration of the substrate, punch-through occurs between the source and the drain due to the extension of the depletion layer from the drain side. There is a possibility that. In order to suppress the short channel effect, the elongation of this depletion layer must be controlled.

  In the case of a fully depleted planar MISFET using a conventional SOI substrate, the occurrence of punch-through is suppressed by making the silicon film forming the channel very thin. However, when the gate length becomes 100 nm or less, it is necessary to make the silicon film thinner than that, and the difficulty in element formation increases.

  Here, as shown in FIG. 1, a case is considered in which the height of the substrate protrusion of the transistor is increased and the channel width W is increased to effectively increase the current flowing area.

  In this case, the transistor portions formed on both side surfaces of the substrate protrusion are relatively advantageous for suppressing the short channel effect as a thin film element that performs the same operation as the SOI element. This is because the thickness of the silicon layer serving as the channel is defined by the width of the substrate protrusion, and the double gate structure is advantageous.

  On the other hand, for the transistor formed on the upper surface of the substrate protrusion, a part of the channel is connected to the drain due to the influence of the impurity diffusion layer in the drain formed on the side surface of the substrate protrusion. When the depth is increased, the effective SOI film thickness appears to be large (in the vertical direction).

  As a result, although depending on the source / drain structure, the extension of the depletion layer on the drain side increases, and punch-through between the source and the drain is likely to occur. This is particularly remarkable in an element having a side surface (substrate protrusion) height of 0.1 μm or more. For this reason, if the apparent current driving force is increased by compensating the channel width W by increasing the height of the substrate protrusion, punch-through is more likely to occur.

  The conventional example shown in FIG. 16 attempts to compensate for this defect by optimizing the impurity concentration profile of the substrate. However, in this case as well, when the gate width W is increased, that is, when the height of the substrate protrusion is increased, it is difficult to dope impurities into the entire region where punch-through can occur, and the substantial upper limit of the gate width W is For example, it is determined within a depth range where impurities can be doped by an ion implantation technique.

  Therefore, in the second embodiment, in order to prevent punch-through between the source and the drain when an extremely fine gate electrode is formed under such an element structure, the uppermost surface portion (upper surface) of the substrate protrusion is used. It is proposed that the channel of the MISFET should not be formed in the portion), and only the side surface portion of the substrate protrusion should be used as the channel. That is, the basic feature of the semiconductor device according to the second embodiment of the present invention is that, unlike the conventional example, the uppermost portion of the substrate protrusion is not used as a channel.

  There are several structures for preventing the channel from being formed on the upper surface of the substrate protrusion. In FIG. 2, the upper surface is doped with an impurity having a conductivity type opposite to the carriers in the channel. In FIG. An example in which the thickness of the gate oxide film formed on the upper surface portion of the portion is effectively increased so that the channel is not formed within the actual operating voltage range. Further, in FIG. 4, the gate electrode is the upper surface of the substrate protrusion. An example is shown in which a channel is not formed so as not to overlap with the portion. Moreover, you may combine the structure shown in FIG.2, FIG3 and FIG.4.

  Hereinafter, the examples shown in FIGS. 2, 3 and 4 will be described in detail.

  FIG. 2 is a perspective view showing the configuration of the semiconductor device according to the second embodiment.

  As shown in FIG. 2, an impurity region 21 doped with a conductivity type (p-type) impurity opposite to the carrier in the channel is formed in the upper layer portion of the substrate protrusion 11A. Other configurations are the same as those of the first embodiment described above.

  A method of manufacturing a semiconductor device having such a structure is performed as follows, for example. First, when forming the substrate protrusion 11A, an insulating film as a cap film, for example, a silicon nitride film is patterned on the semiconductor substrate 11. Using this silicon nitride film as a mask, the semiconductor substrate 11 is cut into a strip shape by reactive ion etching (hereinafter referred to as RIE) to form a substrate protruding portion 11A protruding at a predetermined width and height.

After the substrate protrusion 11A is formed, impurities are introduced vertically into the upper surface of the substrate protrusion 11A by ion implantation. In this case, for example, in the case of an n-channel MISFET, the impurity ion implantation is performed with boron (B) at an acceleration voltage of 15 keV and a dose of about 5 × 10 ¹³ cm ⁻² or more.

  Subsequently, a gate insulating film 13 made of a silicon oxide film is formed on both side surfaces and the upper surface of the substrate protrusion 11A by thermal oxidation. A polysilicon film is deposited on the gate insulating film 13 and patterned to form a gate electrode 14.

  Further, an impurity (for example, P or As) is introduced into both side surfaces of the substrate protrusion 11A except under the gate electrode 14 by ion implantation to form the source diffusion layer 15 and the drain diffusion layer 16.

  FIG. 3 is a perspective view showing a configuration of a semiconductor device according to a modified example of the second embodiment.

  As shown in FIG. 3, an insulating film 22 is formed on the upper surface of the substrate protrusion 11A. The insulating film 22 may be used as it is without peeling off the cap film (for example, silicon nitride film) used when forming the substrate protrusion 11A. A silicon oxide film may be separately formed as the insulating film 22. Other configurations are the same as those of the first embodiment described above.

  In the semiconductor device having the above-described configuration, the insulating film between the gate electrode 14 and the substrate protrusion 11A is thick on the upper surface portion of the substrate protrusion 11A, and a channel is not formed within the actual voltage range.

  A method of manufacturing a semiconductor device having such a structure is performed as follows, for example. First, when forming the substrate protrusion 11 </ b> A, the insulating film 22 as a cap film, for example, a silicon nitride film is patterned on the semiconductor substrate 11. Using this insulating film 22 as a mask, RIE is performed to form a protruding substrate protrusion 11A.

  Subsequently, the gate insulating film 13 made of a silicon oxide film is formed on both side surfaces of the substrate protrusion 11A by thermal oxidation without peeling off the insulating film 22. A polysilicon film is deposited on the substrate protrusion 11A having such a structure and patterned to form the gate electrode 14.

  Further, an impurity (for example, P or As) is introduced into both side surfaces of the substrate protrusion 11A except under the gate electrode 14 by ion implantation to form the source diffusion layer 15 and the drain diffusion layer 16.

  FIG. 4 is a perspective view showing a configuration of a semiconductor device according to another modification of the second embodiment.

  As shown in FIG. 4, the gate electrode is not formed on the upper surface of the substrate projection 11A, and the gate electrodes 14A and 14B are formed only on the side surfaces. That is, two gate electrodes 14A and 14B are formed on both side surfaces of the substrate protrusion 11A in a self-aligning manner so as to sandwich the substrate protrusion 11A, and these two gate electrodes 14A and 14B It is arranged on a straight line orthogonal to the length. In this semiconductor device, since the gate electrode is divided, it is necessary to provide a contact with each of the two divided gate electrodes 14A and 14B. Other configurations are the same as those of the first embodiment described above.

  The semiconductor device having such a structure can be used as a double-gate FET mode in which the same bias is applied to the two gate electrodes 14A and 14B, and different voltages are applied to the two gate electrodes 14A and 14B, respectively. It is also possible to use it.

  For example, as an example in which different voltages are applied to the two gate electrodes 14A and 14B, the gate voltage on the channel side is given to one of the two gate electrodes 14A and 14B, and the substrate potential is given to the other one, It can be used as a back gate FET mode in which a potential different from that of the channel side gate electrode is applied. Although the fully depleted device as shown in FIG. 2 cannot change the threshold voltage after manufacturing, the semiconductor device shown in FIG. 4 controls the threshold voltage when used in the back gate FET mode. be able to.

  Using a plurality of semiconductor devices shown in FIG. 4, a double-gate FET mode element that applies the same bias to the two gate electrodes 14A and 14B, and one of the two gate electrodes 14A and 14B is connected to the channel side. A back gate FET mode element that applies a gate voltage and applies a potential different from the channel-side gate voltage to the remaining one as a substrate potential can be mixed by changing wiring and power supply.

  The method for manufacturing the semiconductor device having the structure shown in FIG. 4 is performed as follows, for example. First, when forming the substrate protrusion 11A, an insulating film as a cap film, for example, a silicon nitride film is patterned on the semiconductor substrate 11. Using this silicon nitride film as a mask, RIE is performed to form a protruding substrate protrusion 11A.

  Subsequently, a gate insulating film 13 made of a silicon oxide film is formed on both side surfaces of the substrate protrusion 11A by thermal oxidation without peeling off the silicon nitride film. A polysilicon film is deposited on the substrate protrusion 11A having such a structure and patterned to form the gate electrode 14.

  Thereafter, the polysilicon film existing on the upper surface of the substrate protrusion 11A is polished by CMP, or the polysilicon film is etched by RIE. Further, the insulating film present on the upper surface of the substrate protrusion 11A is removed. Further, an impurity (for example, P or As) is introduced into both side surfaces of the substrate protrusion 11A except under the gate electrode 14 by ion implantation to form the source diffusion layer 15 and the drain diffusion layer 16. In this case, it is possible to form a self-aligned double-gate MISFET that performs the same operation as the SOI element.

  Any of these semiconductor devices of the second embodiment can operate in the same manner as a fully depleted MISFET using an SOI substrate, and the other configurations are the same as those of the first embodiment. It is.

  Further, preventing the channel portion from being formed on the upper surface portion of the substrate projection 11A means that the thickness of the substrate projection 11A must be reduced in the future, and that the substrate projection can be obtained in order to obtain a current driving force. A book that does not cause much damage under the condition that the height (length in the vertical direction) of the portion 11A must be about 1 μm or more, but rather does not actively use the upper surface portion of the substrate protrusion 11A. It is clear that the features of the invention provide an effective means for suppressing short channel effects.

  In order to increase the carrier mobility, when the transistor is operated only on the side surface of the substrate projection 11A, the side surface is the (100) plane and the channel direction is also [100] in the case of silicon. is necessary.

[Third Embodiment]
In the conventional MISFET having the three-dimensional structure shown in FIGS. 13 and 14, the channel portion needs to be thinned in order to realize a fully depleted SOI device. If the film thickness is 50 nm or less, it is advantageous in forming a shallow junction when forming a so-called source / drain diffusion layer, while the source / drain diffusion layer of the substrate is conventional. Compared to the flat type MISFET, the thickness is very thin. For this reason, the parasitic resistance of the source / drain portion is increased, and as a result, the current driving capability is expected to deteriorate.

  Therefore, in the third embodiment, only the channel region and the vicinity of its end as shown in FIGS. 5 and 6 (a) to 6 (d) are thinned, and other sources / drains are formed. The proposed MISFET is characterized in that the increase in parasitic resistance is minimized by using a thick film substrate protrusion which is not thinned.

  FIG. 5 is a perspective view showing the configuration of the semiconductor device according to the third embodiment. 6A is a plan view of the semiconductor device, FIG. 6B is a side view of the semiconductor device, FIG. 6C is a cross-sectional view taken along line 6C-6C in the plan view, and FIG. (D) is sectional drawing along the 6D-6D line | wire in the said top view.

  The manufacturing method of the semiconductor device having the structure shown in FIGS. 5 and 6A to 6D is performed, for example, as follows. The element shape varies somewhat depending on the manufacturing method.

  First, the silicon semiconductor substrate 11 is cut out in accordance with the protruding region of the thick semiconductor substrate, and a protruding substrate protruding region having a thickness (thickness in a direction orthogonal to the channel length) of about 0.15 μm to 0.20 μm is formed. Next, an insulating film (for example, a silicon nitride film) serving as a mask for forming the gate electrode is deposited and patterned by using a lithography method to form a groove for forming the gate electrode in the silicon nitride film.

  Here, when the substrate 11 is oxidized by about 50 nm to 100 nm, it becomes a shape including a bird's beak equivalent to the shape of an oxide film used for so-called LOCOS element isolation. By selectively removing the oxide film, the source / drain is formed. The portion is thick, and a thin strip-shaped substrate protrusion 31A can be formed in the channel portion and a part of the diffusion portion in the vicinity of the channel portion.

  Thereafter, the gate insulating film 13 is formed on the upper surface and both side surfaces of the thinned substrate projection 31A in the gate electrode formation mask. Further, for example, a polysilicon film is embedded on the gate insulating film 13 in the gate electrode formation mask, and the excess polysilicon film is polished by CMP to form the gate electrode 14.

  Next, the gate electrode forming mask material (silicon nitride film) is removed, and then ion implantation or vapor phase doping is performed on both side surfaces (source / drain formation portions) of the substrate protrusion 31A excluding the channel region. As a result, a deep and low resistance source diffusion layer 15 and drain diffusion layer 16 are formed. At the same time, a shallow junction is formed in the diffusion portion near the end of the channel region because the substrate is thin. When the doping conditions need to be adjusted between the diffusion part and the deep junction part, it is possible to form a deep junction by forming a gate side wall after forming a shallow junction in the diffusion part as in the case of the conventional planar MISFET. It is. A similar structure can also be formed by applying an elevated source / drain structure using an epitaxial technique after forming a transistor on the substrate protrusion.

  In this embodiment, the source diffusion layer 15 and the drain diffusion layer 16 are formed only on both side surfaces of the substrate protrusion 31A. However, the source diffusion layer 15 is also formed on the upper surface of the substrate protrusion 31A as necessary. The drain diffusion layer 16 may be formed, and the diffusion layers 15 and 16 in the upper surface may be in contact with the wiring layer.

[Fourth Embodiment]
As described above, in order to manufacture a MISFET that performs the same operation as an SOI element having a fine gate, it is necessary to form a channel portion with a very thin silicon film regardless of the conventional type or the three-dimensional type. However, in some cases, with the structure described so far, it is expected that processing of a semiconductor substrate, particularly processing by lithography and RIE will become very difficult in the future.

  Therefore, in the fourth embodiment, a strip-shaped substrate protrusion is formed to be relatively thick (for example, about 0.5 μm to 1.0 μm in thickness), and performs the same operation as an SOI element. Propose. The fourth embodiment is characterized in that after an intrinsic pillar is formed as a substrate protrusion, a stacked channel structure in which a p + layer, an n− layer, and a p− layer are stacked in this order is formed.

  FIG. 7 is a perspective view partially showing the configuration of the semiconductor device of the fourth embodiment. FIG. 7 shows a channel portion, and the protrusions on which the source / drain diffusion layers are formed are thick as shown in FIGS.

  First, when forming the substrate protrusion 41A, an insulating film as a cap film, for example, a silicon nitride film is patterned on the p-type silicon semiconductor substrate 11. Using this silicon nitride film as a mask, the semiconductor substrate 11 is cut into a strip shape by RIE to form an intrinsic pillar protruding with a predetermined width and height. A p + layer 42, an n− layer 43, and a p− layer 44 are sequentially formed on the side surfaces and the upper surface of the pillar, that is, around the pillar by selective epitaxial growth, to form the substrate protrusion 41A.

  Further, the gate insulating film 13 made of a silicon oxide film is formed on both side surfaces and the upper surface of the substrate protrusion 41A by thermal oxidation. A polysilicon film is deposited on the gate insulating film 13 and patterned to form a gate electrode 14.

  FIG. 8 is a perspective view partially showing a configuration of a semiconductor device of a modified example of the fourth embodiment. FIG. 8 shows a channel portion, and the protrusions on which the source / drain diffusion layers are formed are thick as shown in FIGS.

  First, when forming the substrate protrusion 41B, an insulating film as a cap film, for example, a silicon nitride film is patterned on the semiconductor substrate 11. Using this silicon nitride film as a mask, the semiconductor substrate 11 is cut into a strip shape by RIE to form an intrinsic pillar protruding with a predetermined width and height.

  Subsequently, an impurity (for example, B) is introduced into the substrate 11 in the element isolation region by ion implantation to form the p + -type impurity region 17, and at the same time, the impurity is also introduced into the pillar to form a p + layer 42. . Thereafter, an element isolation insulating film (for example, a silicon oxide film) 12 is formed on the substrate 11 in the element isolation region.

  Further, an n− layer 43 and a p− layer (channel layer) 44 are grown on the p + layer 42 by selective epitaxial growth so as to surround the p + layer 42. Thereby, the board | substrate protrusion part 41B is formed.

  In the semiconductor device shown in FIG. 8 described above, the p + type impurity region 17 is formed on the substrate 11 in the element isolation region at a stage where the pillar is still thin, that is, immediately after the pillar is formed. It diffuses under the portion 41B and comes into contact with the p + layer 42 of the innermost pillar. Thus, if a potential is applied to the p + type impurity region 17 of the substrate 11 in the element isolation region, it is possible to apply a potential to the p + layer 42 inside the substrate protrusion 41B, and this device is used as a four-terminal element. It can be operated.

  In the semiconductor device of the fourth embodiment shown in FIG. 7 or 8, the thickness and impurity concentration are set so that the n− layer 43 is completely depleted regardless of the gate voltage, and the p + layer 42 and the p− layer are used. If the setting of the impurity concentration of 44 is optimized, the p-layer 44 forming the channel and the substrate 11 can be electrically separated by the depletion layer formed in the n− layer 43. As a result, it is possible to realize an element structure equivalent to a MISFET using an SOI substrate. In this case, in order to realize a fully depleted device, a structure equivalent to the fully depleted device can be obtained by reducing the thickness of the channel layer (p− layer 44).

  Furthermore, since the central pillar of the substrate protrusions 41A and 41B can be formed to an arbitrary thickness, the operation region can be made equivalent to the thin film SOI, and the substrate protrusions 41A and 41B are formed without difficulty in processing the substrate. The dimension area which can be used can be used, and the difficulty in element production can be reduced.

  The portions shown in FIGS. 7 and 8 are enlarged views of only the channel portion directly under the gate. In the source / drain portion, the source / drain diffusion layer and the n− layer 43 need not be in contact with each other. It is. Therefore, the source / drain structure uses an elevated source / drain structure using selective epitaxial growth similar to that shown in FIGS. 5 and 6, or a halo structure (pocket structure) for the source / drain. It is good (not shown here). By using these, the contact between the n− layer 43 and the source / drain diffusion layer (n + layer) can be easily prevented, and the channel structure shown in FIG. 7 or FIG. 8 can be realized.

  In the fourth embodiment, an n-channel field effect transistor has been described. However, the present invention can also be applied to a p-channel field effect transistor by reversing the conductivity type of impurities. In addition, a high-performance CMOS SOI device can be realized by dividing the doping of the well and channel portions and optimizing the halo structure.

[Fifth Embodiment]
In the above-described three-dimensional MISFET, when the channel width W is increased, that is, the height of the substrate protrusion is increased, the difference in height between the contact region of the gate electrode and the contact region of the source / drain diffusion layer increases. There may be a problem in the future that it becomes difficult to form a contact using a process. For example, when the channel width W is about 2 μm, the height of the substrate protrusion must be about 1 μm. In this case, the thickness of the polysilicon serving as the gate is set to the height of the substrate protrusion due to processing problems. It is impossible to increase the thickness to the same extent. This is because if the thickness of the polysilicon is increased to the same level as the height of the substrate protrusion, the aspect ratio increases and cannot be cut by RIE.

  The actual deposited thickness of polysilicon is up to about 200 nm, and a step of about 800 nm is formed between the upper surface of the substrate protrusion and the upper surface of the gate electrode. For example, in order to form a fine contact hole of about 150 nm × 150 nm, since the step is large, a hole having a very large aspect ratio (up to 5.3 + interlayer film) must be formed by RIE. At present, it is very difficult due to the characteristics of lithography and RIE.

  Therefore, in the fifth embodiment, the above-described three-dimensional MISFET has a gate electrode shape as shown in FIG. 9 and includes a contact region of the source / drain diffusion layer of the substrate protrusion and a contact region of the gate electrode. The difference in height is within 200 nm.

  FIG. 9 is a perspective view showing the configuration of the semiconductor device according to the fifth embodiment.

  First, the p-type silicon semiconductor substrate 11 is cut out to form a protruding substrate protrusion having a thickness (thickness in a direction orthogonal to the channel length) of about 2 μm. Next, an insulating film (for example, a silicon nitride film) serving as a mask for forming the gate electrode is deposited, and the silicon nitride film is etched by lithography and RIE to form a groove for forming the gate electrode.

  Here, when the substrate 11 in the groove is oxidized by about 50 nm to 100 nm, it becomes a shape containing a bird's beak equivalent to the shape of an oxide film used in so-called LOCOS element isolation, and by selectively removing the oxide film, As shown in FIG. 9, it is possible to form a substrate protrusion 51A having a thick source / drain part and a thin part of the diffusion part and the channel part.

  Thereafter, the gate insulating film 13 is formed on both side surfaces and the upper surface of the substrate protrusion 51A in the gate electrode formation mask. Further, for example, a polysilicon film is embedded in the gate electrode formation mask, and the excess polysilicon film is polished by CMP to form the gate electrode 54.

  In this way, if the thickness of the polysilicon film that is the gate electrode 54 is initially relatively large, the gate electrode 54 can be formed into a shape having a height as shown in FIG. The level difference between the contact position on 54 and the contact position on the source / drain diffusion layers 15 and 16 can be reduced.

  Compared to the formation of a fine gate pattern on the element isolation insulating film 12, there is a space in the gate width direction, unlike the case of the contact hole, even when the step between the substrate protrusion 51A and the insulating film 12 is large. Easy.

  With the structure and manufacturing method of the semiconductor device shown in FIG. 9, the contact hole aspect ratio can be reduced, and the contact hole can be simultaneously opened on the gate electrode 54 and the source / drain diffusion layers 15 and 16. Also, the parasitic resistance of the gate electrode 54 can be reduced by the thickness of the polysilicon film.

[Sixth Embodiment]
In the sixth embodiment, an example will be described in which a substrate protrusion is formed by epitaxial growth and further contact formation to the source / drain diffusion layer is facilitated.

  FIGS. 10A to 10D are cross-sectional views showing a method for manufacturing a semiconductor device according to the sixth embodiment. FIGS. 11A to 11C show a method for manufacturing the semiconductor device. FIG.

  First, as shown in FIG. 10A, an insulating film 62 is formed on a silicon semiconductor substrate 61, the insulating film 62 is patterned by lithography and dry etching, and an opening is formed at a site where a channel portion of the MISFET is formed. 63 is formed. The planar structure at this time is as shown in FIG.

  Subsequently, silicon is epitaxially grown using the silicon semiconductor substrate 61 in the opening 63 as a seed, and as shown in FIG. 10B, overgrowth is performed on the insulating film 62 to form an epitaxial layer 64.

  Further, the epitaxial layer 64 is patterned by lithography and dry etching to form a substrate protrusion 64A that becomes a source, a drain, and a channel, as shown in FIG. At this time, as shown in FIG. 11B, the planar shape of the substrate protrusion 64A as viewed from above is the upper and lower portions where the source diffusion layer and the drain diffusion layer are formed, as compared with the central portion where the channel is formed. It is getting bigger.

  Next, as shown in FIG. 10D, a gate insulating film 65 is formed on the upper surface and side surfaces of the substrate protrusion 64A. Further, a material to be a gate electrode is deposited on the gate insulating film 65, and patterning is performed by a lithography method and dry etching to form the gate electrode 66. After the formation of the gate electrode 66, phosphorus (P) or arsenic (As) is introduced into the substrate protrusion 64A except under the gate electrode 66 by self-aligned ion implantation using the gate electrode pattern as a mask, and source diffusion is performed. A layer 67 and a drain diffusion layer 68 are formed. The planar structure at this time is as shown in FIG. FIG. 12 is a perspective view of the semiconductor device manufactured by the above process.

  In the semiconductor device having the structure shown in FIG. 12 manufactured by the manufacturing process, it is possible to secure insulation against the substrate of the source / drain portion of the MISFET called delta or fin type. As a result, even if the distance between the elements is reduced, the possibility that the adjacent elements are erroneously turned on is small, and the element isolation resistance can be improved. Further, since the channel portion is formed by the epitaxial layer 64 grown from the substrate 61, the channel bias can be controlled from the substrate side. Further, similarly to the structure shown in FIGS. 5 and 6, the length in the direction perpendicular to the channel length of the substrate projection 64A where the source diffusion layer 67 and the drain diffusion layer 68 are formed is the central portion where the channel is formed. The channel length is longer than the length in the direction perpendicular to the channel length, so that the channel portion can be made thin to realize an operation equivalent to that of an SOI device, and the resistance of the source / drain portion can be reduced. Formation of a contact to the drain diffusion layer is facilitated.

  In the semiconductor device of this embodiment, since the channel portion is electrically connected to the substrate, a substrate bias can be applied, and threshold control and reduction of the substrate floating effect can be achieved. Further, since the source / drain diffusion layers are formed of single crystal silicon from the channel portion, the parasitic resistance can be reduced.

  In each of the above-described embodiments, the n-channel MIS field effect transistor has been described as an example. However, the present invention is not limited to this, and the p-channel MIS field can be changed by changing the conductivity type using an appropriate process condition. It is also possible to form effect transistors.

  As described above, according to the embodiment of the present invention, even when the gate length is miniaturized, the semiconductor device can be operated as a fully depleted element, and heat generation due to Joule heat and a substrate floating effect can be reduced. Can be provided.

1 is a perspective view showing a configuration of a semiconductor device according to a first embodiment of the present invention. It is a perspective view which shows the structure of the semiconductor device of 2nd Embodiment of this invention. It is a perspective view which shows the structure of the semiconductor device of the modification of the 2nd Embodiment of this invention. It is a perspective view which shows the structure of the semiconductor device of the other modification of the 2nd Embodiment of this invention. It is a perspective view which shows the structure of the semiconductor device of 3rd Embodiment of this invention. (A) is a top view of the semiconductor device of the said 3rd Embodiment, (b) is a side view of the said semiconductor device, (c) is sectional drawing along the 6C-6C line | wire in the said top view, d) is a sectional view taken along line 6D-6D in the plan view. It is a perspective view which shows partially the structure of the semiconductor device of 4th Embodiment of this invention. It is a perspective view which shows partially the structure of the semiconductor device of the modification of the 4th Embodiment of this invention. It is a perspective view which shows the structure of the semiconductor device of 5th Embodiment of this invention. (A)-(d) is sectional drawing which shows the manufacturing method of the semiconductor device of 6th Embodiment of this invention. (A)-(c) is a top view which shows the manufacturing method of the semiconductor device of the said 6th Embodiment. It is a perspective view which shows the structure of the semiconductor device of the said 6th Embodiment. (A)-(c) is the layout figure and sectional drawing which show the structure of MOSFET of the conventional 1st example. It is a perspective view of MOSFET using the conventional bulk substrate. It is sectional drawing of the said MOSFET. It is sectional drawing which shows the structure of the MISFET of the conventional 2nd example. It is sectional drawing which shows the structure of the MISFET of the conventional 3rd example.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... P-type silicon substrate, 11A ... Substrate protrusion part, 12 ... Insulating film, 13 ... Gate insulating film, 14 ... Gate electrode, 14A ... Gate electrode, 14B ... Gate electrode, 15 ... Source diffusion layer, 16 ... Drain diffusion layer 17 ... impurity region, 18 ... contact, 21 ... impurity region, 22 ... insulating film, 31A ... substrate projection, 41A ... substrate projection, 41B ... substrate projection, 42 ... p + layer, 43 ... n- layer, 44 ... p-layer, 51A ... substrate projection, 54 ... gate electrode, 61 ... silicon semiconductor substrate, 62 ... insulating film, 63 ... opening, 64 ... epitaxial layer, 64A ... substrate projection, 65 ... gate insulating film, 66 ... Gate electrode, 67 ... Source diffusion layer, 68 ... Drain diffusion layer.

Claims (4)

A protrusion formed on a first conductivity type semiconductor substrate and having a first conductivity type semiconductor layer;
A gate electrode formed on at least a side surface of the protrusion via a gate insulating film;
A source region and a drain region of a second conductivity type formed in the semiconductor layer of the protrusion so as to sandwich the gate electrode;
First and second element isolation insulating films formed on the semiconductor substrate so as to sandwich the protrusion,
A first impurity region of a first conductivity type formed in the semiconductor substrate under the first element isolation insulating film;
A second impurity region of a first conductivity type formed in the semiconductor substrate under the second element isolation insulating film,
The first impurity region and the second impurity region are formed by ion implantation of impurities, respectively, the impurity diffuses into the semiconductor substrate under the protrusion, and the first impurity region and the second impurity region are under the protrusion. Connected within the semiconductor substrate,
The first and second impurity regions are disposed directly below the source region and the drain region via the semiconductor layer,
The height and width direction perpendicular to the channel length of the protrusion formed on the side surface of the gate electrode are orthogonal to the channel length of the protrusion where the source region and drain region are formed. A semiconductor device characterized by being shorter than the height and the length in the width direction. A protrusion formed on a first conductivity type semiconductor substrate and having a first conductivity type semiconductor layer;
A gate electrode formed on at least a side surface of the protrusion via a gate insulating film;
A source region and a drain region of a second conductivity type formed in the semiconductor layer of the protrusion so as to sandwich the gate electrode;
First and second element isolation insulating films formed on the semiconductor substrate so as to sandwich the protrusion,
A first impurity region of a first conductivity type formed in the semiconductor substrate under the first element isolation insulating film;
A second impurity region of a first conductivity type formed in the semiconductor substrate under the second element isolation insulating film;
A contact plug embedded in at least one of the first and second element isolation insulating films and connected to at least one of the first and second impurity regions;
The first impurity region and the second impurity region are formed by ion implantation of impurities, respectively, the impurity diffuses into the semiconductor substrate under the protrusion, and the first impurity region and the second impurity region are under the protrusion. Connected within the semiconductor substrate,
The first and second impurity regions are disposed directly below the source region and the drain region via the semiconductor layer,
The height and width direction perpendicular to the channel length of the protrusion formed on the side surface of the gate electrode are orthogonal to the channel length of the protrusion where the source region and drain region are formed. A semiconductor device characterized by being shorter than the height and the length in the width direction. A protrusion formed on a first conductivity type semiconductor substrate and having a first conductivity type semiconductor layer;
A gate electrode formed on a top surface and a side surface of the protrusion via a gate insulating film;
A source region and a drain region of a second conductivity type formed in the semiconductor layer of the protrusion so as to sandwich the gate electrode;
First and second element isolation insulating films formed on the semiconductor substrate so as to sandwich the protrusion,
A first impurity region of a first conductivity type formed in the semiconductor substrate under the first element isolation insulating film;
A second impurity region of a first conductivity type formed in the semiconductor substrate under the second element isolation insulating film,
The upper surface of the gate electrode is planarized from above the protrusion over the first element isolation insulating film and the second element isolation insulating film,
The first impurity region and the second impurity region are formed by ion implantation of impurities, respectively, the impurity diffuses into the semiconductor substrate under the protrusion, and the first impurity region and the second impurity region are under the protrusion. Connected within the semiconductor substrate,
The first and second impurity regions are disposed directly below the source region and the drain region via the semiconductor layer,
The height and width direction perpendicular to the channel length of the protrusion formed on the side surface of the gate electrode are orthogonal to the channel length of the protrusion where the source region and drain region are formed. A semiconductor device characterized by being shorter than the height and the length in the width direction. The height of the protrusions in which the source region and the drain region are formed and the length in the width direction are the heights of the protrusions on which the gate electrode is formed on the side surfaces using an epitaxial technique. and a semiconductor device according to any one of claims 1 to 3, characterized in that it is formed so that each longer than the length in the width direction.

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