JP4287419B2 - Semiconductor device - Google Patents

Description

The present invention relates to a manufacturing technology of a semiconductor device, in particular, it is applied to the production technology of a semiconductor device having a MISFET of a vertical structure (M etal I nsulator S emiconductor F ield E ffect T ransistor) technique effective .

  As a power transistor (semiconductor device) having a MISFET having a vertical structure, a power transistor having a MISFET in which a low resistance region is formed on a side wall portion of a channel formation region is disclosed in, for example, Japanese Patent Laid-Open No. 1-291468 (Patent Document 1). It is described in. The low resistance region is formed of a semiconductor region made of an impurity introduced through the gate opening by forming a gate opening in the gate electrode of the MISFET. Hereinafter, a method of manufacturing a power transistor having a MISFET in which a low resistance region is formed on the side wall portion of the channel formation region will be described with reference to FIGS.

  First, a semiconductor substrate 1 is prepared in which an n − type epitaxial layer 1B is formed on the main surface of an n + type semiconductor substrate 1A. Next, the gate insulating film 2 is formed on the main surface of the n − type epitaxial layer 1B, which is the main surface of the semiconductor substrate 1, and then the main surface of the n − type epitaxial layer 1B is formed as shown in FIG. A conductive film 3 is formed on the surface with a gate insulating film 2 interposed.

  Next, the conductive film 3 is patterned to form a gate electrode 3A on the first region of the main surface of the n − type epitaxial layer 1B. This patterning process is performed by an etching technique using a photoresist mask as an etching mask. The photoresist mask is formed by a photolithography technique.

  Next, the gate electrode 3A is used as an impurity introduction mask, and as shown in FIG. 26, the p-type impurity 5 is selectively applied to the second region of the main surface of the n − type epitaxial layer 1B by ion implantation. Introduce.

  Next, a photoresist mask 50 having an opening exposing a part of the main surface of the gate electrode 3A and covering the second region of the main surface of the n − type epitaxial layer 1B is formed. Thereafter, using the photoresist mask 50 as an etching mask, the gate electrode 3A is etched to form a gate opening 3B in the gate electrode 3A.

  Next, as shown in FIG. 27, n-type impurities 4 are selectively introduced into the first region of the main surface of the n − -type epitaxial layer 1B through the gate opening 3B by ion implantation. Thereafter, the photoresist mask 50 is removed.

  Next, thermal diffusion treatment is performed, and as shown in FIG. 28, an n-type semiconductor region 4A, which is a low-resistance region, is formed with the n-type impurity 4 in the first region of the main surface of the n − -type epitaxial layer 1B. At the same time, a p-type semiconductor region 5A as a channel formation region is formed with the p-type impurity 5 in the second region of the main surface of the n − type epitaxial layer 1B.

  Next, a photoresist mask 51 is formed so as to cover the gate opening 3B and a part of the main surface of the p-type semiconductor region 5A. Thereafter, as shown in FIG. 29, the photoresist mask is formed. 51 and the gate electrode 3A are used as an impurity introduction mask, and the n-type impurity 6 is selectively introduced into the other region of the main surface of the p-type semiconductor region 5A by ion implantation.

  Next, the photoresist mask 51 is removed, and then a thermal diffusion process is performed. As shown in FIG. 30, the n-type impurity 6 is formed in a partial region of the main surface of the p-type semiconductor region 5A. An n + type semiconductor region 6A which is a source region is formed. In this step, the MISFET Q in which the n-type semiconductor region 4A that is the low resistance region is formed on the side portion of the p-type semiconductor region 5A that is the channel formation region is formed. The channel length of the MISFET Q is defined by the distance between the n-type semiconductor region 4A and the n + -type semiconductor region 6A.

  Next, an interlayer insulating film 7 is formed on the entire main surface of the n − type epitaxial layer 1B including the gate electrode 3A and the gate opening 3B, and then a connection hole 8 is formed in the interlayer insulating film 7. .

  Next, a p + type semiconductor region 9 which is a contact region is formed on the main surface of the p type semiconductor region 5A, and then a source wiring 10A is formed as shown in FIG. 31, whereby a power transistor having a MISFET Q is formed. Almost complete.

  The power transistor configured as described above can reduce the gate input capacitance (feedback capacitance) added to the gate electrode 3A of the MISFET Q by an amount corresponding to the occupied area of the gate opening 3B, so that the operation speed is increased. And lower power consumption. In addition, since the drain resistance can be reduced by the low resistance region (n-type semiconductor region 4A), the on-resistance can be reduced.

JP 11-291468 A

  However, as a result of studying the power transistor having the above-described MISFET Q, the present inventor has found the following problems.

  The gate opening 3B is formed after the gate electrode 3A is formed. That is, since each of the gate electrode 3A and the gate opening 3B is formed in a forming process independent of each forming process, the position of the gate opening 3B with respect to the gate electrode 3A is displaced, and further, the low resistance region is formed. A position shift occurs at the position of the n-type semiconductor region 4A. The misalignment of the n-type semiconductor region 4A, which is a low-resistance region, occurs as shown in FIG. 32 (essential cross-sectional view). The overlapping region 14 where the two overlap is generated. In this overlapping region 14, since the effective concentration of the p-type impurity 5 becomes low, the punch-through breakdown voltage of the MISFET Q deteriorates. Further, there is a possibility that the threshold voltage of the MISFET Q may fluctuate.

  Further, when the n-type semiconductor region 4A which is a low resistance region is not formed, the gate opening 3B is misaligned as shown in FIG. 33 (essential cross-sectional view). And the open area 15 where the gate electrode 3A does not overlap is generated. For this reason, the depletion region extending from the p-type semiconductor region 5A to the n − -type epitaxial layer 1B becomes smaller and the electric field strength increases, so that the channel formation region (p-type semiconductor region 5A) and drain region (n − The junction breakdown voltage at the pn junction with the epitaxial layer 1B) deteriorates.

  Further, even when a voltage is applied to the gate electrode 3A, the channel layer (inversion layer) is not formed in the void region 12, so that the threshold voltage of the MISFET Q varies.

  An object of the present invention is to provide a technique capable of preventing deterioration of punch-through breakdown voltage of a MISFET mounted on a power transistor (semiconductor device).

  Another object of the present invention is to provide a technique capable of preventing the deterioration of the junction breakdown voltage at the pn junction between the channel formation region and the drain region of the MISFET mounted on the power transistor (semiconductor device). There is.

  Another object of the present invention is to provide a technique capable of preventing fluctuations in the threshold voltage of a MISFET mounted on a power transistor (semiconductor device).

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
(1) In a method of manufacturing a power transistor (semiconductor device) having a MISFET, a step of forming a conductive film on a main surface of a first conductivity type semiconductor region which is a drain region with a gate insulating film interposed therebetween; Forming a gate electrode on the first region of the main surface of the first conductivity type semiconductor region, and forming a gate opening in the gate electrode; and the first conductivity type semiconductor region Forming a second conductivity type semiconductor region, which is a channel formation region, with a second conductivity type impurity introduced in a second region of the main surface in a self-aligned manner with respect to the gate electrode; and Forming a first conductivity type semiconductor region which is a source region with a first conductivity type impurity introduced in a self-aligned manner with respect to the gate electrode on a main surface of the type semiconductor region.
(2) In the method for manufacturing a power transistor according to the means (1), the first conductivity type introduced into the first region of the main surface of the first conductivity type semiconductor region which is the drain region through the gate opening. Forming a first conductivity type semiconductor region which is a low-resistance region with impurities;

According to the means (1) described above, since the gate electrode and the gate opening are formed in the same process, it is possible to prevent displacement of the gate opening with respect to the gate electrode. As a result, it is possible to suppress the generation of a void region where the second conductivity type semiconductor region, which is a channel formation region, and the gate electrode do not overlap with each other, so that the MISFET channel formation region (second conductivity type semiconductor region) It is possible to prevent the deterioration of the junction breakdown voltage at the pn junction with the drain region (first conductivity type semiconductor region).
In addition, since the channel layer is reliably formed, fluctuations in the threshold voltage of the MISFET can be prevented.

  According to the means (2) described above, it is possible to prevent the displacement of the gate opening with respect to the gate electrode, and therefore it is possible to prevent the displacement of the first conductivity type semiconductor region which is the low resistance region. As a result, it is possible to suppress the occurrence of an overlapping region where the first conductivity type semiconductor region that is the low resistance region and the second conductivity type semiconductor region that is the channel formation region can be suppressed. Can be prevented.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
It is possible to prevent the deterioration of the punch-through breakdown voltage of the MISFET mounted on the power transistor (semiconductor device).
It is possible to prevent the deterioration of the junction breakdown voltage at the pn junction between the channel formation region and the drain region of the MISFET mounted on the power transistor (semiconductor device).
Variations in the threshold voltage of the MISFET mounted on the power transistor can be prevented.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment of the invention, and the repetitive description thereof is omitted.

(Practical form 1)
1 is a chip layout diagram of a power transistor (semiconductor device) according to a first embodiment of the present invention, FIG. 2 is a plan view of a main part of FIG. 1, and FIG. 3 is a position along line AA shown in FIG. FIG. In FIG. 2, the source wiring 10 </ b> A, the final protective film 11, and the like, which will be described later, are not shown for easy viewing.

  As shown in FIG. 1, the power transistor (semiconductor device) of the present embodiment is configured in a semiconductor chip formation region 16 whose plane is formed in a square shape, for example. This power transistor basically has a single-layer wiring structure (single-layer aluminum wiring structure).

In the central region of the semiconductor chip forming region 16, the source wiring 10 </ b> A is configured in most of the region, and the gate wiring 10 </ b> B is configured in a part of the region. Source wiring 10A is electrically connected to the external terminals (bonding pads) 10A _1, the gate wiring 10B is electrically connected to the external terminals (bonding pads) 10B _1. Each of the source wiring 10A, the gate wiring 10B, the external terminal 10A ₁ and the external terminal 10B ₁ is formed of, for example, an aluminum film or an aluminum alloy film.

  In the central region of the semiconductor chip formation region 16, a plurality of MISFETs Q are mounted as shown in FIG. Each of the plurality of MISFETs Q is electrically connected in parallel and arranged in a triangular arrangement.

  As shown in FIG. 3, the power transistor includes an n − type epitaxial layer (low impurity concentration semiconductor region) on the main surface of an n + type semiconductor substrate (high impurity concentration semiconductor region) 1A made of, for example, single crystal silicon. It is mainly composed of a semiconductor substrate 1 on which 1B is formed. The aforementioned MISFET Q is formed on the main surface of the semiconductor substrate 1, and the drain electrode 12 is formed on the back surface thereof.

  The MISFET Q is mainly composed of a channel formation region, a gate insulating film 2, a gate electrode 3A, a source region, and a drain region. The channel formation region is formed of a p-type semiconductor region 5A formed on the main surface of n − type epitaxial layer 1B. Gate insulating film 2 is formed of a thermally oxidized insulating film formed on the main surface of n − type epitaxial layer 1B. Gate electrode 3 </ b> A is formed of a polycrystalline silicon film formed on the main surface of gate insulating film 2. The source region is composed of an n + type semiconductor region 6A formed on the main surface of the p type semiconductor region 5A. The drain region includes an n + type semiconductor substrate 1A, an n − type epitaxial layer 1B, and an n type semiconductor region (low resistance region) 4A. That is, the MISFET Q of the present embodiment is configured with an n-channel conductivity type having a vertical structure with the semiconductor substrate 1 as a drain region.

  As shown in FIGS. 2 and 3, a gate opening 3B exposing a part of the surface of the gate insulating film 2 is formed in the gate electrode 3A of the MISFETQ. The planar shape of the gate opening 3B is, for example, a triangular shape. Thus, by forming the gate opening 3B in the gate electrode 3A, the gate input capacitance (feedback capacitance) added to the gate electrode 3A can be reduced by an amount corresponding to the occupied area of the gate opening 3B. The operation speed of the power transistor can be increased and the power consumption can be reduced.

  The p-type semiconductor region 5A, which is the channel formation region of the MISFET Q, is composed of p-type impurities introduced in a self-aligned manner with respect to the gate electrode 3A. The p-type semiconductor region 5A has a planar shape, for example, a circular shape. The n + -type semiconductor region 6A, which is the source region of the MISFET Q, is composed of n-type impurities introduced in a self-aligned manner with respect to the gate electrode 3A. The n + type semiconductor region 6A is formed in a ring shape, for example.

  The n-type semiconductor region (low resistance region) 4A, which is the drain region of the MISFET Q, is formed in the first region of the main surface of the n − -type epitaxial layer 1B below the gate electrode 3A, and is a p-type semiconductor region that is a channel formation region It contacts the side wall of 5A. The n-type semiconductor region 4A is composed of n-type impurities introduced through the gate opening 3B, and has a higher impurity concentration than the n − -type epitaxial layer 1B which is a drain region. That is, the resistance of the drain region on the channel formation region side is reduced. As described above, the drain resistance of the MISFET Q can be reduced by forming the low resistance region (n-type semiconductor region 4A) on the side wall of the channel formation region (p-type semiconductor region 5A) of the MISFET Q. The on-resistance can be reduced.

  A p + type semiconductor region 9 which is a contact region is formed on the main surface of the p type semiconductor region 5A which is the channel forming region. The p + type semiconductor region 9 is set to a higher impurity concentration than the p type semiconductor region 5A.

A source wiring 10A is electrically connected to each of the p + type semiconductor region 9 and the n + type semiconductor region 6A through a connection hole 8 formed in the interlayer insulating film 7. A gate wiring (10B) is electrically connected to the gate electrode 3A. The interlayer insulating film 7 is disposed between the gate electrode 3A and the source wiring 10A, and insulates and separates the gate electrode 3A and the source wiring 10A. Interlayer insulating film 7 is formed, for example, PSG (P hospho S ilicate G lass ) film.

  A final protective film 11 is formed on the entire main surface of the n − type epitaxial layer 1B including the source wiring 10A and the gate wiring (10B). This final protective film 11 is formed of, for example, a polyimide resin film.

  Next, a manufacturing method of the power transistor having the MISFET Q will be described with reference to FIGS. 4 to 11 (cross-sectional views for explaining the manufacturing method).

  First, a semiconductor substrate 1 is prepared in which an n − type epitaxial layer (first conductivity type semiconductor region) 1B is formed on the main surface of an n + type semiconductor substrate 1A made of single crystal silicon.

  Next, a thermal oxidation process is performed to form a gate insulating film 2 made of a thermal silicon oxide film on the main surface of the n − type epitaxial layer 1B.

  Next, a conductive film 3 is formed on the main surface of the n − type epitaxial layer 1B with a gate insulating film 2 interposed. The conductive film 3 is formed of a polycrystalline silicon film deposited by, for example, a CVD method. Impurities that reduce the resistance value are introduced into the polycrystalline silicon film during or after the deposition.

  Next, as shown in FIG. 4, a mask 20 for forming a gate electrode and a gate opening is formed on the main surface of the conductive film 3. For example, the mask 20 is formed of a photoresist film formed by a photolithography technique.

Next, using the mask 20 as an etching mask, the conductive film 3 is patterned to form a gate electrode 3A in the first region of the main surface of the n − type epitaxial layer 1B as shown in FIG. At the same time, a gate opening 3B exposing a part of the surface of the gate insulating film 2 is formed in the gate electrode 3A. In this process, since the gate electrode 3A and the gate opening 3B are formed in the same process, the positional deviation of the gate opening 3B with respect to the gate electrode 3A can be prevented.
Next, the mask 20 is removed.

Next, the n-type impurity 4 is selectively introduced into the first region of the main surface of the n − -type epitaxial layer 1B through the gate opening 3B. As shown in FIG. 6, the n-type impurity 4 is introduced by an ion implantation method using the mask 21 covering the second region of the main surface of the n − -type epitaxial layer 1B and the gate electrode 3A as an impurity introduction mask. Is done. The n-type impurity 4 is introduced, for example, under conditions where the final introduction amount is set to about 10 ¹¹ to 10 ¹² [atoms / cm ² ]. For example, the mask 21 is formed of a photoresist film formed by a photolithography technique.

Next, the p-type impurity 5 is selectively introduced into the second region of the main surface of the n − -type epitaxial layer 1B in a self-aligned manner with respect to the gate electrode 3A. As shown in FIG. 7, the p-type impurity 5 is introduced by an ion implantation method using the mask 22 covering the gate opening 3B and the gate electrode 3A as an impurity introduction mask. The p-type impurity 5 is introduced, for example, under conditions where the final introduction amount is set to about 10 ¹³ to 10 ¹⁴ [atoms / cm ² ]. For example, the mask 22 is formed of a photoresist film formed by a photolithography technique.

  Next, thermal diffusion treatment is performed, and as shown in FIG. 8, an n-type semiconductor region 4A, which is a low-resistance region, is formed with the n-type impurity 4 in the first region of the main surface of the n − -type epitaxial layer 1B. At the same time, a p-type semiconductor region 5A as a channel formation region is formed with the p-type impurity 5 in the second region of the main surface of the n − type epitaxial layer 1B. In this step, since the displacement of the gate opening 3B with respect to the gate electrode 3A is prevented, the displacement of the n-type semiconductor region (low resistance region) 4A made of the n-type impurity 4 introduced through the gate opening 3B is prevented. be able to.

Next, n-type impurities 6 are selectively introduced into a partial region of the main surface of the p-type semiconductor region 5A in a self-aligned manner with respect to the gate electrode 3A. As shown in FIG. 9, the n-type impurity 6 introduces an impurity into the mask 23 and the gate electrode 3A, which covers the gate opening 3B and the other part of the main surface of the p-type semiconductor region 5A. It is introduced by the ion implantation method used as a mask. The n-type impurity 6 is introduced, for example, under conditions where the final introduction amount is set to about 10 ¹⁵ to 10 ¹⁶ [atoms / cm ² ]. For example, the mask 23 is formed of a photoresist film formed by a photolithography technique.

  Next, thermal diffusion treatment is performed to form an n + -type semiconductor region 6A as a source region with the n-type impurity 6 in a partial region of the main surface of the p-type semiconductor region 5A as shown in FIG. To do. By this step, the MISFET Q whose channel length is defined by the distance between the n-type semiconductor region (low resistance region) 4A and the n + -type semiconductor region (channel formation region) 6A is formed.

  Next, an interlayer insulating film 7 made of a PSG film is formed on the entire main surface of the n − type epitaxial layer 1B including the gate electrode 3A, and then the interlayer insulating film 7 is formed as shown in FIG. Then, a connection hole 8 is formed to expose a part of the main surface of the p-type semiconductor region 5A and a part of the main surface of the n + -type semiconductor region 6A.

  Next, a p-type impurity is selectively introduced into the main surface of the p-type semiconductor region 5A through the connection hole 8 by an ion implantation method, and a p + -type semiconductor region 9 as a contact region is formed on the main surface of the p-type semiconductor region 5A. Form.

  Next, a source wiring 10A electrically connected to each of the n + type semiconductor region 6A and the p + type semiconductor region 9 is formed, and a gate wiring (10B) electrically connected to the gate electrode 3A is formed. To do.

Next, a final protective film 11 made of a polyimide resin film is formed on the entire main surface of the n − type epitaxial layer 1B including the source wiring 10A and the gate wiring (10B). Thereafter, the drain electrode 12 is formed on the back surface of the semiconductor substrate 1, whereby the power transistor having the MISFET Q is almost completed.
In the manufacturing process described above, the step of the n-type semiconductor region 4A may be omitted.

Thus, according to the present embodiment, the following operational effects can be obtained.
(1) In a method of manufacturing a power transistor (semiconductor device) having a MISFET Q, a step of forming a conductive film 3 with a gate insulating film 2 interposed on a main surface of an n − type epitaxial layer 1 that is a drain region; Patterning the conductive film 3 to form a gate electrode 3A on the first region of the main surface of the n − type epitaxial layer 1B, and forming a gate opening 3B in the gate electrode; and the n − type Forming a p-type semiconductor region 5A, which is a channel formation region, with a p-type impurity 5 introduced in a self-aligned manner with respect to the gate electrode 3A in the second region of the main surface of the epitaxial layer 1B; and the p-type semiconductor Forming an n + -type semiconductor region 6A as a source region with an n-type impurity 6 introduced in a self-aligned manner with respect to the gate electrode 3A on the main surface of the region 5A.

Accordingly, since the gate electrode 3A and the gate opening 3B are formed in the same process, it is possible to prevent the positional deviation of the gate opening 3B with respect to the gate electrode 3A. As a result, when the n-type semiconductor region 4A that is a low-resistance region is not formed, the p-type semiconductor region 5A that is a channel formation region and the gate region (1
5) can be suppressed, so that the channel formation region of MISFETQ (
It is possible to prevent deterioration of the junction breakdown voltage at the pn junction between the p-type semiconductor region 5A) and the drain region (n− type epitaxial layer 1B).

  In addition, since the channel layer is reliably formed, fluctuations in the threshold voltage of the MISFET Q can be prevented.

  In addition, since the channel layer is formed reliably, the electrical characteristics of the plurality of MISFETs Q mounted on the power transistor can be made uniform.

(2) In the method for manufacturing a power transistor (semiconductor device) according to (1), the n-type introduced into the first region of the main surface of the n − -type epitaxial layer 1B as the drain region through the gate opening 3B. A step of forming an n-type semiconductor region 4A, which is a low-resistance region, with the impurity 4 is provided.

  Thereby, since the positional deviation of the gate opening 3B with respect to the gate electrode 3A can be prevented, the positional deviation of the n-type semiconductor region 4A which is a low resistance region can be prevented. As a result, it is possible to suppress the occurrence of the overlapping region 14 where the n-type semiconductor region 4A, which is the low resistance region, and the p-type semiconductor region 5A, which is the channel formation region, overlap, thereby preventing deterioration of the punch-through breakdown voltage of the MISFETQ. be able to.

  The planar shape of the gate opening 3B may be a polygonal shape close to a circle as shown in FIG.

  Further, the gate opening 3B is arranged at the center of the pattern opening 3C as shown in FIGS. This is because the p-type semiconductor region 5A, which is a channel formation region, is composed of the p-type impurity 5 introduced through the pattern opening 3C, and the n-type impurity region 4A, which is a low-resistance region, is introduced through the gate opening 3B. 4, it is essential that the gate opening 3 </ b> B and the pattern opening 3 </ b> C are geometrically equidistant. When the plane area of the gate opening 3B is increased, the gate capacitance and the on-resistance can be reduced, but the gate resistance increases. On the contrary, if the gate opening 3B is made small, the gate capacitance and the on-resistance cannot be made small. As shown in FIGS. 2 and 12, in the case of the MISFETQ having a triangular arrangement, the above-described condition can be satisfied if the planar shape of the gate opening 3B is a triangle or a polygon close to a circle.

(Practical form 2)
13 to 17 are cross-sectional views for explaining a method for manufacturing a power transistor (semiconductor device) according to the second embodiment of the present invention.

  First, a semiconductor substrate 1 is prepared in which an n − type epitaxial layer (first conductivity type semiconductor region) 1B is formed on the main surface of an n + type semiconductor substrate 1A made of single crystal silicon.

  Next, a thermal oxidation process is performed to form a gate insulating film 2 made of a thermal silicon oxide film on the main surface of the n − type epitaxial layer 1B.

  Next, as in the first embodiment, a conductive film (3) is formed on the main surface of the n − type epitaxial layer 1B with the gate insulating film 2 interposed.

  Next, the conductive film (3) is patterned to form a gate electrode 3A on the first region of the main surface of the n-type epitaxial layer 1B, and the gate insulating film 3A is formed on the gate electrode 3A. A gate opening 3B that exposes a partial region of the surface is formed. In this process, since the gate electrode 3A and the gate opening 3B are formed in the same process, the positional deviation of the gate opening 3B with respect to the gate electrode 3A can be prevented. This patterning step is performed by an etching technique using a mask made of a photoresist film as an etching mask, as in the first embodiment.

Next, the n-type impurity 4 is selectively introduced into the first region of the main surface of the n − type epitaxial layer 1B through the gate opening 3B, and the second region of the main surface of the n − type epitaxial layer 1B is introduced. The n-type impurity 4 is selectively introduced in a self-aligned manner with respect to the gate electrode 3A. As shown in FIG. 13, the n-type impurity 4 is introduced by an ion implantation method using the gate electrode 3A as an impurity introduction mask. The n-type impurity 4 is introduced, for example, under conditions where the final introduction amount is set to about 10 ¹¹ to 10 ¹² [atoms / cm ² ].

Next, in the second region of the main surface of the n − type epitaxial layer 1B, the p-type impurity is set to be higher in introduction amount than the introduction amount of the n-type impurity 4 by self-alignment with the gate electrode 3A. 5 is introduced selectively. As shown in FIG. 14, the p-type impurity 5 is introduced by an ion implantation method using the mask 30 covering the gate opening 3B and the gate electrode 3A as an impurity introduction mask. The p-type impurity 5 is introduced, for example, under conditions where the final introduction amount is set to about 10 ¹³ to 10 ¹⁴ [atoms / cm ² ]. For example, the mask 30 is formed of a photoresist film formed by a photolithography technique.

  Next, thermal diffusion treatment is performed, and as shown in FIG. 15, an n-type semiconductor region 4A, which is a low-resistance region, is formed by the n-type impurity 4 in the first region of the main surface of the n − -type epitaxial layer 1B. At the same time, a p-type semiconductor region 5A is formed with the p-type impurity 5 in the second region of the main surface of the n − -type epitaxial layer 1B. In this step, each of the n-type impurity 4 and the p-type impurity 5 is introduced into the second region of the main surface of the n − -type epitaxial layer 1B. Since it is about an order of magnitude higher than the amount introduced, p-type semiconductor region 5A is formed in the second region of the main surface of n − type epitaxial layer 1B. Further, since the displacement of the gate opening 3B with respect to the gate electrode 3A is prevented, the displacement of the n-type semiconductor region (low resistance region) 4A made of the n-type impurity 4 introduced through the gate opening 3B can be prevented. it can.

Next, n-type impurities 6 are selectively introduced into a partial region of the main surface of the p-type semiconductor region 5A in a self-aligned manner with respect to the gate electrode 3A. As shown in FIG. 16, the n-type impurity 6 introduces an impurity into the mask 31 and the gate electrode 3A covering the gate opening 3B and covering the other region of the main surface of the p-type semiconductor region 5A. It is introduced by the ion implantation method used as a mask. The n-type impurity 6 is introduced, for example, under conditions where the final introduction amount is set to about 10 ¹⁵ to 10 ¹⁶ [atoms / cm ² ]. For example, the mask 31 is formed of a photoresist film formed by a photolithography technique.

  Next, thermal diffusion treatment is performed to form an n + type semiconductor region 6A as a source region with the n type impurity 6 in a partial region of the main surface of the p type semiconductor region 5A as shown in FIG. To do. By this step, the MISFET Q whose channel length is defined by the distance between the n-type semiconductor region (low resistance region) 4A and the n + -type semiconductor region (channel formation region) 6A is formed.

Next, as in the first embodiment, the interlayer insulating film (7), the connection hole (8), the p + type semiconductor region (9) as a contact region, the source wiring (10A), the gate wiring (10B), and the final By forming the protective film (11) and the drain electrode (12), a power transistor having the MISFET Q is almost completed.
In the manufacturing process described above, the step of the n-type semiconductor region 4A may be omitted.

  As described above, according to the present embodiment, the same effects as those of the first embodiment can be obtained, and the n-type impurity 4 can be selectively applied to the first region of the main surface of the n − -type epitaxial layer 1B through the gate opening 3B. Since the mask at the time of introduction into the first layer can be eliminated, one step of the photolithography process (coating, baking process, exposure process, development process, etc.) can be eliminated as compared with the first embodiment.

(Practical form 3)
18 to 22 are cross-sectional views for explaining a method for manufacturing a power transistor (semiconductor device) according to the third embodiment of the present invention.

  First, a semiconductor substrate 1 is prepared in which an n − type epitaxial layer (first conductivity type semiconductor region) 1B is formed on the main surface of an n + type semiconductor substrate 1A made of single crystal silicon.

  Next, a thermal oxidation process is performed to form a gate insulating film 2 made of a thermal silicon oxide film on the main surface of the n − type epitaxial layer 1B.

  Next, as in the first embodiment, a conductive film (3) is formed on the main surface of the n − type epitaxial layer 1B with the gate insulating film 2 interposed.

  Next, the conductive film (3) is patterned to form a gate electrode 3A on the first region of the main surface of the n-type epitaxial layer 1B, and the gate insulating film 3A is formed on the gate electrode 3A. An opening 3B that exposes a partial region of the surface is formed. In this process, since the gate electrode 3A and the gate opening 3B are formed in the same process, the positional deviation of the gate opening 3B with respect to the gate electrode 3A can be prevented. This patterning step is performed by an etching technique using a mask made of a photoresist film as an etching mask, as in the first embodiment.

Next, the p-type impurity 5 is selectively introduced into the second region of the main surface of the n − -type epitaxial layer 1B in a self-aligned manner with respect to the gate electrode 3A. As shown in FIG. 18, the p-type impurity 5 is introduced by an ion implantation method using the mask 40 covering the gate opening 3B and the gate electrode 3A as an impurity introduction mask. The p-type impurity 5 is introduced, for example, under conditions where the final introduction amount is set to about 10 ¹³ to 10 ¹⁴ [atoms / cm ² ]. The mask 40 is formed of, for example, a photoresist film formed by a photolithography technique.

  Next, thermal diffusion treatment is performed, and as shown in FIG. 19, a p-type semiconductor region 5A, which is a channel formation region, is formed in the second region of the main surface of the n − -type epitaxial layer 1B with the p-type impurity 5. Form.

Next, n-type impurities 6 are selectively introduced into a partial region of the main surface of the p-type semiconductor region 5A in a self-aligned manner with respect to the gate electrode 3A. As shown in FIG. 20, the n-type impurity 6 introduces an impurity into the mask 41 and the gate electrode 3A covering the gate opening 3B and covering the other part of the main surface of the p-type semiconductor region 5A. It is introduced by the ion implantation method used as a mask. The n-type impurity 6 is introduced, for example, under conditions where the final introduction amount is set to about 10 ¹⁵ to 10 ¹⁶ [atoms / cm ² ]. For example, the mask 41 is formed of a photoresist film formed by a photolithography technique.

  Next, thermal diffusion treatment is performed to form an n + -type semiconductor region 6A as a source region with the n-type impurity 6 in a partial region of the main surface of the p-type semiconductor region 5A.

  Next, thermal oxidation treatment is performed to form a speed-up oxide insulating film 13 on the main surface of the n + -type semiconductor region 6A. In this step, a speed-up oxide insulating film is also formed on the other region of the main surface of the p-type semiconductor region 5A and the first region of the main surface of the n − -type epitaxial layer 1B. Since the growth rate of the film varies depending on the impurity concentration, the film thickness of the accelerated oxide insulating film 13 formed on the main surface of the n + -type semiconductor region 6A having a high impurity concentration is the main thickness of the p-type semiconductor region 5A having a low impurity concentration. This is thicker than the film thickness of the accelerated oxide insulating film formed on the other region of the surface and on the first region of the main surface of the n − type epitaxial layer 1B. The accelerated oxide insulating film 13 is also formed on the surface of the gate electrode 3A that is not covered with the mask 41 of the previous step.

Next, the n-type impurity 4 is selectively introduced through the gate opening 3B onto the first region of the main surface of the n − -type epitaxial layer 1B. As shown in FIG. 21, the n-type impurity 4 is introduced by an ion implantation method using the enhanced oxide insulating film 13 and the gate electrode 3A as an impurity introduction mask. The n-type impurity 4 is introduced, for example, under conditions where the final introduction amount is set to about 10 ¹¹ to 10 ¹² [atoms / cm ² ]. In this step, the n-type impurity 4 is also introduced into the other region of the main surface of the p-type semiconductor region 5A.

Next, each of the interlayer insulating film 7 and the connection hole 8 is formed as in the first embodiment.
Next, a p-type impurity is selectively introduced into the main surface of the p-type semiconductor region 5A through the connection hole 8 by an ion implantation method. This p-type impurity is introduced, for example, under conditions where the final introduction amount is set to about 10 ¹⁵ to 10 ¹⁶ [atoms / cm ² ].

  Next, thermal diffusion treatment is performed, and as shown in FIG. 22, an n-type semiconductor region 4A, which is a low-resistance region, is formed by the n-type impurity 4 in the first region of the main surface of the n − -type epitaxial layer 1B. At the same time, a p + type semiconductor region 9 as a contact region is formed with the p type impurity on the main surface of the p type semiconductor region 5A. In this step, each of the n-type impurity 4 and the p-type impurity is introduced into the main surface of the p-type semiconductor region 5A, but the introduced amount of the p-type impurity is four digits larger than the introduced amount of the n-type impurity 4. Since the height is high, the p + type semiconductor region 9 is formed on the main surface of the p type semiconductor region 5A. Further, in this step, since the displacement of the gate opening 3B with respect to the gate electrode 3A is prevented, the displacement of the n-type semiconductor region (low resistance region) 4A made of the n-type impurity 4 introduced through the gate opening 3B is prevented. Can be prevented. By this step, the MISFET Q whose channel length is defined by the distance between the n-type semiconductor region (low resistance region) 4A and the n + -type semiconductor region (channel formation region) 6A is formed.

Next, as in the first embodiment, the source wiring (10A), the gate wiring (10B), the final protective film (11), and the drain electrode (12) are formed, whereby the power transistor having the MISFET Q is formed. Almost complete.
In the manufacturing process described above, the step of the n-type semiconductor region 4A may be omitted.

  As described above, according to the present embodiment, the same effects as those of the first embodiment can be obtained, and the n-type impurity 4 can be selectively applied to the first region of the main surface of the n − -type epitaxial layer 1B through the gate opening 3B. Since the photoresist mask at the time of introduction into can be eliminated, one step of the photolithography process (coating, baking, exposure, development, etc.) can be eliminated as compared with the first embodiment.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Of course.

  For example, the present invention can be applied to a power transistor having a MISFET in which a gate opening 3B is formed in a stripe-shaped gate electrode 3A, as shown in FIGS. 23 and 24 (plan views of main portions of the gate electrode).

Further, the present invention, equivalent circuit can be applied to the power transistor (semiconductor device) having a pnp bipolar transistor, an IGBT constituted by respective MISFET (I nsulated G ate B ipolar T ransistor).

1 is a chip layout diagram of a power transistor according to a first embodiment of the present invention. It is a principal part top view of the said power transistor. It is sectional drawing cut in the position of AA shown in FIG. It is principal part sectional drawing for demonstrating the manufacturing method of the said power transistor. It is principal part sectional drawing for demonstrating the manufacturing method of the said power transistor. It is principal part sectional drawing for demonstrating the manufacturing method of the said power transistor. It is principal part sectional drawing for demonstrating the manufacturing method of the said power transistor. It is principal part sectional drawing for demonstrating the manufacturing method of the said power transistor. It is principal part sectional drawing for demonstrating the manufacturing method of the said power transistor. It is principal part sectional drawing for demonstrating the manufacturing method of the said power transistor. It is principal part sectional drawing for demonstrating the manufacturing method of the said power transistor. It is a principal part top view which shows the modification of the gate electrode of MISFET mounted in the said power transistor. It is principal part sectional drawing for demonstrating the manufacturing method of the power transistor which is Embodiment 2 of this invention. It is principal part sectional drawing for demonstrating the manufacturing method of the said power transistor. It is principal part sectional drawing for demonstrating the manufacturing method of the said power transistor. It is principal part sectional drawing for demonstrating the manufacturing method of the said power transistor. It is principal part sectional drawing for demonstrating the manufacturing method of the said power transistor. It is principal part sectional drawing for demonstrating the manufacturing method of the power transistor which is Embodiment 3 of this invention. It is principal part sectional drawing for demonstrating the manufacturing method of the said power transistor. It is principal part sectional drawing for demonstrating the manufacturing method of the said power transistor. It is principal part sectional drawing for demonstrating the manufacturing method of the said power transistor. It is principal part sectional drawing for demonstrating the manufacturing method of the said power transistor. It is a principal part top view which shows the modification of the gate electrode of MISFET mounted in a power transistor. It is a principal part top view which shows the modification of the gate electrode of MISFET mounted in a power transistor. It is principal part sectional drawing for demonstrating the manufacturing method of the conventional power transistor. It is principal part sectional drawing for demonstrating the manufacturing method of the conventional power transistor. It is principal part sectional drawing for demonstrating the manufacturing method of the conventional power transistor. It is principal part sectional drawing for demonstrating the manufacturing method of the conventional power transistor. It is principal part sectional drawing for demonstrating the manufacturing method of the conventional power transistor. It is principal part sectional drawing for demonstrating the manufacturing method of the conventional power transistor. It is principal part sectional drawing for demonstrating the manufacturing method of the conventional power transistor. It is principal part sectional drawing for demonstrating the problem of the conventional power transistor. It is principal part sectional drawing for demonstrating the problem of the conventional power transistor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 1A ... n + type semiconductor substrate, 1B ... n-type epitaxial layer, 2 ... Gate insulating film, 3 ... Conductive film, 3A ... Gate electrode, 3B ... Gate opening, 3C ... Pattern opening, 4 ... N type Impurities, 4A... N-type semiconductor region (low resistance region), 5... P-type impurity, 5A... P-type semiconductor region (channel formation region), 6. ... Interlayer insulating film, 8 ... connection hole, 9 ... p + type semiconductor region, 10A ... source wiring, 10B ... gate wiring, 11 ... final protective film, 12 ... drain electrode, 13 ... accelerated oxide insulating film, 14 ... overlapping region , 15 ... open space area, 16 ... semiconductor chip formation area.

Claims (1)

A semiconductor device having a MISFET,
A semiconductor substrate;
A drain electrode formed on the back surface of the semiconductor substrate;
A plurality of channel regions formed on the surface of the semiconductor substrate;
A plurality of first semiconductor regions formed on the surface of the semiconductor substrate and having a conductivity type opposite to that of the channel region;
A plurality of source regions formed in the channel region;
A gate insulating film formed on the channel region and the first semiconductor region;
A gate electrode formed on the gate insulating film;
An opening of the gate electrode formed immediately above the first semiconductor region;
A source electrode formed on the gate electrode and electrically connected to the source region;
The plurality of channel regions and the plurality of first semiconductor regions are alternately arranged, and the adjacent channel regions and the first semiconductor regions are in contact with each other.

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