JP2876716B2 - Semiconductor device - Google Patents

Description

The present invention relates to an improvement in the structure of a semiconductor device.

[Conventional technology]

Conventionally, as shown in FIG. 2 (a), a semiconductor device, especially a read-only memory, is composed of one transistor per cell, and ROM data is written by changing the threshold voltage of this transistor by ion implantation. . FIG. 2 (b) is a sectional view of this,
201 is a semiconductor substrate, 202 is a gate film, 203 is a gate electrode, 2
04 is a high-concentration diffusion layer, 205 is a low-concentration diffusion layer of an LDD structure, 206 is an LDD-structured side wall insulating film 207 is an interlayer insulating film, and 208 is an AL wiring. Here, ROM data writing is performed by forming the impurity layer 209 by ion implantation before or after the formation of the interlayer insulating film 207 and changing the threshold voltage. FIG. 2C is a plan view, wherein a is a unit portion of one cell, and 210 is an element isolation region.

[Problems to be solved by the invention]

As miniaturization and integration increase, one cell shares one transistor and one contact part (second contact).
(In FIG. 2B, the gate electrode 3, the AL 208, and the diffusion layer 204 correspond.)
Is necessary and cannot be reduced much,
In addition, the problem that the speed cannot be increased because the on-resistance of the transistor itself cannot be reduced has become apparent.

An object of the present invention is to solve the problem and to provide a structure capable of realizing reduction in size and speed.

[Means for solving the problem]

A semiconductor device according to the present invention includes a first insulating film provided on a semiconductor substrate, a first conductor layer containing a first conductivity type impurity provided on the first insulating film, and provided on the first conductor layer. A second insulating film having a plurality of first openings, a first region of a second conductivity type provided on the second insulating film and in contact with the first conductor layer through the first opening, and a second insulating film; A second region of the first conductivity type other than the first region; a second conductor layer made of polycrystalline silicon; and a second conductor layer provided on the second conductor layer, and a predetermined one of the plurality of first openings. The first
A third insulating film having a second opening above the opening, a third conductor layer containing Al as a main component and disposed on the third insulating film,
It is characterized by having.

〔Example〕

1 (a), 1 (b) and 1 (c) are a plan view and a sectional view showing a circuit system and a structure of a semiconductor device according to an embodiment of the present invention.

1 (b) and 1 (c), 101 is a semiconductor substrate, 1
02 is an element isolation insulating film, 103 is a conductor layer formed of the same material as the gate electrode and containing impurities of the first conductivity type, for example, N
Polycrystalline silicon containing type impurities or so-called polycide on which refractory metal silicide is formed,
4 is a first interlayer insulating film, 105 is a first opening, 106 is a polycrystalline silicon layer containing a first conductivity type, that is, an N-type impurity, 107
Is a polycrystalline silicon layer containing a P-type impurity of the second conductivity type, 108 is a second interlayer insulating film, and 109 is a polycrystalline silicon layer formed on the first opening 105 and containing a P-type impurity. An opening 2 and 110 are wiring layers such as AL. A in FIG. 1B is a cell unit.

As can be seen from FIGS. 1 (b) and 1 (c), one cell unit is based on one contact opening 109, and whether a contact is to be opened or not is formed by data on a mask during a processing step. In other words, this method is a method in which data is determined by electrically sensing whether or not the wiring 110 and the conductive layer 103 are conductive, thereby forming a read-only memory. At this time, if the conductor layer 103 and the wiring layer 110 are simply connected through the opening 109, short-circuiting occurs between cells in a cell portion formed in a matrix. In order to avoid this, a polycrystalline silicon layer is provided below the opening, and an N-type impurity layer 106 and a P-type impurity layer 107 are formed here to form a PN junction. FIG. 1A shows this structure in a circuit diagram. At this time, the processability was improved by forming an insulating film 104 between the conductor layer 103 and the polycrystalline silicon layers 106 to 107. That is, the conductor layer 103 and the polycrystalline silicon layer 1
When 06 to 107 are in contact with the entire surface, both must be etched continuously, and when it is desired to directly connect the wiring layer 110 such as AL and the conductor layer 103, the etching must be performed via the polycrystalline silicon layer 106. However, there was a problem in contact resistance and the like. On the other hand, through the insulating film 104, this can stop the etching, the polysilicon layers 106, 107 and the conductor layer 103 can be etched separately, and the conductor layer 1
03 wiring layer 110 could be directly contacted.

According to this method, a memory cell as shown in FIG. 1B can be realized, and a reduction in size can be realized. Further, since the transistor functions via the electrical conduction between the conductor layer 103 and the wiring layer 110 although there is a PN junction without the intervention of a transistor, the resistance is lower than the ON resistance of the transistor, and high-speed operation is achieved. Further, since data is written with the presence or absence of the contact, that is, the opening 107, the time from data writing to completion of the product, that is, the production delivery time can be shortened.

〔The invention's effect〕

As described above, according to the present invention, a memory cell of a read-only memory, which has conventionally constituted a memory cell by a transistor, is constituted by a diode formed on polycrystalline silicon and a contact formed on the diode, and a memory cell is formed. Integration, high speed, and short delivery time were also measured.

[Brief description of the drawings]

1A to 1C are explanatory views of the present invention.
1 is a circuit diagram, FIG. 1 (b) is a plan view, and FIG. 1 (c) is a sectional view. 2 (a) to 2 (c) are explanatory views of a conventional structure, wherein FIG. 2 (a) is a circuit diagram, FIG. 2 (b) is a plan view, and FIG. 2 (c).
Is a sectional view. In the figure, 101, 201... Semiconductor substrates 102, 210... Element isolation insulating films 103, 203... Gate electrodes containing N-type impurities and their wiring layers 104. ... Polycrystalline silicon layer containing N-type impurity 107 Polycrystalline silicon layer containing P-type impurity 108 Second interlayer insulating film 109 Second opening 110, 208... Wiring layer 202 such as AL … Gate insulating film 204… High-concentration impurity layer 205… Low-concentration impurity layer 206… Sidewall 207… Interlayer insulating film 209… Impurity layer for data writing 211… Contact

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 27/112 H01L 21/8246

Claims (1)

(57) [Claims] A first insulating film provided on the semiconductor substrate, a first conductive layer containing a first conductivity type impurity provided on the first insulating film, provided on the first conductive layer; A second insulating film having a plurality of first openings, a first region of a second conductivity type disposed on the second insulating film and in contact with the first conductive layer through the first opening, and the first region; And a second region of a first conductivity type other than
A second conductive layer made of polycrystalline silicon, a third insulating layer disposed on the second conductive layer and having a second opening above a predetermined first opening of the plurality of first openings; A semiconductor device comprising: a film; and a third conductor layer containing Al as a main component, which is provided on the third insulating film.