JP2924127B2 - Semiconductor device - Google Patents

Description

The present invention relates to an improvement in the structure of a semiconductor device.

[Conventional technology]

Conventionally, as shown in FIG. 2 (a), a semiconductor device, especially a read-only memory, is composed of one transistor per cell, and ROM data is written by changing the threshold voltage of this transistor by ion implantation. . FIG. 2 (b) is a cross-sectional view of FIG.
01 is a semiconductor substrate, 202 is a gate film, 203 is a gate electrode, 20
4 is a high concentration diffusion layer, 205 is a low concentration diffusion layer of the LDD structure, 206 is a sidewall insulation film of the LDD structure, 207 is an interlayer insulation film, and 208 is an AL wiring. Here, ROM data writing is performed by forming the impurity layer 209 by ion implantation before or after the formation of the interlayer insulating film 207 and changing the threshold voltage. FIG. 2 (c) is a plan view and FIG.
Is a unit portion of one cell, and 210 is an element isolation region.

[Problems to be solved by the invention]

As miniaturization and integration increase, one cell shares one transistor and one contact part (second contact).
(In FIG. 2B, the gate electrode 3, the AL 208, and the diffusion layer 204 correspond.)
Is necessary and cannot be reduced much,
Further, the problem that the speed cannot be increased because the ohmic resistance of the transistor itself cannot be reduced has become apparent.

An object of the present invention is to solve the problem and to provide a structure capable of realizing reduction in size and speed.

[Means for solving the problem]

A semiconductor device according to the present invention includes a first insulating film provided on a semiconductor substrate, a first polycrystalline film provided on the first insulating film in a first direction and containing a first conductivity type impurity. A first opening disposed on the silicon layer or the first polycide layer, the first polycrystalline silicon layer or the first polycide layer, and exposing the first polycrystalline silicon layer or the first polycide layer; A second insulating film having a portion, the second insulating film being provided on the second insulating film in the first direction;
A first region containing an impurity of the first conductivity type directly connected to the first polycrystalline silicon layer or the first polycide layer at the opening of the first polycrystalline silicon layer or the first polycide layer; A second polysilicon layer comprising a second region which is not directly connected to the layer and contains a second conductivity type impurity of a conductivity type opposite to the first conductivity type, and the second polysilicon layer A semiconductor device, comprising: a third insulating film provided thereon; and a third conductor layer having A1 as a main component and extending in a second direction orthogonal to the first direction. Wherein the second region is provided at a position where the second polycrystalline silicon layer and the third conductor layer cross each other, and the third insulating film is At least one of the positions where the polycrystalline silicon layer and the third conductor A second opening that directly connects the conductor layer and the second region of the second polycrystalline silicon layer, wherein the first region and the second region are in the first direction; Wherein the first opening and the second opening are provided such that the second opening is not positioned on the first opening. .

〔Example〕

1 (a), 1 (b) and 1 (c) are a plan view and a sectional view showing a circuit system and a structure of a semiconductor device according to an embodiment of the present invention.

1 (b) and 1 (c), 101 is a semiconductor substrate, 1
02 is an element isolation insulating film, 103 is a conductor layer formed of the same material as the gate electrode and containing impurities of the first conductivity type, for example, N
Polycrystalline silicon containing type impurities or so-called polycide on which refractory metal silicide is formed,
4 is a first interlayer insulating film, 105 is a first opening, 106 is a polycrystalline silicon layer containing a first conductivity type, that is, an N-type impurity, 107
Is a second conductivity type, that is, a polycrystalline silicon layer containing a P-type impurity, 108 is a second interlayer insulating film, and 109 is a polycrystalline silicon layer formed on the first opening 105 and containing a P-type impurity. An opening 2 and 110 are wiring layers such as AL. A in FIG. 1B is a cell unit.

As can be seen from FIGS. 1 (b) and 1 (c), one cell unit is based on one contact opening 109, and whether a contact is to be opened or not is formed by data on a mask during a processing step. In other words, this method is a method in which data is determined by electrically sensing whether or not the wiring 110 and the conductive layer 103 are conductive, thereby forming a read-only memory.

At this time, if the conductor layer 103 and the wiring layer 110 are simply connected through the opening 109, short-circuiting occurs between cells in a cell portion formed in a matrix. To avoid this, a polycrystalline silicon layer is provided below the opening, and an N-type impurity layer 106 and a P-type
An N junction was formed and avoided by this rectifying action. FIG. 1A shows this structure in a circuit diagram. At this time, the processability was improved by forming an insulating film 104 between the conductor layer 103 and the polycrystalline silicon layers 106 to 107. That is, the conductor layer 103 and the polycrystalline silicon layer 106 or
When 107 is in contact with the entire surface, both must be etched continuously, and when it is desired to directly connect the wiring layer 110 such as AL and the conductor layer 103, the etching must be performed via the polycrystalline silicon layer 106. However, there was a problem in contact resistance and the like. On the other hand, insulating film 104
Through this, the etching can be stopped, the polysilicon layers 106 and 107 and the conductor layer 103 can be etched separately, and the conductor layer 103 and the wiring layer 1 can be etched separately.
10 could be contacted directly.

In addition, the first opening 105 is not provided on the second opening,
Since the N-type impurities in the conductor layer 103 are diffused into the upper polycrystalline silicon layer 106 by a heat treatment in a later step, the N-type impurities do not directly hit the P-type impurity region 107 by being provided in separate portions. Is obtained.

By this method, a memory cell as shown in FIG. 1 (b) can be realized and downsizing can be realized. Further, since the transistor functions via the electrical conduction between the conductor layer 103 and the wiring layer 110 although there is a PN junction without the intervention of a transistor, the resistance is lower than the ON resistance of the transistor, and high-speed operation is achieved. In addition, the time from writing of data for writing data to the presence or absence of the contact 107, that is, the opening 107 to completion of the writing, that is, the production delivery time could be shortened.

〔The invention's effect〕

According to the semiconductor device of the present invention, a PN junction diode for preventing a short circuit between cells is provided in the first polycrystalline silicon layer.
And a memory cell for writing information depending on the presence or absence of a second opening provided on the second region, the memory device including a second polycrystalline silicon layer and a word. The connection with the first polycrystalline silicon layer or the first polycide layer which is to be a line is made through the first opening which is not located immediately below the second opening in the direction perpendicular to the substrate. The first conductivity type impurity in the crystalline silicon layer or the first polycide layer can be prevented from diffusing into the second region containing the second conductivity type impurity, and the PN junction characteristics in the second polycrystalline silicon can be reduced. Can be stabilized.

[Brief description of the drawings]

1A to 1C are explanatory views of the present invention.
1 is a circuit diagram, FIG. 1 (b) is a plan view, and FIG. 1 (c) is a sectional view. 2 (a) to 2 (c) are explanatory views of a conventional structure, wherein FIG. 2 (a) is a circuit diagram, FIG. 2 (b) is a plan view, and FIG. 2 (c).
Is a sectional view. In the figure, 101, 201 ... semiconductor substrates 102, 210 ... element isolation insulating films 103, 203 ... gate electrodes containing N-type impurities and their wiring layers 104 ... first interlayer insulating film 105 ... First opening 106 Polycrystalline silicon layer containing N-type impurity 107 Polycrystalline silicon layer containing P-type impurity 108 Second interlayer insulating film 109 Second opening 110, 208 ... Wiring layer of AL etc. 202... Gate insulating film 204... Highly doped impurity layer 205... Lowly doped impurity layer 206... Sidewall 207... Interlayer insulating film 209. ……contact

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 27/10 431 H01L 29/872

Claims (1)

(57) [Claims] A first insulating film provided on a semiconductor substrate; a first polycrystalline silicon layer provided on the first insulating film in a first direction and containing a first conductivity type impurity; Alternatively, a first opening is provided on the first polycide layer, the first polycrystalline silicon layer or the first polycide layer, and exposes the first polycrystalline silicon layer or the first polycide layer. A second insulating film, which is provided on the second insulating film in the first direction, and is directly connected to the first polycrystalline silicon layer or the first polycide layer at the first opening. The first region containing the impurity of the first conductivity type is not directly connected to the first polycrystalline silicon layer or the first polycide layer, and the first region is not connected to the first region.
A second impurity containing an impurity of a second conductivity type opposite to the conductivity type;
A second polycrystalline silicon layer comprising a region of: a third insulating film provided on the second polycrystalline silicon layer; and a second direction extending in a second direction orthogonal to the first direction. And a third conductor layer having A1 as a main component, wherein the second region is formed by the second polycrystalline silicon layer and the third conductor layer. The third insulating film is provided corresponding to a position where the third conductive layer intersects with the third conductive layer at at least one of positions where the second polycrystalline silicon layer and the third conductive layer cross each other. A second opening that directly connects the second region of the second polycrystalline silicon layer to the second region, wherein the first opening and the second opening are located on the first opening; Wherein the second opening is not located.