JPS58169960A - Integrated circuit containing capacity element - Google Patents

Abstract

PURPOSE:To obtain an IC memory of high density by a method wherein gated electrodes are formed on a gate insulation film by aligning the end parts with the N-layers of a P type substrate, then the electrode of a capacity element is superposed via the insulation film, and accordingly an Al wiring is provided by covering it with an insulation film. CONSTITUTION:The gate electrodes 3 and 4 are formed on the gate oxide film 2 of the P type Si substrate 1, and covered with Si3N4 films 7 and 8, and an active region is isolated by a thick field oxide film 9 and a P<+> channel stopper. The electrode 11 of the capacity element of P doped poly Si is superposed on the Si3N4 films 7 and 8, and covered with an SiO2 film 12. Successively etched by the mask 12, P ions are implanted into the substrate surface selectively exposed, with the electrodes 3 and 4 as the mask resulting in the formation of N- layers 13 and 14, and the Al electrode 15 is connected to the exposed surfaces of the electrodes 3 and 4. by this constitution, a memory cell of the minimum occupation area which is constituted of the gate electrodes, capacity element electrode, and N-layers can be obtained on the active region.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit including a μ-capacitance element, and relates to a MUSg product circuit suitable as an IC memory with a capacity of 1%.

MO8 integrated circuits are suitable for high density and large scale.

5J large capacity 1C memory! can be expressed. Special 1
'Cj) Transistor-type IC memory vJ Storage using each transistor and capacitive element r1: The device occupancy is small because the storage area is also exposed. (2) It is attracting attention as a high-density integrated memory integrated circuit. . Conventionally, a μ-capacitor element and a transistor are formed separately in an active region, and the gate electrode of the transistor is formed by two inverse 1-type regions and one pole of the capacitor element.
! The layer is spread out flatly and provided on the active area,
These 4i for rainbow density! It is desirable that the thickness be small and thin. Well, the gate of the transistor [iQM4
By making it smaller, it is necessary to strike exactly g @ at the side of the total microscopic r1n of the connection between the gate electrode and the wiring electrode! It has become a technology.

It is an object of the present invention to provide a high-density M (J8 integrated path t').

This inventive integrated circuit! The value is - A gate electrode is provided on a conductive type semiconductor substrate via a gate insulating film, and the substrate IF
3, an opposite conductivity type region is provided in such a way that each end is aligned with this gate electrode, and a capacitive main electrode is placed on the gate electrode through a 9μ insulating film, and this capacitive element ≠ electrode is formed. Furthermore, there is an integrated circuit in which an insulating film is soldered and a wiring layer made of aluminum or the like is provided thereon.

Such a semiconductor device, for example, uses the selective oxidizing properties of a silicon nitride film on the surface of a type II semiconductor to protect the active region with a silicon nitride film and grow a thick oxide film on the surrounding semiconductor surface. In the Dan circuit, after providing the active region with a gate electrode that crosses the region in advance, 11
Selectively coat a silicon nitride film and perform selective oxidation,
It can be manufactured by a manufacturing method in which a single-sided VC resistor electrode is formed using a silicon nitride film using the selectively oxidized rC, and an opposite conductivity type region is formed at the other end of the active region.

According to this invention, an integrated circuit with a sufficiently small planar shape can be realized without using special microfabrication techniques.

Next, to better understand the characteristics of this invention.

An embodiment of this invention will be explained using -.

Figures 1 to 4 show this invention! It is a sectional view in the main manufacturing process of the example.

In the MO8 integrated circuit of this example, a gate insulating film 2 of silicon oxide with a thickness of 300 mm was grown by thermal oxidation on one surface of a P-type silicon crystal base l having a specific resistance of 1 ω, and then d
IJ (selective formation of gate electrodes 3.4 of phosphorous-doped polycrystalline silicon (FIG. 1)).

Gate electrodes 3, 4 Silicon oxide film of about 100λ 5.
61, a silicon nitride film 7. forms an active region.
8, and the substrate is thermally oxidized to form a 1al layer around the active region.
[1, A thick 7 silicon oxide film 9 of about Qgn is formed.

In addition, the silicon nitride film 7, 8t" selective oxidation mask is attached to the silicon oxide film 9, and the silicon nitride film 7.8 is used as a mask to prevent parasitic effects on the surface of the inactive region. impurities are introduced, resulting in a high concentration of Pmm
A boundary area O is formed (Figure 2).

Next, the active region is partitioned and 'fc7 recongenization is performed.7.
Top surface of 8 VC phosphorus-doped polycrystalline silicon volumetric element electrode 1
1, and thermally oxidize a silicon oxide film 12 with a thickness of about 5 L) OOA on the electrode.
12 is also used as an etching mask for the silicon nitride film 7.8. That is, the valley electrode 11 and the silicon nitride film 7.8 are deposited on one end side of each active region, and the silicon nitride film is deposited from a portion of the tk plane and the substrate surface of the gate electrode 3.4 on the other end side. (Figure 3) 0 On the substrate surface from which the silicon nitride film has been removed, a polycrystalline silicon gate electrode 3.4 is masked and phosphorus is concentrated on the surface to a junction depth of 1 μm. ions are implanted into the active region, and N-type regions 13 and 14 are formed at the other end of the active region.
is formed, and an aluminum wiring electrode 15 is conductively coupled to the reverse surface of the gate electrode 3.4 to complete the process as shown in FIG. Add gate electrodes to each active region in this completed M08 circuit! # Form a memory cell with a minimum confectionary area consisting of a wooden electrode and an N-type region.

FIG. 5 is a partial top view showing the 4-bit matrix section 5j- of the completed MOB integrated circuit of FIG. 4.

As shown in this figure, the gate electrode 3 that connects the N-type region 13 of the memory cell and the element electrode 11 through a conductive channel overlaps with the element electrode 11, so the area is smaller than that of a conventional one-transistor memory cell. Miniaturization is performed. Further, the conductive bond between the gate electrodes 3, 4 and the wiring 1 pole 15 is obtained on the etched surface of the silicon nitride film, and since the silicon nitride film has etching selectivity with respect to the silicon oxide film, it takes 0.5 to 2 μms! A highly reliable conductive bond can be obtained on the microscopic surface.

Although one embodiment of the present invention has been described above, the present invention is not limited to integrated circuits for memory as described above.

Also applicable to MO8 integrated circuits for logic.

The conductive type, electrode material, insulator, etc. used are a must! may be changed accordingly.

[Brief explanation of the drawing]

Figures wJ1 to 4 are diagrams 11'rl1 showing the sequence of steps in the main manufacturing process of an embodiment of the present invention, and Figure 5 is a top view of the embodiment of the present invention. In addition, in the figure, 1.1...P-type silicon single crystal substrate,
2... Gate insulating film, 3.4... Gate electrode, 5,
6... Silicon densified film, 7.8... 7 Recondensed film, 9... Silicon oxide film, 10... High a degree Pg region, 11... Capacitor collector electrode, 12. . . . silicon oxide film, 13. 14 . . N type region, 15 . . . wiring electrode.

Claims (1)

[Scope of Claims] A gate electrode is provided on a semiconductor substrate of one conductivity type (a gate electrode is provided through a first insulating film, and the opposite conductivity type has a planar shape in which the gate electrode and its end are aligned with the semiconductor substrate of -conductivity type) A capacitive element electrode is provided on the gate 1N electrode via a second insulating film, and a wiring is provided on the capacitive element electrode via a third insulating film. 7.