JPH04361566A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enable a resistor to be lessened in both occupied area and parasitic capacitance by a method wherein a through-hole is provided to an interlayer insulating film on a semiconductor substrate, and the resistor is formed inside the through-hole. CONSTITUTION:A first wiring 3 is formed on a silicon substrate 1 through the intermediary of a silicon oxide film 2, and an interlayer insulating film 4 is formed on the first wiring 3. A through-hole is made in the interlayer insulating film 4, and a resistor 5 connected to an end of the first wiring 3 and an Au electrode 6 connected to the other end of the wiring 3 are provided inside the through-hole concerned. By this constitution, the resistor 5 is equal in occupation plane area to a through-hole which connects the first wiring 3 with the second wiring 7, for instance, 2mumX2mum and can be lessened in parasitic capacitance because it is provided vertical to the main surface of a semiconductor substrate.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to semiconductor integrated circuits.
Especially regarding the structure of the resistor.

0002

2. Description of the Related Art As shown in FIG. 3, the structure of a resistor formed in a conventional semiconductor integrated circuit includes a resistor 15 formed on a semiconductor substrate 11 via a silicon oxide film 12, and Contact holes 16 are formed by opening the insulating film 14 on both ends of the resistor 15, and wirings 13A and 13B are connected to the resistor 15 through the contact holes 16 and are made of the same metal layer. It had become. In this structure, the resistor 15 is connected to other elements within the same semiconductor integrated circuit, power supply wiring, etc. via wirings 13A and 13B. FIG. 3 shows an example in which one wiring 13A connected to the resistor 15 is connected to the power wiring 18 via a through hole provided in an interlayer insulating film 17 formed thereon. .

The resistor 15 may be formed by diffusion or ion implantation into a single crystal semiconductor in a region separated from the surroundings by a PN junction, or may be formed on an insulating film on the main surface of the semiconductor substrate and doped with impurities. There are cases where the polysilicon layer is mixed with.

0004

[Problems to be Solved by the Invention] In the conventional semiconductor integrated circuit shown in FIG. 3, the resistor is placed horizontally on the main surface of the semiconductor substrate, so it requires a considerable area. It has the disadvantage of having a parasitic capacitance between it and the semiconductor substrate.

For example, the size of the contact hole is 2 μm×2
μm, the wiring margin of the contact hole is 2 μm, the wiring spacing is 4 μm, and the thickness of the silicon oxide film on the semiconductor substrate is 1 μm.
In a device with a size of μm, the area occupied by the resistor needs to be about 10 μm×20 μm, and the parasitic capacitance is about 7×10 −3 pF. Especially E
In a CL gate array or the like, 1/4 of the chip area is occupied by the resistor.

[0006]

[Means for Solving the Problems] A semiconductor integrated circuit of the present invention includes a first metal wiring formed on a semiconductor substrate via an insulating film, and an interlayer insulating film formed on the first metal wiring. a resistor embedded in a through hole formed in the interlayer insulating film and having one end connected to the first metal wiring; and a resistor formed on the interlayer insulating film and connected to the other end of the resistor. and a second metal wiring.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. Figure 1
1 is a sectional view of a semiconductor chip according to a first embodiment of the present invention.

In FIG. 1, a first wiring 3 is formed on a silicon substrate 1 with a silicon oxide film 2 interposed therebetween.
An interlayer insulating film 4 is formed on the first wiring 3, a through hole is provided in the interlayer insulating film 4, and a resistor 5 connected to one end of the first wiring 3 is provided in the through hole.
and an Au electrode 6 connected to the other end of the first wiring. A second wiring 7 connected to the resistor 5 and a wiring 8 connected to the Au electrode 6 are provided on the interlayer insulating film 4.

As a method for forming the resistor 5, for example, a first wiring 3 made of Au is formed, and an interlayer insulating film 4 such as PSG is formed.
After growing a through hole in the interlayer insulating film 4 using a method such as anisotropic dry etching, a polysilicon layer containing impurities is further grown and etched to form a polysilicon film only in the through hole. Use methods such as filling the Further, the Au electrode 6 is formed by, for example, an Au plating method. The second wiring 7 and the wiring 8 are formed of Au, Al, or the like.

As described above, in the structure of the resistor in the first embodiment, the planar area occupied by the resistor is the first
The area of the through hole connecting the wiring 3 and the second wiring 7 can be the same, for example, 2 μm x 2 μm, and the parasitic capacitance due to the resistor can be reduced because the resistor is perpendicular to the main surface of the semiconductor substrate. Therefore, it is significantly reduced.

FIG. 2 is a cross-sectional view of a second embodiment of the invention.

In FIG. 2, a first wiring 3 formed on a silicon substrate 1 via a silicon oxide film 2, an interlayer insulating film 4, a resistor 5, an Au electrode 6, a second wiring 7A, and a wiring 8A. is almost the same as the first embodiment. In the second embodiment, a second interlayer insulating film 4A is further formed on the second wiring 7A, and a second resistor 5A is provided in the through hole of this second interlayer insulating film. The end portion is connected to the third wiring 9.

In the second embodiment, the first wiring 3
The resistor interposed between and the third wiring 9 is made by a combination of two types of resistors 5 and 5A formed in separate steps of the process, and has the following advantages in addition to the advantages of the first embodiment: It has the following advantages. That is, in order to obtain a desired resistance value, after forming the first type of resistor 5, its resistance value is measured, and based on the results, the conditions for forming the second type of resistor 5A,
For example, the impurity concentration of the polysilicon layer can be adjusted. By using the first type of resistor and the second type of resistor independently, in addition to the case where the above two types of resistors are used in series, there is of course the advantage that the number of types of resistors increases. It is.

[0014]

[Effects of the Invention] As explained above, the present invention forms through holes in an interlayer insulating film formed on a semiconductor substrate,
Since the resistor is formed inside the resistor, the area occupied by the resistor can be significantly reduced, and the parasitic capacitance thereof can be reduced.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a first embodiment of the invention.

FIG. 2 is a sectional view of a second embodiment of the invention.

FIG. 3 is a sectional view of a conventional example.

[Explanation of symbols]

1 Silicon substrate 2 Silicon oxide film 3 First wiring 4,4A　　Interlayer insulation film 5,5A Resistor 6 Au electrode 7,7A Second wiring 8,8A wiring 9 Third wiring 11 Semiconductor substrate 12 Silicon oxide film 13A, 13B Wiring 14 Insulating film 15 Resistor 16,16A Contact hole 17 Interlayer insulation film 18 Power wiring

Claims (1)

[Claims] 1. A first metal wiring formed on a semiconductor substrate via an insulating film, an interlayer insulating film formed on the first metal wiring, and a through hole formed in the interlayer insulating film. a resistor embedded in the resistor and having one end connected to the first metal wiring; and a second metal wiring formed on the interlayer insulating film and connected to the other end of the resistor. semiconductor integrated circuits.