JPS6370552A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the occupying area of a resistance element, and to scale down chip size by forming a thin-film resistor to the upper section of a diffusion region consisting of a diffusion layer shaped onto the main surface of a semiconductor substrate through an insulating film and changing a resistance region into three dimensions. CONSTITUTION:A thin film resistor composed of a polysilicon layer 7 is formed onto a P-type semiconductor region 3 as a diffusion resistor through a first layer insulating film 6 as an silicon oxide film so as to be positioned between electrodes 5a, 5b. Aluminum electrodes 5c, 5d are brought into contact with both ends of the polysilicon layer 7, and used as terminals for the thin-film resistor. The aluminum electrodes 5a-5d are shaped in such a manner that a second layer insulating film 8 as a PSG film is formed onto the polysilicon layer 7, contact holes 9a-9d are shaped to the insulating film 8 and the first layer insulating film 6, and an aluminum layer is evaporated, and patterned.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor integrated circuit technology and to a technology that is particularly effective when applied to the formation of resistive elements in semiconductor integrated circuit devices.

[Prior Art] Conventionally, resistive elements in semiconductor integrated circuits have generally been made of a diffusion layer formed on the main surface of a semiconductor substrate, or a material such as nichrome or tantalum formed on an oxide film formed on the surface of a semiconductor substrate. It was composed of a thin film resistor consisting of a metal layer or a semiconductor layer such as polysilicon ([``Semiconductor Handbook (2nd edition)'' published by Coohm Co., Ltd. in June 1981, pp. 335-337). (See page 582).

[Problems to be Solved by the Invention] A resistance element formed in a semiconductor integrated circuit device has a sheet resistance of approximately several hundred Ω/unit, and thus requires a larger area than a transistor.

Moreover, although transistors in semiconductor integrated circuits are becoming increasingly miniaturized, resistive elements on chips cannot be reduced at the same rate as transistors are miniaturized. However, in conventional semiconductor integrated circuit devices,
Each resistive element was formed at a separate location on the substrate.

Therefore, the ratio of the area occupied by the resistive element on the semiconductor substrate becomes larger and larger as the degree of integration increases, making it difficult to reduce the chip size.

An object of the present invention is to reduce the area occupied by a resistance element in a semiconductor integrated circuit device, thereby reducing the chip size.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, a thin film resistor is formed above a diffusion region made of a diffusion layer formed on the main surface of a semiconductor substrate with an insulating film interposed therebetween, thereby making the resistance region three-dimensional.

[Operation] According to the above-mentioned means, the resistance value for the same area can be approximately doubled compared to the case where only a diffused resistance or a thin film resistance is used, thereby reducing the area occupied by the resistance element. This makes it possible to achieve the above objective of reducing the chip size.

Embodiment FIGS. 1 and 2 show an embodiment of the cross-sectional structure and layout of an element when the present invention is applied to a bipolar integrated circuit device.

In this embodiment, a semiconductor substrate 1 such as single crystal silicon is used.
An N-type epitaxial layer 2 is formed on the main surface of the N-type epitaxial layer 2 by a vapor phase growth method, and on the surface of this N-type epitaxial layer 2,
A P-type semiconductor region 3 serving as a diffused resistance is formed. This semiconductor region 3 is formed, for example, simultaneously or independently with a base region of a bipolar transistor (not shown).

The semiconductor region 3 is surrounded by a relatively thick silicon oxide film 4 for element isolation called a field oxide film. Aluminum electrodes 5 are provided at both ends of the P-type semiconductor region 3.
a and 5b are in contact with each other, and these aluminum electrodes 5a and 5b are used as terminals of a diffused resistor.

In this embodiment, a thin film resistor made of a polysilicon (polycrystalline silicon) layer 7 is installed on the P-type semiconductor region 3 as the diffused resistor via a first interlayer insulating film 6 such as a silicon oxide film. Electrode 5a.

5b. Aluminum electrodes 5C95d are in contact with both ends of this polysilicon layer 7, and serve as terminals of a thin film resistor.

Note that the aluminum electrodes 58 to 5d are connected to the polysilicon layer 7.
A second interlayer insulating film 8 such as a PSG (phosphorus silicate glass) film is formed thereon, contact holes 9a to 9d are formed in this insulating film 8 and the first interlayer insulating film 6, and then aluminum is formed. It is formed by depositing a layer and then patterning it.

FIG. 2 shows an example of the layout of a transistor region and a resistor region when a resistor element having the above structure is applied to a bipolar integrated circuit.

In FIG. 2, a portion designated by numeral 10 is a transistor forming region, and a portion designated by numeral 3 is a P-type semiconductor region serving as a diffused resistance. Further, reference numeral 7 indicates a thin film resistor made of a positive silicon layer, and reference numerals 9a to 9d indicate contact holes for aluminum electrodes 58 to 5d as connecting terminals of each resistor.

As is clear from FIG. 2, according to this embodiment.

Two resistive elements can be formed in the same area on the semiconductor substrate so that they overlap vertically.
The area occupied by the resistor is reduced.

In other words, if the resistor elements formed on the semiconductor substrate are only diffused resistors or thin film resistors, in order to form the same number of resistors and transistors as shown in Figure 2, the resistors must be placed in separate areas as shown in Figure 4. had to be formed. On the other hand, according to the embodiment described above, the resistance area is made three-dimensional, so that the area occupied by the entire resistance area is reduced to about half that of the layout method shown in FIG.

Note that the diffused resistor 3 shown in the above embodiment (Fig. 2)
Although the thin film resistor 7 and the thin film resistor 7 may be used as separate resistance elements, it is preferable to short-circuit the diffusion layer (3) and the polysilicon M (7) at one end and use them as one resistor. You can.

In other words, it is used as a folding resistor.

Further, in the above embodiment, the diffused resistor 3 and the thin film resistor 7 are completely overlapped, but the longitudinal direction of each resistor region is
They may be crossed at right angles or diagonally as shown in the figure. If this is done, the area efficiency will be somewhat lower than the layout method shown in Figure 2, but compared to the layout method shown in Figure 4. The area occupied by the resistor can be significantly reduced. Furthermore, the degree of freedom in layout is increased.

Moreover, in the embodiment shown in FIG. 2, the aluminum electrode 5a.

In order to prevent short circuits between 50 and 5b and 5d, there was a restriction that the length of the polysilicon layer 7 had to be shorter than the length of the diffusion layer 3 by a certain amount, but in the embodiment shown in FIG. There are no such restrictions.

In addition, in the embodiment shown in FIG. 2, the step of the insulating film in the area where the aluminum electrodes 5a and 5d are formed is large, but in the embodiment of FIG. becomes.

In the above embodiment, it was explained that the thin film resistor 7 is constituted by a polysilicon layer, but it is not limited thereto, and a gold RIA layer such as nichrome or tantalum may be used. However, in recent years, In semiconductor integrated circuits, polysilicon layers are often used for the emitter electrode of bipolar transistors and the gate electrode of MOSFETs, so if polysilicon is used in such cases, the polysilicon electrode and polysilicon resistor can be separated. can be formed simultaneously.

As explained above, in the above embodiment, the thin film resistor is formed above the resistance region made of the diffusion layer formed on the main surface of the semiconductor substrate via the insulating film, so that the resistance value for the same area is reduced. Since the size can be approximately doubled compared to the case where only a diffused resistor or a thin film resistor is used, the area occupied by the resistive element is reduced, which has the effect of reducing the chip size.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above embodiment, the resistance region has a two-stage structure of a diffused resistor and a thin film resistor, but a second thin film resistor made of a polysilicon layer or the like is placed on top of the polysilicon layer 7 with an insulating film 8 interposed therebetween. may be formed.

In the above explanation, the invention made by the present inventor was mainly applied to bipolar integrated circuits, which is the background field of application. Can be used generally.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

In other words, when forming a resistor on a semiconductor substrate, the area occupied by the resistor element can be reduced, thereby reducing the chip size9.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the structure of a resistance region in a semiconductor integrated circuit device according to the present invention, and is a sectional view taken along the line I-■' in FIG. FIG. 2 is an explanatory plan view showing an example of the layout of an element when the resistor structure according to the present invention is applied, FIG. 3 is an explanatory plan view showing another embodiment of the present invention, and FIG. FIG. 2 is an explanatory plan view showing a layout corresponding to FIG. 2 in the case of using . 1... Semiconductor substrate, 3... Diffused resistance (P-type semiconductor region), 5a to 5d... Aluminum electrode, 6, 8...
...Insulating film, 7...Polysilicon layer (thin film resistor) 9
8 to 9d...contact hole, 10...transistor formation region. Figure 1 Figure 2 Figure 3 Figure 74

Claims (1)

[Claims] 1. A semiconductor integrated circuit characterized in that a thin film resistance element is formed on a semiconductor region as a resistance region formed on one main surface of a semiconductor substrate with an insulating film interposed therebetween. Device. 2. The semiconductor integrated circuit device according to claim 1, wherein the thin film resistive element is arranged on the resistive region so that its longitudinal direction is orthogonal to the longitudinal direction of the resistive region. . 3. The semiconductor integrated circuit device according to claim 1 or 2, wherein the thin film resistive element is formed of a polycrystalline silicon layer.