JP2869978B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2869978B2 JP2869978B2 JP63241468A JP24146888A JP2869978B2 JP 2869978 B2 JP2869978 B2 JP 2869978B2 JP 63241468 A JP63241468 A JP 63241468A JP 24146888 A JP24146888 A JP 24146888A JP 2869978 B2 JP2869978 B2 JP 2869978B2
- Authority
- JP
- Japan
- Prior art keywords
- conductive layer
- insulating film
- interlayer insulating
- thickness
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に多層配線構造を有す
る半導体装置に関する。The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a multilayer wiring structure.
従来の半導体装置は、第４図（ａ），（ｂ）に示すよ
うに、シリコンからなる半導体基板41上に酸化シリコン
膜42、その上に電極配線等の第１の導電層43がありそれ
らを覆って層間絶縁膜44があり、その上に第２の導電層
45がある。この第２の導電層45は層間絶縁膜44を介して
第１の導電層43の上に載っているか、または第５図に示
すように層間絶縁膜54を介して、第２の導電層55が第１
の導電層53を覆っているような構造となっており、第１
の導電層上の第２の導電層の導電層の膜厚ａが第１の導
電層側部の第２の導電層の膜厚ｂと同じであった。In a conventional semiconductor device, as shown in FIGS. 4A and 4B, a silicon oxide film 42 is provided on a semiconductor substrate 41 made of silicon, and a first conductive layer 43 such as an electrode wiring is provided thereon. There is an interlayer insulating film 44 covering the second conductive layer
There are 45. The second conductive layer 45 is placed on the first conductive layer 43 via the interlayer insulating film 44 or, as shown in FIG. 5, via the interlayer insulating film 54, Is the first
Of the first conductive layer 53.
The thickness a of the conductive layer of the second conductive layer on the conductive layer was the same as the thickness b of the second conductive layer on the side of the first conductive layer.
上述した従来の半導体装置は、第２の導電層が第１の
導電層の上にあるかまたは第１の導電層を覆って第２の
導電層が載って並行配置されている構造となっており第
１の導電層上の第２の導電層の膜厚ａが第１の導電層側
部の第２の導電層の膜厚ｂと同じとなっているので第1,
第２の導電層の重なりによる段差が大きくなり、形状が
悪くなるという欠点がある。たとえば第４図（ｂ）のよ
うに第1,第２の導電層が重なっている上を第３の導電層
47が横ぎる場合に、第1,第２の導電層の重なりによる段
差が大きいため、第３の導電層の形状が悪くなり、導電
層の抵抗が上がることやマイグレーションの悪化などの
問題が起こる。The above-described conventional semiconductor device has a structure in which the second conductive layer is on the first conductive layer or the second conductive layer is placed in parallel with the first conductive layer so as to cover the first conductive layer. The thickness a of the second conductive layer on the first conductive layer is the same as the thickness b of the second conductive layer on the side of the first conductive layer.
There is a disadvantage that the step due to the overlap of the second conductive layer is increased and the shape is deteriorated. For example, as shown in FIG. 4 (b), the third conductive layer overlaps the first and second conductive layers.
When 47 crosses, since the step due to the overlap of the first and second conductive layers is large, the shape of the third conductive layer is deteriorated, and problems such as an increase in resistance of the conductive layer and deterioration of migration occur. .
本発明の目的は、配線の重なり部における段差が比較
的少ない半導体装置を提供することとにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a relatively small step in an overlapping portion of wiring.
本発明による半導体装置は、第１の導電層と、前記第
１の導電層を覆う第１の層間絶縁膜と、前記第１の層間
絶縁膜上に設けられ前記第１の導電層上に重ねて敷設さ
れた第２の導電層と、前記第２の導電層を覆う第２の層
間絶縁膜と、前記第２の層間絶縁膜上に設けられ前記第
１及び第２の導電層の積層部においてこれらを横切って
敷設された第３の導電層とを備える半導体装置であっ
て、前記第１の層間絶縁膜は、前記第１の導電層の上面
部を覆う第１の部分と前記第１の導電層の側面部を覆う
第２の部分とを少なくとも有し、前記第２の導電層は、
前記第１の層間絶縁膜の前記第１の部分上に設けられた
第３の部分と前記第１の層間絶縁膜の前記第２の部分上
に設けられた第４の部分とを少なくとも有し、前記第２
の導電層の前記第３の部分の膜厚は、前記第２の導電層
の前記第４の部分の膜厚よりも薄いことを特徴とする。A semiconductor device according to the present invention includes a first conductive layer, a first interlayer insulating film covering the first conductive layer, and a layer provided on the first interlayer insulating film and overlying the first conductive layer. A second conductive layer laid down, a second interlayer insulating film covering the second conductive layer, and a laminated portion of the first and second conductive layers provided on the second interlayer insulating film And a third conductive layer laid across the first and second conductive layers, wherein the first interlayer insulating film includes a first portion covering an upper surface portion of the first conductive layer and the first portion. And at least a second portion covering a side surface portion of the conductive layer, wherein the second conductive layer comprises:
At least a third portion provided on the first portion of the first interlayer insulating film and a fourth portion provided on the second portion of the first interlayer insulating film are provided. , The second
The thickness of the third portion of the conductive layer is smaller than the thickness of the fourth portion of the second conductive layer.
次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図（ａ），（ｂ）は本発明の第１の実施例を説明
するための製造工程順に配置した半導体チップの縦断面
図である。1 (a) and 1 (b) are longitudinal sectional views of semiconductor chips arranged in the order of manufacturing steps for explaining a first embodiment of the present invention.
第１図（ａ）において、半導体基板11上に酸化シリコ
ン膜12を形成したものを下地（基板）として第１の導電
層13があり、それらを覆って層間絶縁膜14があり、第１
の導電層に応じて形成されるメサ部を備えた層間絶縁膜
14を介して第２の導電層15が第１の導電層13を覆ってお
り、第１の導電層13上にある第２の導電層15の膜厚ａが
第１の導電層13の側部にある第２の導電層14の膜厚ｂよ
りも小さい。この構造により、第１図（ｂ）に示すよう
に、第１の導電層13と第２の導電層15とが重なってでき
る段差を少なくでき、その段差部分を横切る第３の導電
層17の段部での形状がよくなり、第３の導電層の段切れ
などの問題をなくすことができる。In FIG. 1 (a), there is a first conductive layer 13 with a silicon oxide film 12 formed on a semiconductor substrate 11 as a base (substrate), and an interlayer insulating film 14 covering them.
Interlayer insulating film having a mesa formed according to a conductive layer
The second conductive layer 15 covers the first conductive layer 13 via the first conductive layer 13, and the thickness a of the second conductive layer 15 on the first conductive layer 13 is smaller than that of the first conductive layer 13. It is smaller than the thickness b of the second conductive layer 14 in the portion. With this structure, as shown in FIG. 1 (b), the step formed by the overlap of the first conductive layer 13 and the second conductive layer 15 can be reduced, and the third conductive layer 17 crossing the step can be reduced. The shape at the step portion is improved, and problems such as disconnection of the third conductive layer can be eliminated.
ここで、第２の導電層15は、CVD成長した多結晶シリ
コン膜に有機樹脂に塗布した後、エッチバックして、有
機樹脂の膜厚の薄い部分の多結晶シリコン膜すなわち、
第１の導電層上の多結晶シリコン膜を所定の厚さにした
後にフォトレジストを使って多結晶シリコン膜をパター
ンニングしたものである。Here, the second conductive layer 15 is applied to an organic resin on a polycrystalline silicon film grown by CVD, and then etched back to form a portion of the polycrystalline silicon film having a small thickness of the organic resin, that is,
After the polycrystalline silicon film on the first conductive layer has a predetermined thickness, the polycrystalline silicon film is patterned using a photoresist.
第２図（ａ），（ｂ）は第１の実施例の変種を説明す
るための製造工程順に配置した半導体チップの縦断面図
である。2 (a) and 2 (b) are longitudinal sectional views of semiconductor chips arranged in the order of manufacturing steps for explaining a variation of the first embodiment.
第２図（ａ）において、Ｎ型シリコンからなる半導体
基板21表面にP-型ウェル28とN+拡散層29があり、半導体
基板21上には、酸化シリコン膜22と第１の導電層23があ
り、第１の導電層23はN+拡散層29を介して半導体基板21
と接続している。さらに、これら酸化シリコン膜22と第
１の導電層23を覆って層間絶縁膜24がありその上に第２
の導電層25がある。ここで第２の導電層25は、前述のよ
うに、多結晶シリコンをエッチバックによって、第１の
導電層上の第２の導電層の膜厚が第１の導電層の側部の
第２の導電層の膜厚よりも小さく形成されている。最後
に第２図（ｂ）に示すように、第２の導電層25を覆って
もう一つの層間絶縁膜26があり、その上にアルミニウム
などからなる第３の導電層27があり、第３の導電層27
は、第１及び第２の導電層の重なった上を横切ってい
る。この列はスタティックメモリのセル内線構造につい
て想定しており、ここでの第１の導電層はGND線、第２
の導電層はVcc線、第２の導電層はディジット線であ
る。In FIG. 2A, a P − -type well 28 and an N + diffusion layer 29 are provided on the surface of a semiconductor substrate 21 made of N-type silicon, and a silicon oxide film 22 and a first conductive layer 23 And the first conductive layer 23 is connected to the semiconductor substrate 21 via an N + diffusion layer 29.
Is connected to Further, an interlayer insulating film 24 covers the silicon oxide film 22 and the first conductive layer 23, and a second insulating film 24
Of the conductive layer 25. Here, as described above, the second conductive layer 25 is formed by etching back polycrystalline silicon so that the thickness of the second conductive layer on the first conductive layer is equal to the thickness of the second conductive layer on the side of the first conductive layer. Is formed smaller than the thickness of the conductive layer. Finally, as shown in FIG. 2 (b), there is another interlayer insulating film 26 which covers the second conductive layer 25, on which a third conductive layer 27 made of aluminum or the like is provided. Conductive layer 27
Crosses over the overlap of the first and second conductive layers. This column assumes the cell extension structure of the static memory, where the first conductive layer is the GND line,
Is a Vcc line, and the second conductive layer is a digit line.
第３図（ａ），（ｂ）は本発明の第２の実施例を説明
するための製造工程順に配置した半導体チップの縦断面
図である。3 (a) and 3 (b) are longitudinal sectional views of semiconductor chips arranged in the order of manufacturing steps for explaining a second embodiment of the present invention.
第３図（ａ）において、半導体基板31上に酸化シリコ
ン膜32がありその上に第１の導電層33がある。ここで酸
化シリコン膜32はフィールド酸化膜（厚さ300nm）であ
り、第１の導電層33は多結晶シリコン層（厚さ300nm）
とタングステンシリサイド層（厚さ300nm）からなる２
層構造の配線である。次にこれらを覆って層間絶縁膜36
があり、層間絶縁膜34を介して第２の導電層35が第１の
導電層33の両側部にあり第１の導電層33の上にはない構
造となっている。ここで層間絶縁膜34はCVDシリコン酸
化膜（厚さ300nm）であり、第２の導電層35は厚さ500nm
のCVD成長した多結晶シリコン膜をエッチバック技術を
用いてエッチングしたもので第１の導電層33の上部に多
結晶シリコン膜は残っていない。すなわち第３図（ａ）
で、第１の導電層33上の第２の導電層の膜厚は０となっ
ている。次に第３図（ｂ）において、第２の導電層35を
覆ってもう一つの層間絶縁膜36があり、その上に第３の
導電層37がある。第３の導電層37は第１の導電層33と第
２の導電層35の上を横切っている。この実施例では、第
１の導電層33の上部に第２の導電層がないため、第１の
実施例の構造のものよりも第３の導電層の段差部分での
形状がよくなる利点がある。In FIG. 3A, a silicon oxide film 32 is provided on a semiconductor substrate 31, and a first conductive layer 33 is provided thereon. Here, the silicon oxide film 32 is a field oxide film (thickness 300 nm ), and the first conductive layer 33 is a polycrystalline silicon layer (thickness 300 nm ).
And a tungsten silicide layer (thickness: 300 nm ) 2
This is a wiring having a layer structure. Next, an interlayer insulating film 36 is
There is a structure in which the second conductive layer 35 is on both sides of the first conductive layer 33 via the interlayer insulating film 34 and is not on the first conductive layer 33. Here, the interlayer insulating film 34 is a CVD silicon oxide film (thickness 300 nm ), and the second conductive layer 35 is 500 nm thick.
The polycrystalline silicon film grown by CVD is etched using an etch-back technique, and the polycrystalline silicon film does not remain on the first conductive layer 33. That is, FIG.
Thus, the thickness of the second conductive layer on the first conductive layer 33 is zero. Next, in FIG. 3B, there is another interlayer insulating film 36 which covers the second conductive layer 35, and a third conductive layer 37 is provided thereon. The third conductive layer 37 traverses over the first conductive layer 33 and the second conductive layer 35. In this embodiment, since there is no second conductive layer above the first conductive layer 33, there is an advantage that the shape of the step portion of the third conductive layer is better than that of the structure of the first embodiment. .
第２の導電層はメサ部の両方の側面に被着しているの
で、別々の配線として使用できる外、図示しないメサ部
の他の側面で接続するようにすれば一本の配線としても
使用できる。Since the second conductive layer is attached to both side surfaces of the mesa portion, it can be used as separate wires, and can be used as one wire if it is connected to the other side surface of the mesa portion (not shown). it can.
第１の実施例に比較すると第２の導電層の抵抗は大き
くなるが、その抵抗を積極的に利用するところに（例え
ば信号遅延用の抵抗素子として）使用すればよいのであ
る。Although the resistance of the second conductive layer is larger than that of the first embodiment, it can be used where the resistance is actively used (for example, as a resistance element for signal delay).
以上の説明において、第２の導電層は図示の形状をそ
の一部に有しておればよく、その他の部分では第１の導
電層と同様の形状を有していてもよいのである。In the above description, the second conductive layer only needs to have the illustrated shape in part, and may have the same shape as the first conductive layer in other portions.
以上説明したように本発明は、多層配線構造を有する
半導体装置において、第１の導電層上を第２の導電層が
通る場合に第１の導電層とその上の層間絶縁膜とで形成
されるメサ部の側面に最も厚く第２の導電層を設けるこ
とによって、それら第１及び第２の導電層の重なりによ
る段差を少なくできその段差部分を第３の導電層が横ぎ
るような場合に第３の導電層の段差部分での形状がよく
なり、導電層の段切れなどが少なくなり、半導体装置の
信頼性や歩留りが改善される効果がある。As described above, the present invention relates to a semiconductor device having a multilayer wiring structure, which is formed by a first conductive layer and an interlayer insulating film thereover when the second conductive layer passes over the first conductive layer. By providing the thickest second conductive layer on the side surface of the mesa portion, the step due to the overlapping of the first and second conductive layers can be reduced, and the third conductive layer can cross the step. The shape of the third conductive layer at the stepped portion is improved, the level of the conductive layer is reduced, and the reliability and yield of the semiconductor device are improved.
第１図（ａ），（ｂ）及び第２図（ａ），（ｂ）はそれ
ぞれ本発明の第１の実施例及びその変種を説明するため
の製造工程順に配置した半導体チップの縦断面図、第３
図（ａ），（ｂ）は同じく第２の実施例を説明するため
縦断面図、第４図（ａ），（ｂ）及び第５図はそれぞれ
従来例を説明するための縦構造断面図である。 11,21,31,41,51……半導体基板、12,22,32,42,52……酸
化シリコン膜、13,23,33,43,53……第１の導電層、14,2
4,34,44,54……層間絶縁膜、15,25,35,45,55……第２の
導電層、16,26,36,46……層間絶縁膜、17,27,37,47……
第３の導電層、28……P-型ウェル、29……N+型拡散層。FIGS. 1 (a) and 1 (b) and FIGS. 2 (a) and 2 (b) are longitudinal sectional views of semiconductor chips arranged in the order of manufacturing steps for explaining a first embodiment of the present invention and its variants. , Third
4A and 4B are longitudinal sectional views for explaining a second embodiment, and FIGS. 4A, 4B and 5 are longitudinal sectional views for explaining a conventional example. It is. 11, 21, 31, 41, 51 ... semiconductor substrate, 12, 22, 32, 42, 52 ... silicon oxide film, 13, 23, 33, 43, 53 ... first conductive layer, 14, 2
4, 34, 44, 54 ... interlayer insulating film, 15, 25, 35, 45, 55 ... second conductive layer, 16, 26, 36, 46 ... interlayer insulating film, 17, 27, 37, 47 ......
Third conductive layer, 28... P - type well, 29... N + type diffusion layer.
Claims (1)
第１の層間絶縁膜と、前記第１の層間絶縁膜上に設けら
れ前記第１の導電層上に重ねて敷設された第２の導電層
と、前記第２の導電層を覆う第２の層間絶縁膜と、前記
第２の層間絶縁膜上に設けられ前記第１及び第２の導電
層の積層部においてこれらを横切って敷設された第３の
導電層とを備える半導体装置であって、前記第１の層間
絶縁膜は、前記第１の導電層の上面部を覆う第１の部分
と前記第１の導電層の側面部を覆う第２の部分とを少な
くとも有し、前記第２の導電層は、前記第１の層間絶縁
膜の前記第１の部分上に設けられた第３の部分と前記第
１の層間絶縁膜の前記第２の部分上に設けられた第４の
部分とを少なくとも有し、前記第２の導電層の前記第３
の部分の膜厚は、前記第２の導電層の前記第４の部分の
膜厚よりも薄いことを特徴とする半導体装置。A first conductive layer; a first interlayer insulating film covering the first conductive layer; and a first interlayer insulating film provided on the first interlayer insulating film and laid on the first conductive layer. A second conductive layer, a second interlayer insulating film covering the second conductive layer, and a stacked portion of the first and second conductive layers provided on the second interlayer insulating film. A third conductive layer laid across the first conductive layer, wherein the first interlayer insulating film includes a first portion that covers an upper surface of the first conductive layer and the first conductive layer. A second portion that covers at least a side portion of the layer, wherein the second conductive layer includes a third portion provided on the first portion of the first interlayer insulating film and the first portion; At least a fourth portion provided on the second portion of the interlayer insulating film, and the third portion of the second conductive layer
The semiconductor device according to claim 1, wherein the thickness of the portion is smaller than the thickness of the fourth portion of the second conductive layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63241468A JP2869978B2 (en) | 1988-09-26 | 1988-09-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63241468A JP2869978B2 (en) | 1988-09-26 | 1988-09-26 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0287628A JPH0287628A (en) | 1990-03-28 |
| JP2869978B2 true JP2869978B2 (en) | 1999-03-10 |
Family
ID=17074761
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63241468A Expired - Lifetime JP2869978B2 (en) | 1988-09-26 | 1988-09-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2869978B2 (en) |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS532969U (en) * | 1976-06-26 | 1978-01-12 | ||
| JPS57157543A (en) * | 1981-03-25 | 1982-09-29 | Toshiba Corp | Manufacture of semiconductor device |
| JPS61136244A (en) * | 1984-12-07 | 1986-06-24 | Sumitomo Electric Ind Ltd | Wiring process of semiconductor device |
| JP2586038B2 (en) * | 1987-04-04 | 1997-02-26 | ソニー株式会社 | Semiconductor device |
| JPS63132455A (en) * | 1987-04-17 | 1988-06-04 | Nec Corp | Semiconductor integrated circuit |
-
1988
- 1988-09-26 JP JP63241468A patent/JP2869978B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0287628A (en) | 1990-03-28 |
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