JPH09167796A - Ferroelectric storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize high integration by reducing the dimensions of memory cell in the breadthwise direction of both bit line and word line. SOLUTION: Upper electrode 32 of a ferroelectric capacitor 11 is connected electrically with the diffusion layer 24 of an access transistor 12 through the interconnection 41 of different layer from bit line 14. Since the bit line 14 and the interconnection 41 can be arranged three-dimensionally and can be superposed in plan view, dimensions of memory cell can be reduced in the breadthwise direction for both bit line 14 and word line 15.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric memory device in which a memory cell is composed of a ferroelectric capacitor and an access transistor.

[0002]

2. Description of the Related Art FIG. 6 shows an equivalent circuit of a memory cell in a 1-transistor 1-capacitor type ferroelectric memory device. In this memory cell, one electrode of the ferroelectric capacitor 11 and one diffusion layer of the access transistor 12 are electrically connected, and the other electrode of the ferroelectric capacitor 11 is a plate electrode 13. . The bit line 14 is connected to the other diffusion layer of the access transistor 12, and the word line 15 serves as the gate electrode of the access transistor 12.

FIG. 7 shows a conventional example of a ferroelectric memory device. In this conventional example, the element isolation oxide film 22 and the gate oxide film 23 are formed on the surface of the semiconductor substrate 21, and the word line 15 is formed on the gate oxide film 23 and the element isolation oxide film 22. There is. The diffusion layers 2 of the access transistor 12 are formed in the element active regions on both sides of the word line 15.
4 and 25 are formed, and the word line 15 and the like are covered with the interlayer insulating film 26.

A lower electrode 27 as a plate electrode 13 is formed along the word line 15 on the element isolation oxide film 22 and on the interlayer insulating film 26, and a ferroelectric film 31 and an upper portion are formed on the lower electrode 27. The electrodes 32 are sequentially formed to form the ferroelectric capacitor 11.

The ferroelectric capacitor 11 and the like have the interlayer insulating film 3
3 and covers the upper electrode 32 and the diffusion layers 24 and 25.
Connection holes 34 to 36 are formed in the interlayer insulating films 33 and 26. The bit line 14 extends on the element isolation oxide film 22 and on the interlayer insulating film 33, and the branch portion 14 a of the bit line 14 is connected to the diffusion layer 25 via the connection hole 36. The upper electrode 32 and the diffusion layer 24 are connected to each other through the connection holes 34 and 35 by the wiring 37 in the same layer as the bit line 14.

[0006]

However, in the above-mentioned conventional example, since the bit line 14 and the wiring 37 are in the same layer, as seen from FIG. 7B, the bit is seen in a plan view. Since the line 14 and the wiring 37 are lined up in the memory cell, the dimension of the memory cell in the width direction of the bit line 14 cannot be reduced more than twice the minimum wiring pitch.

On the other hand, as shown in FIG. 8, connection holes 35 and 36 are formed.
Are formed in a self-aligned manner with respect to the word lines 15, and the connection holes 3
There is a technique of reducing the size of the memory cell in the width direction of the word line 15 by eliminating the alignment margin between the word lines 15 and 36 and the word line 15.

However, as in the above-mentioned conventional example, the bit line 1
4 and the wiring 37 is the same layer, as shown in FIG. 8, connected between the opposite sides of the wire 37 between the holes 36, the width w ₁ and a minimum feature size w ₂ of at least bifurcation 14a 2 It is necessary to secure an interval of double and sum. Therefore, the connection holes 35, 36
However, even if it is formed in self-alignment with the word line 15, the size of the memory cell in the width direction of the word line 15 could not be sufficiently reduced.

[0009]

According to another aspect of the present invention, there is provided a ferroelectric memory device in which a memory cell is composed of a ferroelectric capacitor having a ferroelectric film as a capacitor dielectric film and an access transistor. The memory device is characterized in that one electrode of the ferroelectric capacitor and one diffusion layer of the access transistor are electrically connected by a wiring in a layer different from a bit line.

A ferroelectric memory device according to a second aspect of the invention is characterized in that the one electrode extends to above the diffusion layer to form the wiring.

According to another aspect of the ferroelectric memory device of the present invention, one electrode of the ferroelectric capacitor and one diffusion layer of the access transistor are electrically connected by a wiring in a layer different from the bit line. These bit lines and wirings can be arranged three-dimensionally, and the bit lines and wirings can be overlapped when viewed two-dimensionally.

According to another aspect of the ferroelectric memory device of the present invention, since one electrode of the ferroelectric capacitor itself extends over the diffusion layer to form a wiring, the pattern of one electrode of the ferroelectric capacitor is formed. It only needs to be changed and there is no need to form new wiring.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION First to fourth specific examples of the present invention applied to a ferroelectric memory device of one-transistor / one-capacitor type cell will be described below with reference to FIGS.
Also in the ferroelectric memory devices of the first to fourth specific examples, the equivalent circuit of the memory cell is as shown in FIG. 6 already described.

FIG. 1 shows a first specific example. In the first specific example, the element isolation oxide film 22 and the gate oxide film 23 are formed on the surface of the semiconductor substrate 21, and the word line 15 is formed on the gate oxide film 23 and the element isolation oxide film 22.
Are formed. Diffusion layers 24 and 25 of the access transistor 12 are formed in element active regions on both sides of the word line 15, and the word line 15 and the like are covered with an interlayer insulating film 26.

A lower electrode 27 as a plate electrode 13 is formed along the word line 15 on the element isolation oxide film 22 and on the interlayer insulating film 26, and a ferroelectric film 31 and an upper portion are formed on the lower electrode 27. The electrodes 32 are sequentially formed to form the ferroelectric capacitor 11.

The ferroelectric capacitor 11 and the like have the interlayer insulating film 3
3, the connection holes 34 and 35 reaching the upper electrode 32 and the diffusion layer 24 are provided in the interlayer insulating films 33 and 26. The upper electrode 32 and the diffusion layer 24 have connection holes 34, 3
The wiring 41 is connected via the wiring 5, and the wiring 41 and the like are covered with the interlayer insulating film 42.

As the material of the wiring 41, any one of polycrystalline Si, tungsten polycide in which WSi is laminated on polycrystalline Si, W, Al or the like is used. Interlayer insulation film 4
2, 33, 26 are provided with connection holes 36 reaching the diffusion layer 25. The bit line 14 extends on the wiring 41 and on the interlayer insulating film 42, and the bit line 14 is connected to the diffusion layer 25 via the connection hole 36.

FIG. 2 shows a second specific example. In the second specific example, the connection hole 35 reaching the diffusion layer 24 is provided in the interlayer insulating film 26, and the wiring 41 is provided between the formation region of the lower electrode 27 and the connection hole 35. The wiring 41 and the like are covered with the interlayer insulating film 43, and the lower electrode 27
A connection hole 34 is provided in the interlayer insulating film 43 in the formation region of.

The connection hole 34 is filled with a plug 44, and a lower electrode 27 connected to the plug 44 is formed. The side wall insulating film 4 is formed on the side surface of the lower electrode 27.
5 are provided. Ferroelectric film 31 and plate electrode 1
The upper electrode 32 as 3 and the upper electrode 32 are formed in the same pattern on the lower electrode 27 to form the ferroelectric capacitor 11.

A connection hole 36 reaching the diffusion layer 25 is provided in the interlayer insulating film 33 and the interlayer insulating films 43 and 26 covering the ferroelectric capacitor 11 and the like, and the bit line 14 is connected through the connection hole 36. It is connected to the diffusion layer 25. Except for the above points, this second specific example also has substantially the same configuration as the first specific example shown in FIG.

FIG. 3 shows a third specific example. In the third specific example, the lower electrode 27 as the plate electrode 13 is used.
And the ferroelectric film 31 are formed in the same pattern on the interlayer insulating film 26, and the side wall insulating film 46 is provided on the side surfaces of the lower electrode 27 and the ferroelectric film 31.

A connection hole 35 reaching the diffusion layer 24 is provided in the interlayer insulating film 26, and an upper electrode 32 extends to above the diffusion layer 24 and is connected to the diffusion layer 24 via the connection hole 35. Except for the above points, this third specific example is also shown in FIG.
It has substantially the same configuration as the second specific example shown in FIG.

FIG. 4 shows a fourth specific example. In the fourth specific example, the lower electrode 27 extends to above the diffusion layer 24 and is connected to the diffusion layer 24 via the connection hole 35.
The upper electrode 32 as the plate electrode 13 and the ferroelectric film 3
It has substantially the same configuration as the third specific example shown in FIG. 3, except that 1 and 1 are formed in the same pattern.

As described above, the wiring 4 of the first and second specific examples
Both the upper electrode 32 of the first and third specific examples and the lower electrode 27 of the fourth specific example overlap with the bit line 14 in plan view. Therefore, the size of the memory cell in the width direction of the bit line 14 can be made smaller than twice the minimum wiring pitch.

If the size of the memory cell in the width direction of the bit line 14 is not restricted by the size of the ferroelectric capacitor 11, the size of the memory cell in the width direction of the bit line 14 is reduced to the minimum wiring pitch. can do.

Further, the wiring 41 of the first and second specific examples, the upper electrode 32 of the third specific example, and the lower electrode 2 of the fourth specific example.
Since all 7 overlap with the bit line 14 in a plan view, the wiring 41 connected to the diffusion layer 24 via the connection hole 35 and the diffusion layer 25 connected via the connection hole 36. It suffices to secure an interval between the bit line 14 and the bit line 14 that does not reduce the withstand voltage.

Therefore, as shown in FIG.
Even when 6 is formed in self-alignment with the word line 15, the distance between the wirings 41 on both sides of the connection hole 36 can be reduced as compared with the conventional example shown in FIG. The size of the memory cell 15 in the width direction can be sufficiently reduced.

Although the above-mentioned first to fourth specific examples apply the invention of the present application to the ferroelectric memory device of one-transistor / one-capacitor type cell, data of "1" and "0" are complemented. Even in a 2-transistor 2-capacitor type cell that accumulates statically, the equivalent circuit shown in FIG. 6 is only configured in a complementary manner. Of course it can be applied.

[0029]

In the ferroelectric memory device according to the first aspect of the present invention, the wiring connected to one electrode of the ferroelectric capacitor and one diffusion layer of the access transistor and the bit line are made to overlap in a plan view. Therefore, the size of the memory cell in both the width direction of the bit line and the width direction of the word line can be reduced, and a high degree of integration can be obtained.

In the ferroelectric memory device according to the second aspect, it is only necessary to change the pattern of one electrode of the ferroelectric capacitor and it is not necessary to newly form wiring, so that the manufacturing cost is high without increasing. The degree of integration can be obtained.

[Brief description of the drawings]

FIG. 1 shows a first specific example of the invention of the present application, (a)
Is a side sectional view taken along the line A-A in FIG.
(B) is a plan view.

FIG. 2 shows a second specific example of the invention of the present application, (a)
Is a side sectional view taken along the line A-A in FIG.
(B) is a plan view.

FIG. 3 shows a third specific example of the invention of the present application, (a)
Is a side sectional view taken along the line A-A in FIG.
(B) is a plan view.

FIG. 4 shows a fourth specific example of the invention of the present application, (a)
Is a side sectional view taken along the line A-A in FIG.
(B) is a plan view.

FIG. 5 is a side sectional view showing a modification of the first to fourth specific examples.

FIG. 6 is an equivalent circuit of a memory cell in a 1-transistor 1-capacitor type ferroelectric memory device to which the present invention can be applied.

FIG. 7 shows a conventional example of the invention of the present application, (a) is a side sectional view taken along the line AA of (b), and (b).
Is a plan view.

FIG. 8 is a side sectional view showing a modified example of a conventional example.

[Explanation of symbols]

 11 Ferroelectric Capacitor 12 Access Transistor 14 Bit Line 24 Diffusion Layer 27 Lower Electrode 31 Ferroelectric Film 32 Upper Electrode 41 Wiring

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical indication H01L 29/788 29/792

Claims (2)

[Claims] 1. A ferroelectric memory device in which a memory cell is composed of a ferroelectric capacitor having a ferroelectric film as a capacitor dielectric film and an access transistor, wherein one electrode of the ferroelectric capacitor and the A ferroelectric memory device, characterized in that one diffusion layer of an access transistor is electrically connected to a wiring in a layer different from a bit line. 2. The one electrode is extended to above the diffusion layer to form the wiring.
The ferroelectric memory device described.