JP3646423B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a ferroelectric capacitor using polarization inversion of a ferroelectric material.
[0002]
[Prior art]
FERAM (ferroelectric memory using a ferroelectric capacitor having a ferroelectric substance between two electrodes and storing binary data according to the direction of polarization of the ferroelectric substance according to the voltage applied to both electrodes. In ferroelectric random access memories, the magnitude of the polarization charge value is proportional to the magnitude of the readout signal quantity. Therefore, in order to improve the reliability of the device, the polarization charge value can be increased or the necessary quantity can be secured. is important.
[0003]
PZT (PbZrTiO ₃ ) is well known as a ferroelectric used in the semiconductor memory, and a compound group called Y-1 has been developed (US Pat. No. 5,519,234).
The polarization charge value of the ferroelectric is proportional to the surface area of the ferroelectric used for the memory capacitor. A similar example is DRAM (dynamic random access memories). A memory capacitor of a DRAM preferably has a large storage capacity for storing binary data, and in order to achieve high integration and downsizing of the device, it is possible to reduce the area occupied by the capacitor while securing a necessary storage capacity. is important. For this reason, a stack type such as a cylindrical type or a fin type or a trench type has been developed as a structure of the memory capacitor. All of these increase the surface area of the capacitor by giving the capacitor a three-dimensional structure, thereby enabling the memory cell area to be reduced.
[0004]
In a ferroelectric memory as well as a DRAM or the like, high integration of a memory and a reduction in size of a device are desired, and reduction of a memory cell size is a big problem. That is, it is necessary to reduce the memory cell area while securing a necessary polarization charge value.
[0005]
[Problems to be solved by the invention]
However, in a ferroelectric capacitor, when the ferroelectric used for the capacitor is formed on an uneven base, the film quality is deteriorated due to non-uniform film thickness. Degradation of film quality degrades reliability, for example, making the operation of the device unstable. Therefore, the ferroelectric must be formed on a flat base so as not to cause nonuniform film thickness. It is difficult to take such a complicated three-dimensional structure.
[0006]
Therefore, the present invention reduces the memory cell area while securing the necessary polarization charge value of the ferroelectric capacitor that cannot take a complicated three-dimensional structure, and can achieve high integration of the memory and reduction of the device. An object is to provide an apparatus.
[0007]
[Means for Solving the Problems]
To achieve the above object, the present invention provides a ferroelectric capacitor having a ferroelectric substance between two electrodes and storing binary data according to the direction of polarization of the ferroelectric substance in accordance with the voltage applied to both electrodes. And a semiconductor memory device having a memory cell composed of a switching field effect transistor connected to the ferroelectric capacitor, the same as two or more layers of ferroelectric capacitors stacked via an insulating layer. A U-shaped planar shape having a first capacitor in a plane and a second capacitor in another same plane , each having a region through which the first capacitor and the second capacitor pass bit contacts. There is provided a semiconductor memory device characterized by having overlapping portions with each other.
[0008]
The semiconductor device of the present invention has two or more ferroelectric capacitors that are stacked with an insulating layer interposed therebetween. When all the capacitors are configured in one layer as in the prior art, the capacitors cannot overlap each other, so that the area of the capacitor cannot be increased. However, by stacking capacitors in two or more layers, it becomes possible for the capacitors to have overlapping portions, and by having such overlapping portions, the area of the capacitor can be expanded compared to the conventional case. Become.
[0009]
Therefore, in a ferroelectric capacitor that needs to be formed on a flat base so as not to cause a non-uniform film thickness, the area of the capacitor can be expanded without any problem, and thus the polarization charge value can be increased. Become. In addition, the area of the memory cell can be reduced while securing a necessary polarization charge value.
[0010]
In the semiconductor device of the present invention, it is preferable that adjacent transistors are connected to capacitors in different layers.
When adjacent transistors are connected to capacitors in different layers, the capacitor can be extended to adjacent transistor regions, and an overlapping portion of the capacitors can be formed, so that the area of the capacitor can be expanded.
[0011]
In the semiconductor device of the present invention, it is preferable that capacitors of two or more layers are repeatedly formed alternately in the bit line direction or the word line direction. Such a structure can be expanded with the same area of each capacitor, and thus is suitable for a ferroelectric capacitor in which the same polarization charge value is required for each capacitor.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a semiconductor device according to the present invention will be described with reference to FIG.
FIG. 1A is an equivalent circuit diagram of an embodiment of a semiconductor device according to the present invention. The (1Tr + 1Cap) type semiconductor memory device in which one memory cell is constituted by one field effect transistor and one ferroelectric capacitor. This corresponds to 4 memory cells. Both a plan view and a cross-sectional view of FIG. 1B show a semiconductor device having the same configuration as the equivalent circuit diagram of FIG.
[0013]
As shown in FIG. 1A, a transistor Tr1 and a capacitor C1 constitute a memory cell MC1, and the same applies to the memory cells MC2 to MC4. The source S of the field effect transistor Tr selected by the word line WL and one electrode of the ferroelectric capacitor C are connected, and the other electrode of the capacitor is connected to the plate line PL. The drain D of the transistor is connected to the bit line BL.
[0014]
The semiconductor memory device of the present invention will be described with reference to the plan view of FIG. 1B and the equivalent circuit diagram of FIG. A word line 31 (WL) is wired up and down in the drawing to form gate electrodes of the transistors Tr1 to Tr4. Transistors Tr1 to Tr4 are constituted by the gate electrode and the source / drain diffusion layers 11 on both sides. In the capacitors C1 to C4, the capacitors 34 and 34 (C1 and C3) are in the same plane, and the capacitors 35 and 35 (C2 and C4) are in another same plane. The lower electrodes of the capacitors C1 to C4 are connected to the source diffusion layer 11 of the transistor via the capacitor contacts 32 and 33, and the upper electrodes of the capacitors C1 to C4 are connected to the plate lines 36 and 37 (PL), so that the drain diffusion of the transistor The layer 11 is connected to the bit line 39 (BL) through the bit contact 38. Ferroelectric capacitors 34 and 35 are formed in a U-shape so as to avoid bit contact, and the capacitors have overlapping portions in the vertical direction. The upper electrode of each ferroelectric capacitor is integrated with plate lines 36 and 37, and the plate line runs parallel to the word line. On the other hand, the bit line is provided in a direction perpendicular to the word line and the plate line.
[0015]
Next, description will be made with reference to FIG. This figure is a cross-sectional view along the plane AA ′ in the plan view of FIG. Further, the display of the element isolation insulating film is omitted. On the P-type semiconductor substrate 10, there is a word line (gate electrode) 31 made of polycide having a two-layer structure of, for example, polysilicon and tungsten silicide via a gate oxide film (not shown), Source / drain diffusion layers 11a and 11b are formed by ion implantation. A bit contact 38 made of polysilicon is shared by two memory cells, and connects a common drain and a bit line 39 made of aluminum. The other diffusion layer of each transistor is connected to the lower electrodes 34c and 35c of the ferroelectric capacitor via the capacitor contacts 32 and 33. The ferroelectric capacitor is disposed on the first ferroelectric capacitor 34 disposed on the first interlayer insulating layer 21 covering the transistor and on the second interlayer insulating layer 22 covering the first ferroelectric capacitor. This is a two-layer configuration with the second ferroelectric capacitor 36 provided. The first interlayer insulating film 21 and the second interlayer insulating film 22 are each made of, for example, silicon oxide. Each of the first ferroelectric capacitor 34 and the second ferroelectric capacitor 35 is composed of three layers of upper electrodes 34a and 35a, ferroelectric films 34b and 35b, and lower electrodes 34c and 35c. A conductor such as Pt can be used as the upper electrodes 34a and 35a, and a Pt / Ti laminated electrode can be used as the lower electrodes 34c and 35c, for example. PZT and Y-1 can be used as the ferroelectric used for the ferroelectric films 34b and 35b. The upper electrodes 34a and 35a are formed integrally with plate electrodes 36 and 37 made of the same material as the upper electrode, and are connected to them.
[0016]
The capacitor according to this embodiment has a two-layer structure of a first ferroelectric capacitor and a second ferroelectric capacitor, which are insulated by a second interlayer insulating film. A capacitor adjacent in the bit line direction has a form in which a first ferroelectric capacitor and a second ferroelectric capacitor are alternately repeated. For example, the capacitor of the memory cell MC2 has a second ferroelectric capacitor, and the capacitors of the adjacent memory cells MC1 and MC3 have a first ferroelectric capacitor.
[0017]
As described above, the ferroelectric capacitor of the present invention has an overlapping portion between adjacent capacitors by adopting a two-layer configuration with an insulating layer interposed therebetween, so that the occupable area of each capacitor can be expanded. Since the area of the ferroelectric film can be increased, the polarization charge value can be increased, and the area occupied by each ferroelectric capacitor can be reduced while securing the required polarization charge value, thereby increasing the memory integration and the device. Can be reduced.
[0018]
Next, a method for manufacturing the semiconductor memory device of this embodiment will be described with reference to FIG.
First, the process leading to FIG. 2A will be described. An element isolation insulating film (not shown) is formed on the P-type semiconductor substrate 10, and a word line (gate electrode) 31 is formed after the gate oxide film is formed. Thereafter, source / drain diffusion layers 11a and 11b are formed by ion implantation to complete a field effect transistor. A first interlayer insulating film 21 is formed by depositing PSG or BPSG so as to cover the transistor and planarizing it by reflow or the like.
[0019]
Next, as shown in FIG. 2B, by performing anisotropic etching after resist formation, capacitor contact holes are opened in every other source diffusion layer 11a of the transistor, and the surface of the diffusion layer is formed. Expose. The opened contact hole is filled with polysilicon deposition and etch back to form a capacitor contact 32, which is connected to the source diffusion layer 11a. Further, a Pt / Ti layer serving as a lower electrode of the capacitor and a PZT layer serving as a ferroelectric film are deposited thereon, and resist patterning is performed in a U-shape in the shape of the capacitor electrode. Further, a Pt layer serving as an upper electrode is deposited on the upper portion and patterned to form the upper electrode 34a and the plate line 36 integrally. As a result, the first ferroelectric capacitor 34 having a three-layer structure of the upper electrode 34a, the ferroelectric film 34b, and the lower electrode 34c is completed. The first ferroelectric capacitor is covered, PSG or the like is deposited, and planarized by reflow or the like to form the second interlayer insulating film 22, and the first ferroelectric capacitor and the second ferroelectric capacitor to be formed next And insulate.
[0020]
Next, as shown in FIG. 2C, the second ferroelectric capacitor 35 and the plate line 37 are formed by the same method as that for forming the first ferroelectric capacitor 34, and the upper part is formed on the third interlayer. Cover with an insulating film 23. However, the capacitor contact of the second ferroelectric capacitor 35 is connected to the first interlayer insulating film 21 and the second interlayer insulating film 22 with respect to the source diffusion layer 11a of the transistor not connected to the first ferroelectric capacitor. Open to penetrate through.
[0021]
Finally, the bit contact 38 is formed by opening the bit contact with respect to the drain diffusion layer 11b and burying a polysilicon plug in the bit contact hole, and the bit line 39 is formed by sputtering aluminum, so that the semiconductor memory shown in FIG. The device is completed.
[0022]
In the semiconductor device manufacturing method of the present embodiment, the second interlayer insulating film is deposited so as to cover the entire surface of the formation of the first ferroelectric capacitor. As a result, insulation between the first ferroelectric capacitor and the second ferroelectric capacitor to be formed later is ensured, and the capacitors of each layer can have an overlapping portion, and the area of the capacitor can be expanded as compared with the conventional case. It becomes possible. At this time, the capacitor contact of the second ferroelectric capacitor in the upper layer needs to be opened so as not to expose the first ferroelectric capacitor in order to ensure insulation. Further, the ferroelectric capacitor is formed in a U-shape, and an area for passing a bit contact is provided. In this case, it is possible to avoid forming a complicated U-shaped shape by appropriately changing the position of the bit contact.
[0023]
The present invention is not limited to the above embodiment. For example, in the present embodiment, one memory cell is described as a (1Tr + 1Cap) type, but it can also be applied to a (2Tr + 2Cap) type semiconductor device. Also, the structure in which the capacitor electrode formed in the first ferroelectric capacitor layer and the capacitor electrode formed in the second ferroelectric capacitor layer are alternately repeated in the bit line direction is shown. The structure may be alternately repeated, or may be alternately repeated for both the bit line and the word line. In this embodiment, the ferroelectric capacitor has a two-layer structure, but three or more layers may be used. Further, although polysilicon is buried in forming the bit contact and the capacitor contact, a metal such as tungsten may be used as the conductor . It can make various changes without departing from the scope of the other invention of that.
[0024]
【The invention's effect】
In the semiconductor memory device of the present invention, the area of each capacitor electrode can be expanded, that is, the area of the ferroelectric film can be expanded, so that the polarization charge value can be increased and the film thickness is flat so as not to cause non-uniform film thickness. In a ferroelectric capacitor that needs to be formed on a base, it is possible to reduce the memory cell area while securing a necessary polarization charge value, thereby enabling high integration of the memory and reduction of the device.
[Brief description of the drawings]
1A and 1B show an embodiment of a semiconductor memory device of the present invention, in which FIG. 1A is an equivalent circuit diagram, FIG. 1B is a plan view, and FIG.
FIGS. 2A and 2B are cross-sectional views showing a manufacturing process of a method of manufacturing a semiconductor memory device according to the present invention, wherein FIG. 2A shows a first interlayer insulating film forming process, and FIG. 2B shows a second interlayer insulating film forming process; (C) shows up to the third interlayer insulating film forming step.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Board | substrate, 11a ... Source diffusion layer, 11b ... Drain diffusion layer, 21 ... 1st interlayer insulation film, 22 ... 2nd interlayer insulation film, 23 ... 3rd interlayer insulation film, 31 ... Word line (gate electrode), 32 33 ... Capacitor contact, 34 ... First ferroelectric capacitor, 34a ... Upper electrode, 34b ... Ferroelectric film, 34c ... Lower electrode, 35 ... Second ferroelectric capacitor, 35a ... Upper electrode, 35b ... Ferroelectric Body film, 35c ... lower electrode, 36, 37 ... plate line, 38 ... bit contact, 39 ... bit line

Claims (2)

A ferroelectric capacitor having a ferroelectric substance between two electrodes and storing binary data according to the direction of polarization of the ferroelectric substance according to the voltage applied to both electrodes, and connected to the ferroelectric capacitor In a semiconductor memory device having a memory cell composed of a field effect transistor for switching,
Having two or more layers of ferroelectric capacitors stacked with an insulating layer between each other, the first capacitor in the same plane and the second capacitor in the same plane,
The semiconductor memory device, wherein the first capacitor and the second capacitor have a U-shaped planar shape provided with regions for passing bit contacts, respectively, and have overlapping portions.   2. The semiconductor memory device according to claim 1, wherein transistors adjacent to each other are connected to ferroelectric capacitors of different layers.

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