JPH1079473A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a memory cell area, while ensuring a necessary polarizing charge value by providing dielectric capacitors having two or more layers deposited via an insulating layer, such that the capacitors mutually overlap with each other at overlapping portions. SOLUTION: A word line 31 is wired in a vertical direction to construct gate electrodes of transistors Tr1 to Tr4. Each of the transistors Tr1 to Tr4 is constructed with the gate electrode and source-drain diffusion layer 11 on both sides of the gate electrode. Capacitors 34, 34 (C1, C3) are flush with each other, and capacitors 35, 35 (C2, C4) are flush with in another plane. The lower electrodes of the capacitors C1 to C4 are connected to a source diffusion layer 11a of the transistors via capacitor contacts 32 and 33. The upper electrodes of the capacitors C1 to C4 are connected to plate lines 36 and 37. A drain diffusion layer 11b is connected to a bit line 39 via bit contacts 38. The U-shaped ferroelectric capacitors 34 and 35 respectively have upper and lower overlap portions.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a ferroelectric capacitor utilizing polarization inversion of a ferroelectric.

[0002]

2. Description of the Related Art A ferroelectric substance is provided between two electrodes, and the direction of polarization of the ferroelectric substance depends on the voltage applied to both electrodes.
FERAM (ferroelectric random a), which is a ferroelectric memory using a ferroelectric capacitor for storing value data
In ccess memories), the magnitude of the polarization charge value is proportional to the magnitude of the read signal amount, so it is important to increase the polarization charge value or secure the required amount to improve the reliability of the device. is there.

As a ferroelectric used in the above semiconductor memory, PZT (PbZrTiO ₃ ) is well known.
A group of compounds called -1 has been developed (US Pat. No. 5,519,234). The polarization charge value of the ferroelectric is proportional to the surface area of the ferroelectric used for the memory capacitor. A similar example is the DRAM (dynamic rand
om access memories). It is preferable that the storage capacitor of the DRAM has a large storage capacity for storing binary data. To achieve high integration and miniaturization of the device, it is necessary to reduce the area occupied by the capacitor while securing the necessary storage capacity. is important. For this reason, a stack type such as a cylindrical type or a fin type, or a trench type has been developed as a memory capacitor structure. All of these increase the surface area of the capacitor by providing the capacitor with a three-dimensional structure, thereby reducing the memory cell area.

[0004] In the case of ferroelectric memories as well, like DRAMs and the like, high integration of memories and miniaturization of devices are desired, and reduction of the memory cell size is a major issue. That is, it is necessary to reduce the memory cell area while securing the required polarization charge value.

[0005]

However, in a ferroelectric capacitor, when the ferroelectric used for the capacitor is formed on an uneven base, the film quality is deteriorated due to the uneven thickness. I will. Deterioration of film quality lowers reliability, such as making the operation of the device unstable,
The ferroelectric must be formed on a flat underlayer so that the film thickness does not become uneven, and it is difficult to form a complicated three-dimensional structure like a memory capacitor of a DRAM.

Accordingly, the present invention reduces the memory cell area while securing the required polarization charge value of a ferroelectric capacitor which cannot take a complicated three-dimensional structure, and achieves high integration of a memory and downsizing of a device. It is an object to provide a possible semiconductor device.

[0007]

In order to achieve the above-mentioned object, the present invention has a ferroelectric material between two electrodes, and a ferroelectric material having a ferroelectric material depending on the direction of polarization of the ferroelectric material according to the voltage applied to both electrodes.
In a semiconductor memory device having a memory cell composed of a ferroelectric capacitor for storing value data and a switching field-effect transistor connected to the ferroelectric capacitor, the two are stacked with an insulating layer interposed therebetween.
There is provided a semiconductor memory device having at least one ferroelectric capacitor, wherein the ferroelectric capacitors have mutually overlapping portions.

The semiconductor device of the present invention has two or more ferroelectric capacitors stacked on each other with an insulating layer interposed therebetween. When all the capacitors are formed in one layer as in the related art, the capacitors cannot have overlapping portions, and thus the area of the capacitors cannot be increased. However, by stacking two or more layers of capacitors in a three-dimensional manner, the capacitors can have overlapping portions, and by having such overlapping portions, the area of the capacitor can be increased as compared with the conventional case. Become.

Therefore, in a ferroelectric capacitor which needs to be formed on a flat underlayer so that the film thickness does not become nonuniform, the area of the capacitor can be enlarged without inconvenience, and the polarization charge value can be increased. Becomes possible. Further, it is possible to reduce the area of the memory cell while securing a necessary polarization charge value.

In the semiconductor device of the present invention, it is preferable that transistors adjacent to each other are connected to capacitors of different layers. When adjacent transistors are connected to capacitors in different layers, the capacitors can be extended to adjacent transistor regions, and an overlapping portion of the capacitors can be formed, so that the area of the capacitors can be increased.

In the semiconductor device of the present invention, it is preferable that capacitors of each layer having two or more layers are alternately formed in the bit line direction or the word line direction. Such a structure is suitable for a ferroelectric capacitor in which the same polarization charge value is required for each capacitor since the area of each capacitor can be expanded in a uniform manner.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to the present invention will be described below with reference to FIG. FIG. 1A is an equivalent circuit diagram of a semiconductor device according to an embodiment of the present invention, wherein one field-effect transistor and one ferroelectric capacitor form one.
This corresponds to four memory cells of a (1Tr + 1Cap) type semiconductor memory device forming a memory cell. 1B and FIG. 1C both show a semiconductor device having the same configuration as that of FIG. 1A.

As shown in FIG. 1A, a transistor T
The memory cell MC1 is composed of r1 and the capacitor C1, and the same applies to the memory cells MC2 to MC4. The source S of the field-effect transistor Tr selected by the word line WL is connected to one electrode of the ferroelectric capacitor C, and the other electrode of the capacitor is connected to the plate line PL. The drain D of the transistor is connected to the bit line BL.

The semiconductor memory device of the present invention will be described with reference to the plan view of FIG. 1B and the equivalent circuit diagram of FIG. Word lines 31 (WL) are wired up and down in the drawing to form gate electrodes of the transistors Tr1 to Tr4. The transistor T is formed by the gate electrode and the source / drain diffusion layers 11 on both sides.
r1 to Tr4 are configured. Capacitors C1 to C4 have capacitors 34 and 34 (C1, C3) on the same plane,
Capacitors 35, 35 (C2, C4) are in another co-planar plane. The lower electrodes of the capacitors C1 to C4 are connected to the source diffusion layer 11 of the transistor via the capacitor contacts 32 and 33, and the upper electrodes of the capacitors C1 to C4 are connected to the plate lines 36 and 37 (PL), and the drain diffusion of the transistor is performed. The layer 11 is connected to a bit line 39 (BL) via a bit contact 38. U-shaped ferroelectric capacitor 3 to avoid bit contact
4 and 35 are formed, and the capacitor has a vertically overlapping portion. The upper electrode of each ferroelectric capacitor is integrated with the plate lines 36 and 37, and the plate lines run parallel to the word lines. On the other hand, the bit lines are provided in a direction perpendicular to the word lines and the plate lines.

Next, a description will be given with reference to FIG.
This figure is a cross-sectional view along the AA ′ plane in the plan view of FIG. Also, the illustration of the element isolation insulating film is omitted. A word line (gate electrode) 31 made of, for example, polycide having a two-layer structure of polysilicon and tungsten silicide is provided on a P-type semiconductor substrate 10 via a gate oxide film (not shown). Source / drain diffusion layers 11a and 11b are formed by ion implantation. A bit contact 38 made of polysilicon is shared by two memory cells, and connects a common drain and a bit line 39 made of aluminum. The other diffusion layer of each transistor is connected to lower electrodes 34c and 35c of the ferroelectric capacitor via capacitor contacts 32 and 33. The ferroelectric capacitor includes a first interlayer insulating layer 21 covering the transistor.
A two-layer structure of a first ferroelectric capacitor 34 provided thereon and a second ferroelectric capacitor 36 provided on the second interlayer insulating layer 22 covering the first ferroelectric capacitor It is. First interlayer insulating film 21 and second interlayer insulating film 22
Are made of, for example, silicon oxide. The first ferroelectric capacitor 34 and the second ferroelectric capacitor 35 are both upper electrodes 34a, 35a and a ferroelectric film 34, respectively.
b, 35b and lower electrodes 34c, 35c. As the upper electrodes 34a and 35a, for example, Pt
For example, a Pt / Ti laminated electrode can be used as the lower electrodes 34c and 35c. PZT is used as a ferroelectric used for the ferroelectric films 34b and 35b.
And Y-1 can be used. Also, the upper electrodes 34a, 35a
Are plate electrodes 36 and 37 made of the same material as the upper electrode
And are connected to them.

The capacitor of this embodiment has a two-layer structure of a first ferroelectric capacitor and a second ferroelectric capacitor, which are insulated by a second interlayer insulating film. Capacitors adjacent in the bit line direction have a form in which first ferroelectric capacitors and second ferroelectric capacitors are alternately repeated. For example, the capacitor of the memory cell MC2 has the second ferroelectric capacitor, and the capacitors of the adjacent memory cells MC1 and MC3 are the first ferroelectric capacitors.
It has a ferroelectric capacitor.

As described above, since the ferroelectric capacitor of the present invention has a two-layer structure with an insulating layer interposed therebetween, adjacent capacitors can have overlapping portions, so that the occupied area of each capacitor can be increased. In other words, since the area of the ferroelectric film can be increased, the polarization charge value can be increased, and the area occupied by one ferroelectric capacitor can be reduced while securing the required polarization charge value. And the size of the device can be reduced.

Next, a method of manufacturing the semiconductor memory device according to the present embodiment will be described with reference to FIG. First, a process leading to FIG. 2A will be described. An element isolation insulating film (not shown) is formed on the P-type semiconductor substrate 10, and a word line (gate electrode) 31 is formed after forming a gate oxide film. After that, the source / drain diffusion layers 11a,
11b is formed, and the field effect transistor is completed.
A first interlayer insulating film 21 is formed by depositing PSG or BPSG by covering the transistor and flattening it by reflow or the like.

Next, as shown in FIG. 2B, anisotropic etching is performed after the formation of the resist, so that a capacitor contact hole is opened for every other source diffusion layer 11a of the transistor. Expose the surface. Filling the opened contact holes with polysilicon deposition and etch back to form capacitor contacts 32;
Connected to source diffusion layer 11a. Further, a Pt / Ti layer serving as a lower electrode of the capacitor and a PZT layer serving as a ferroelectric film are deposited thereon, and are patterned in a U shape in the shape of the capacitor electrode. Further, a Pt layer serving as an upper electrode is deposited and patterned on the upper portion to integrally form the upper electrode 34a and the plate line 36. Thereby, the first ferroelectric capacitor 3 having a three-layer structure of the upper electrode 34a, the ferroelectric film 34b, and the lower electrode 34c is formed.
4 is completed. Cover the first ferroelectric capacitor and
G or the like is deposited and planarized by reflow or the like to form a second interlayer insulating film 22 to insulate the first ferroelectric capacitor from a second ferroelectric capacitor to be formed next.

Next, as shown in FIG. 2C, a second ferroelectric capacitor 35 and a plate line 37 are formed by the same method as that for forming the first ferroelectric capacitor 34, and the upper part thereof is formed. Cover with a third interlayer insulating film 23. However, the capacitor contact of the second ferroelectric capacitor 35 is
An opening is formed in the source diffusion layer 11a of the transistor not connected to the ferroelectric capacitor so as to penetrate the first interlayer insulating film 21 and the second interlayer insulating film 22.

Finally, a bit contact 38 is formed by burying a polysilicon plug into the bit contact opening and the bit contact opening with respect to the drain diffusion layer 11b.
Wire 3 by sputtering aluminum and aluminum
By the formation of 9, the semiconductor memory device as shown in FIG. 1C is completed.

In the method of manufacturing a semiconductor device according to this embodiment, the second interlayer insulating film is deposited so as to cover the entire surface of the first ferroelectric capacitor. As a result, insulation between the first ferroelectric capacitor and the second ferroelectric capacitor formed thereafter is ensured, and the capacitors in the respective layers can have overlapping portions, thereby increasing the area of the capacitor as compared with the related art. It becomes possible. At this time, the capacitor contact of the upper second ferroelectric capacitor needs to be opened so that the first ferroelectric capacitor is not exposed in order to ensure insulation. Further, the ferroelectric capacitor is formed in a U-shape, and a region for passing a bit contact is provided. In this case, by appropriately changing the position of the bit contact, it is possible to avoid molding into a complicated U-shape.

The present invention is not limited to the above embodiment. For example, in the present embodiment, one memory cell is (1Tr + 1Cap)
Although the description has been given of the type, the present invention can also be applied to a (2Tr + 2Cap) type semiconductor device. Further, the structure in which the capacitor electrode formed on the first ferroelectric capacitor layer and the capacitor electrode formed on the second ferroelectric capacitor layer are alternately repeated in the bit line direction has been described. A structure that repeats alternately may be used, and a structure that repeats alternately to both bit lines and word lines may be used. In this embodiment, the ferroelectric capacitor has a two-layer structure, but may have three or more layers. Although polysilicon is buried in the formation of the bit contact and the capacitor contact, a metal such as tungsten may be used as the conductor. Also, the shape of the capacitor electrode need not be a U-shape. Various other changes can be made without departing from the spirit of the present invention.

[0024]

According to the semiconductor memory device of the present invention, the area of each capacitor electrode can be expanded, that is, the area of the ferroelectric film can be expanded, so that the polarization charge value can be increased.
In a ferroelectric capacitor that needs to be formed on a flat underlayer so that the film thickness does not become uneven, the memory cell area can be reduced while securing the required polarization charge value, and high integration of memory and device Reduction can be made possible.

[Brief description of the drawings]

FIGS. 1A and 1B show an embodiment of a semiconductor memory device of the present invention, wherein FIG. 1A is an equivalent circuit diagram, FIG. 1B is a plan view, and FIG.

FIGS. 2A and 2B are cross-sectional views illustrating a manufacturing process of a method for manufacturing a semiconductor memory device according to the present invention, wherein FIG. 2A is a diagram up to a first interlayer insulating film forming process, and FIG. Until,
(C) shows up to the third interlayer insulating film forming step.

[Explanation of symbols]

Reference Signs List 10: substrate, 11a: source diffusion layer, 11b: drain diffusion layer, 21: first interlayer insulating film, 22: second interlayer insulating film, 23: third interlayer insulating film, 31: word line (gate electrode), 32 , 33: capacitor contact, 34: first
Ferroelectric capacitor, 34a: upper electrode, 34b: ferroelectric film, 34c: lower electrode, 35: second ferroelectric capacitor, 35a: upper electrode, 35b: ferroelectric film, 35c
... lower electrode, 36, 37 ... plate line, 38 ... bit contact, 39 ... bit line

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical indication location H01L 27/108 H01L 29/78 371 21/8242 G11C 11/34 352A 21/8247 29/788 29 / 792 // G11C 14/00

Claims (2)

[Claims] 1. A ferroelectric capacitor having a ferroelectric substance between two electrodes and storing binary data according to the direction of polarization of the ferroelectric substance in accordance with a voltage applied to both electrodes, and the ferroelectric substance. A semiconductor memory device having a memory cell composed of a switching field-effect transistor connected to a capacitor, comprising two or more ferroelectric capacitors stacked on each other with an insulating layer interposed therebetween. A semiconductor memory device wherein body capacitors have overlapping portions. 2. The semiconductor memory device according to claim 1, wherein adjacent transistors are connected to ferroelectric capacitors of different layers.