CN114974895A - MLCC and SLC-based multilayer ceramic binary capacitor and capacitor adjusting method - Google Patents
MLCC and SLC-based multilayer ceramic binary capacitor and capacitor adjusting method Download PDFInfo
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- H—ELECTRICITY
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- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
- H01G5/00—Capacitors in which the capacitance is varied by mechanical means, e.g. by turning a shaft; Processes of their manufacture
- H01G5/04—Capacitors in which the capacitance is varied by mechanical means, e.g. by turning a shaft; Processes of their manufacture using variation of effective area of electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
- H01G5/00—Capacitors in which the capacitance is varied by mechanical means, e.g. by turning a shaft; Processes of their manufacture
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
- H01G5/00—Capacitors in which the capacitance is varied by mechanical means, e.g. by turning a shaft; Processes of their manufacture
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
- H01G5/00—Capacitors in which the capacitance is varied by mechanical means, e.g. by turning a shaft; Processes of their manufacture
- H01G5/16—Capacitors in which the capacitance is varied by mechanical means, e.g. by turning a shaft; Processes of their manufacture using variation of distance between electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
- H01G5/00—Capacitors in which the capacitance is varied by mechanical means, e.g. by turning a shaft; Processes of their manufacture
- H01G5/38—Multiple capacitors, e.g. ganged
Abstract
A multilayer ceramic binary capacitor based on MLCC and SLC and a capacitance adjusting method belong to the field of binary capacitor design. The invention aims to solve the problems that the existing MLCC has single and unadjustable capacitance value, the existing binary capacitor has small capacitance value, few types of capacitor combinations, difficult capacitance value adjustment and lower voltage resistance. The multilayer ceramic binary capacitor is laminated in a surface layer green ceramic tape-capacitor part-surface layer green ceramic tape mode, and the capacitor part is formed by overlapping a dielectric layer printed with a plurality of electrodes and a dielectric layer printed with a grounding flat plate from top to bottom; one or more electrode groups are formed by a row of electrodes corresponding to the upper and lower positions of the multilayer ceramic binary capacitor. The capacitance adjusting method comprises the following steps: and the capacitance value is changed by changing and connecting different electrode groups. The invention is used for multilayer ceramic binary capacitance and capacitance regulation.
Description
Technical Field
The invention belongs to the field of binary capacitor design.
Background
The multilayer Ceramic capacitor (MLCC) is a multilayer laminated structure, and is a parallel body formed by combining a plurality of simple parallel plate Capacitors, Ceramic dielectric films printed with electrodes (inner electrodes) are laminated in a staggered mode, a Ceramic chip is formed by one-time high-temperature sintering, and metal layers (outer electrodes) are sealed at two ends of the chip, so that a structural body similar to a monolithic body is formed, and the monolithic capacitor is also called as the monolithic capacitor. The structure comprises three main components: ceramic dielectric (porcelain body), metal internal electrode and metal terminal electrode.
The Single-layer ceramic capacitor (SLC for short) has the advantages of small size, thin thickness, low equivalent series resistance, low loss and the like, is suitable for frequencies up to 100MHz-100GHz, and has wide application prospect in high-frequency, microwave, small-sized and miniaturized occasions. The single-layer ceramic capacitor is widely applied to microwave communication lines, microwave power amplifiers, modules (Bluetooth modules, external elements of integrated circuits, hybrid integrated circuit modules, mobile phone circuit modules and radio microwave communication modules), oscillating circuits, timing delay circuits, coupling circuits, balanced filter circuits, high-frequency noise suppression circuits, radio frequency bypasses and microwave integrated circuits, and is a military and civil high-reliability product.
Single layer ceramic capacitors are classified according to the surface electrode pattern structure, and there are several common types: (1) general type: the capacitor is mainly small in size, large in capacitance and excellent in microwave performance; the weldability is good; for the surface edge-retaining type single-layer capacitor, the short circuit caused by glue overflow is prevented, the design also reduces the damage caused by tweezers, and the operation of an automatic machine is facilitated. The method is mainly applied to microwave integrated circuits and has the functions of isolating direct current, bypassing a source, matching impedance and the like. (2) Two-electrode type chip capacitor: the capacitor of the type has unique structure and good performance consistency; the surface mounting can be carried out, the gold wire bonding process is omitted, the large-scale production is facilitated, and the production efficiency is improved. (3) Array type chip capacitor: this type of capacitor is simple to mount, can be integrated in an IC package to reduce lead length, improve performance, and can reduce the cost of the capacitor as well as the mounting cost. The capacitor is mainly used for a monolithic microwave integrated circuit, a decoupling circuit and a radio frequency bypass. (4) Binary multi-electrode type chip capacitor: this type of capacitor has a small geometry and is suitable for microwave circuits; the capacitance value of the capacitor array layout shows certain regular change, which is convenient for accurate debugging and is beneficial to circuit matching and adjustment. The method is mainly applied to matching networks and provides convenient circuit adjustability. The structure is shown in fig. 1.
The traditional binary multi-electrode chip is of a single-layer ceramic structure, and has smaller size and more capacitance combination modes compared with a single-electrode, double-electrode and array chip, but due to the single-layer structure and the limitation of volume, the capacitance value of the chip is small, the capacitance combination types are few, the capacitance value is difficult to adjust, the working voltage is low, certain high-power conditions are easy to break down, and certain fields requiring high density, miniaturization, high frequency and low loss are difficult to meet.
Disclosure of Invention
The invention aims to solve the problems that the capacitance value of the conventional MLCC is single and unadjustable, the capacitance value of the conventional binary capacitor is small, the combination types of capacitors are few, the capacitance value is difficult to adjust, and the withstand voltage is low, and further provides a multilayer ceramic binary capacitor based on the MLCC and the SLC and a capacitor adjusting method.
A multilayer ceramic binary capacitor based on MLCC and SLC is laminated in a mode of a surface layer green ceramic tape, a capacitor part and a surface layer green ceramic tape, wherein the capacitor part is formed by overlapping a dielectric layer printed with a plurality of electrodes and a dielectric layer printed with a grounding flat plate from top to bottom, and the number of the dielectric layers printed with the plurality of electrodes in the capacitor part is 2-80;
in the thickness direction of the multilayer ceramic binary capacitor, a row of electrodes corresponding to the upper and lower positions form one or more electrode groups, the electrode area of each layer in the same electrode group is the same as the distance between the electrode and an adjacent ground plate, and one or more of the electrode area of a single layer in different electrode groups, the distance between the electrode and the adjacent ground plate and the number of electrode layers are different.
A capacitance adjusting method of a multilayer ceramic binary capacitor based on MLCC and SLC is carried out according to the following steps:
in the multilayer ceramic binary capacitor based on the MLCC and the SLC, one or more of the area of a single-layer electrode in different electrode groups, the distance between the electrode and an adjacent ground plate and the number of the electrode layers are different, and the capacitance value is changed by changing the connection of different electrode groups.
The beneficial effects of the invention are:
1. the invention provides a brand new binary capacitor, which can achieve a larger capacitance value under the condition of the same area of a single-layer electrode by combining the characteristics of an MLCC (multilayer ceramic capacitor) and a single-layer binary multi-electrode type chip capacitor, improves the comprehensive electrical property of the binary capacitor, reduces the volume of a device, and is suitable for various fields with high precision and high performance requirements.
2. The binary capacitor provided by the invention has more capacitor combinations. Compared with the existing single-layer binary multi-electrode chip capacitor, the capacitor is adjusted by accessing the electrodes with different areas, the capacitor can be adjusted by accessing the electrode groups with different single-layer electrode areas, different electrode and adjacent horizontal plate distances and different electrode layer numbers, the capacitor can be adjusted by mutually combining the electrode groups in various modes, the combination types are various, and the use requirements under different conditions can be met.
3. The structure provided by the invention can be processed and manufactured by a plurality of processing modes, including: LTCC, HTCC, PCB and the like can be flexibly combined according to use requirements, equipment conditions and cost factors, mass production can be realized, and use cost is reduced.
4. The structure provided by the invention has the advantages of large capacity, multiple capacitor combination modes and convenience in adjustment, and is particularly suitable for the high-precision field of multi-frequency point quick adjustment such as frequency hopping communication.
5. The structure provided by the invention has the advantages of multilayer superposition, higher pressure resistance and better reliability.
Drawings
Fig. 1 is a schematic structural view of a conventional single-layer binary multi-electrode type chip capacitor, in which 1 is a surface electrode, 2 is a dielectric layer, and 3 is a ground plate;
FIG. 2 is a schematic structural diagram of a MLCC and SLC based multi-layer ceramic binary capacitor and a test substrate according to an embodiment, where 1 is the MLCC and SLC based multi-layer ceramic binary capacitor, and 2 is the test substrate;
FIG. 3 is a schematic diagram of the overall structure of a MLCC and SLC based multilayer ceramic binary capacitor according to one embodiment, where 1, 2, 3, 4 and 5 are electrode groups, and 6 is a ground plate;
FIG. 4 is a side view of an MLCC and SLC based multilayer ceramic binary capacitor according to one embodiment, with electrode sets 1 and 2, ground plane 6, and dielectric layer 7;
fig. 5 is a schematic structural diagram of an embodiment in which capacitance is changed by accessing electrode groups having different electrode areas, where 1 and 2 are electrode groups;
fig. 6 is a schematic structural diagram of an embodiment of ten electrodes with different electrode layers to change capacitance, where 4 and 5 are electrode groups;
fig. 7 is a schematic diagram of a structure of an embodiment in which capacitance is changed by accessing an electrode group having a different distance between the electrode and an adjacent ground plate, and fig. 3, 4 and 5 are electrode groups;
FIG. 8 is a schematic diagram of a multi-layer ceramic binary capacitor and test substrate based on MLCC and SLC according to an embodiment;
fig. 9 is a schematic diagram illustrating an overall structure of a multi-layer ceramic binary capacitor based on MLCC and SLC, where fig. 1, 2, 3, and 4 are electrode sets.
Detailed Description
The first specific implementation way is as follows: specifically, referring to fig. 2 to 4, in the multilayer ceramic binary capacitor based on MLCC and SLC according to the present embodiment, the multilayer ceramic binary capacitor is stacked in a manner of surface layer green ceramic tape-capacitor portion-surface layer green ceramic tape, the capacitor portion is formed by overlapping a dielectric layer printed with a plurality of electrodes and a dielectric layer printed with a ground plane from top to bottom, and the number of layers of the dielectric layer printed with the plurality of electrodes in the capacitor portion is 2 to 80;
in the thickness direction of the multilayer ceramic binary capacitor, a row of electrodes corresponding to the upper and lower positions form one or more electrode groups, the electrode area of each layer in the same electrode group is the same as the distance between the electrode and an adjacent ground plate, and one or more of the electrode area of a single layer in different electrode groups, the distance between the electrode and the adjacent ground plate and the number of electrode layers are different.
The specific implementation mode has the advantages of large capacitance value, multiple capacitance combination modes, simple and convenient capacitance value adjustment and capability of being combined with various manufacturing processes.
In fig. 3, the structures 1, 2, 3, 4 and 5 are used for forming a plurality of plate capacitors in parallel through a laminated structure, so that the capacitance value of the capacitor is fully improved when the electrode area is constant, and the plate capacitors can be combined randomly to realize a binary capacitor function; the structure 6 is used for grounding, so that each layer of metal flat plate can form a flat capacitor, and the capacitance value is improved.
The beneficial effects of the embodiment are as follows:
1. the embodiment provides a brand-new binary capacitor, and by combining the characteristics of the MLCC and a single-layer binary multi-electrode chip capacitor, a single-layer electrode can reach a larger capacitance value under the condition of the same area, the comprehensive electrical property of the binary capacitor is improved, the volume of a device is reduced, and the capacitor is suitable for various fields with high precision and high performance requirements.
2. The binary capacitor proposed in this embodiment has more capacitor combinations. Compared with the existing single-layer binary multi-electrode chip capacitor, the capacitor is adjusted by accessing the electrodes with different areas, the capacitor can be adjusted by accessing the electrode groups with different single-layer electrode areas, different electrode and adjacent horizontal plate distances and different electrode layer numbers, the capacitor can be adjusted by mutually combining the electrode groups in various modes, the combination types are various, and the use requirements under different conditions can be met.
3. The structure that this embodiment provided can be processed the preparation through multiple processing mode, includes: LTCC, HTCC, PCB and the like can be flexibly combined according to use requirements, equipment conditions and cost factors, mass production can be realized, and use cost is reduced.
4. The structure provided by the embodiment has the advantages of large capacity, multiple capacitor combination modes and convenience in adjustment, and is particularly suitable for the high-precision field of multi-frequency point quick adjustment such as frequency hopping communication.
5. The structure that this embodiment provided, multilayer stack, withstand voltage is higher, has better reliability.
The second embodiment is as follows: the first difference between the present embodiment and the specific embodiment is: the surface layer raw ceramic belt and the medium layer are made of ceramic medium materials; the dielectric constant of the ceramic dielectric material is 2-20000. The rest is the same as the first embodiment.
The third concrete implementation mode: this embodiment is different from the first or second embodiment in that: the upper surface area of the multilayer ceramic binary capacitor based on the MLCC and the SLC is 100 mu m 2 ～100cm 2 . The other is the same as in the first or second embodiment.
The fourth concrete implementation mode: the difference between this embodiment mode and one of the first to third embodiment modes is: the layout mode of the electrodes in the dielectric layer printed with the plurality of electrodes is the same as that of the single-layer binary multi-electrode chip capacitor. The others are the same as the first to third embodiments.
The fifth concrete implementation mode is as follows: the difference between this embodiment and one of the first to fourth embodiments is: the dielectric layer is provided with a through hole, and the diameter of the through hole is 10-500 mu m; the electrode group is connected by filling holes with conductive metal slurry. The rest is the same as the first to fifth embodiments.
The sixth specific implementation mode: the difference between this embodiment and one of the first to fifth embodiments is: one or more layers of dielectric layers printed with grounding flat plates are arranged between the adjacent dielectric layers printed with a plurality of electrodes. The rest is the same as the first to fifth embodiments.
The seventh embodiment: the difference between this embodiment and one of the first to sixth embodiments is: the distance between the electrode and the adjacent flat plate is 10-3000 μm; the thickness of the electrode is 1-1000 μm; the thickness of the grounding flat plate is 1-1000 μm. The others are the same as the first to sixth embodiments.
The specific implementation mode is eight: the present embodiment differs from one of the first to seventh embodiments in that: the multilayer ceramic binary capacitor based on the MLCC and the SLC is obtained by an LTCC, HTCC or PCB processing method. The rest is the same as the first to seventh embodiments.
The LTCC \ HTCC technology is adopted in the specific implementation mode, the volume can be compressed to be small, and the single-layer binary volume required to be used is far larger than that of the capacitor in the specific implementation mode to achieve the same capacitance value and capacitance combination quantity.
The LTCC processing method comprises the following steps: selecting a ceramic dielectric material with a dielectric constant of 2-20000, wherein the sintering temperature of the ceramic material is lower than 900 ℃, and the expansion coefficient of the ceramic material is close to that of the used metal material. Because of the low sintering temperature, the metal material can be selected from silver and copper metals with high conductivity and lower melting point. The processing process comprises the steps of firstly carrying out ceramic powder tape casting and slide glass to prepare a raw ceramic tape; then punching, filling and printing electrodes on the green ceramic tape; and finally, laminating, statically pressing and sintering the printed capacitor part and the unprinted surface layer green ceramic tape together to prepare the multilayer ceramic binary capacitor.
The HTCC processing method comprises the following steps: the HTCC needs to carry out glue removal treatment at the temperature of below 900 ℃ and then co-fire the laminated substrates into a whole in a higher high temperature environment of 1500-1600 ℃, and the ceramic material is Al 2 O 3 AlN and the like. Because of the high sintering temperature, only metals or noble metals with high melting points but poor conductivity, such as tungsten, molybdenum, manganese, etc., can be selected. The production process flow is similar to that of LTCC.
The PCB processing method comprises the following steps: the substrate material adopts a copper clad laminate, and the metal-based heat dissipation plate comprises an aluminum substrate, a copper substrate and an iron substrate. The PCB comprises 1-64 layers, the minimum board thickness can reach 0.6mm, and the processing flow comprises cutting, grinding, pasting, exposing, developing, etching/electroplating, stripping, browning, laminating, drilling, copper plate plating, outer dry film, outer pattern electroplating, solder resisting, character silk-screen printing, surface treatment, molding, electrical testing and final inspection.
The specific implementation method nine: the embodiment of the invention relates to a capacitance adjusting method of a multilayer ceramic binary capacitor based on MLCC and SLC, which is carried out according to the following steps:
in the multilayer ceramic binary capacitor based on the MLCC and the SLC, one or more of the area of a single-layer electrode in different electrode groups, the distance between the electrode and an adjacent ground plate and the number of the electrode layers are different, and the capacitance value is changed by changing the connection of different electrode groups.
The detailed implementation mode is ten: as described in detail with reference to fig. 5 to 7, the present embodiment differs from the ninth embodiment in that: when the spacing between electrodes in different electrode groups and adjacent ground plane is the same as the number of electrode layers in a multilayer ceramic binary capacitor based on MLCC and SLC, and the areas of single-layer electrodes in different electrode groups are different, the area of the electrodes is controlled to change the capacitance value by changing and connecting different electrode groups;
when the area of a single-layer electrode in different electrode groups is the same as the number of electrode layers and the distance between the electrode in different electrode groups and an adjacent ground plate is different in the multilayer ceramic binary capacitor based on the MLCC and the SLC, the capacitance value is changed by changing the distance between the control electrode and the adjacent ground plate by changing and connecting different electrode groups;
in the multilayer ceramic binary capacitor based on the MLCC and the SLC, the area of a single-layer electrode in different electrode groups and the distance between the electrode and an adjacent horizontal plate are the same, and the number of electrode layers in different electrode groups is different, the number of electrode layers is controlled to change the capacitance value by changing and connecting different electrode groups. The rest is the same as the embodiment nine.
The different layers can not be accessed by selecting electrodes independently, but the capacitance value of the capacitor can be adjusted rapidly by controlling the access conditions of different electrode groups, and the capacitance value can be controlled accurately according to the requirements. The specific implementation manner is as follows:
(1) the capacitance value is changed by changing the area of the single-layer electrode in the access electrode group. In different electrode groups, under the condition that the distance between an electrode and an adjacent flat plate (the distance between the electrode and the grounding flat plate, namely the thickness of a green ceramic band) and the number of electrode layers are the same, the size of the capacitance value of the whole binary capacitor can be changed by accessing the electrode groups with different single-layer electrode areas, which is similar to the method for adjusting the capacitance value by the traditional single-layer binary capacitor. Fig. 5 is a schematic diagram showing a structure of a capacitance value of an electrode assembly according to an embodiment, in which electrode assemblies having different electrode areas are connected, and fig. 1 and 2 are electrode assemblies; the electrode layer number and the electrode and adjacent flat plate spacing of the 1 and 2 electrode groups are completely the same, but the single-layer electrode area in the 1 and 2 electrode groups is different (plan view), so the capacitance value of 1 and 2 is different, and when 1 or 2 is selected, the capacitance value of the whole capacitor can be changed.
(2) The capacitance value is changed by controlling the number of electrode layers. In different electrode groups, under the condition that the space between the electrode and the adjacent horizontal plate and the area of a single-layer electrode are the same, in the thickness direction of the dielectric layer, one row of electrodes are arranged into two or more groups of electrode groups with different electrode layers, and the size of the binary capacitance value can be controlled by selecting the electrode groups with different electrode layers. As shown in fig. 6, fig. 6 is a schematic structural diagram of an embodiment in which capacitance values are changed by accessing electrode groups having different electrode layer numbers, and fig. 4 and 5 are electrode groups; the array of electrodes corresponding to the upper and lower positions in the thickness direction of the capacitor is divided into 2 electrode groups with different electrode layers, so that the electrode layers are changed under the condition that the space between the electrodes and the adjacent horizontal plates and the area of a single-layer electrode are the same; as can be seen, the same electrode set is connected by filling the holes with conductive paste, and the conductive paste is not disposed between the different electrode sets 4 and 5.
(3) The capacitance value is changed by controlling the distance between the electrode and the adjacent flat plate. In different electrode groups, under the condition that the area of a single-layer electrode and the number of electrode layers are the same, the size of a binary capacitance value can be adjusted by adjusting the distance between the electrode and an adjacent ground plate, as shown in fig. 7, fig. 7 is a schematic structural diagram of a specific embodiment that the capacitance value is changed by accessing an electrode group with a different distance between the electrode and the adjacent ground plate, and fig. 3, 4 and 5 are electrode groups; the array of electrodes corresponding to the upper and lower positions in the thickness direction of the capacitor is divided into 2 electrode groups 4 and 5 with different layers, silver paste is not arranged between the different electrode groups 4 and 5, the number of the electrodes in the electrode group 4 is 2, the number of the layers of the electrode group 3 is the same as that of the electrode group 4, namely, the area of a single-layer electrode is the same as that of the electrode layer, the distance between the electrode in the electrode group 3 and the electrode in the electrode group 4 and the adjacent ground plane is different, and 2 dielectric layers printed with ground planes are arranged between the dielectric layers printed with the electrodes in the electrode group 3.
The three methods for adjusting the capacitance value of the capacitor can be used independently or combined with one another, and the combination types are very many, so that different use requirements can be met.
The following examples were used to demonstrate the beneficial effects of the present invention:
the first embodiment is described in detail with reference to fig. 8 and 9:
the multilayer ceramic binary capacitor is laminated in a surface layer green ceramic tape-capacitor part-surface layer green ceramic tape mode, the capacitor part is formed by overlapping a dielectric layer printed with 3 electrodes and a dielectric layer printed with a grounding flat plate from top to bottom, and the number of the dielectric layers printed with 3 electrodes in the capacitor part is 6; the number of dielectric layers printed with the grounding flat plate in the capacitor part is 6;
in the thickness direction of the multilayer ceramic binary capacitor, a row of electrodes corresponding to the upper and lower positions form an electrode group 1, a row of electrodes form an electrode group 2, a row of electrodes form electrode groups 3 and 4, the electrode area of each layer in the same electrode group and the distance between the electrodes and the adjacent horizontal plates are the same, and related parameters of the electrode group 1, the electrode group 2 and the electrode groups 3 and 4 are detailed in table 1.
The surface layer raw porcelain belt and the medium layer are made of K14 ceramic materials.
The dielectric constant of the ceramic dielectric material is 13.5.
The size of the multilayer ceramic binary capacitor based on the MLCC and the SLC is 4mm multiplied by 1.44 mm.
The layout mode of the electrodes in the dielectric layer printed with 3 electrodes is the same as that of a DCMS100J40 type single-layer binary multi-electrode chip capacitor.
The medium layer is provided with a through hole, and the diameter of the through hole is 100 micrometers; the electrode group is connected by filling holes with silver paste.
The thickness of the electrode is 20 μm; the thickness of the grounding flat plate is 20 μm;
the electrode is made of metal silver; the grounding flat plate is made of metal silver.
The multilayer ceramic binary capacitor based on the MLCC and the SLC is obtained by an LTCC processing method, and the specific process is as follows:
firstly, casting: carrying out tape casting on K14 ceramic powder to obtain a raw ceramic film belt, and winding the raw ceramic film belt for later use;
secondly, carrying a slide: cutting the green ceramic film belt from a roll type to a single sheet type according to the size requirement to obtain a cut green ceramic belt;
thirdly, punching, filling holes and printing: punching holes at corresponding positions on the cut raw porcelain strips, filling holes with silver paste on a screen printer and printing electrodes to obtain a dielectric layer printed with 3 electrodes, or filling holes with silver paste on the screen printer and printing a grounding flat plate to obtain a dielectric layer printed with the grounding flat plate;
fourthly, laminating: taking the cut raw porcelain tape as a surface raw porcelain tape, aligning, fixing and laminating the medium layer printed with 3 electrodes, the medium layer printed with the grounding flat plate and the surface raw porcelain tape to obtain a laminated raw porcelain tape;
fifth, static pressure: packaging and evacuating the laminated green porcelain tape, fixing the green porcelain tape in a reinforced plastic bag, and then putting the green porcelain tape in hot water for pressure equalization to obtain a green porcelain tape subjected to static pressure;
sixthly, cutting and co-firing: and cutting the green ceramic tape subjected to static pressure into different modules according to design requirements, and sintering in a sintering furnace to finally obtain the MLCC and SLC-based multilayer ceramic binary capacitor.
Capacitance value measurement and regulation scheme analysis: the same material, the same electrode area, the same electrode-to-ground plate distance DCMS100J40 single layer binary multi-electrode chip capacitor was set as group 1, example one was set as group 2, and the comparative results of the test are shown in the following table:
the data in the table show that, under the same single-layer electrode plate area condition, the embodiment has larger capacitance value, more capacitance combination modes, wider capacitance regulation range, better voltage resistance and better comprehensive performance compared with the existing single-layer binary multi-electrode chip capacitor, and can be suitable for certain fields requiring high density, miniaturization, high frequency and low loss.
Claims (10)
1. A multilayer ceramic binary capacitor based on MLCC and SLC is characterized in that the multilayer ceramic binary capacitor is laminated in a surface layer green ceramic tape-capacitor part-surface layer green ceramic tape mode, the capacitor part is formed by overlapping a dielectric layer printed with a plurality of electrodes and a dielectric layer printed with a grounding flat plate from top to bottom, and the number of the dielectric layers printed with the plurality of electrodes in the capacitor part is 2-80;
in the thickness direction of the multilayer ceramic binary capacitor, a row of electrodes corresponding to the upper and lower positions form one or more electrode groups, the electrode area of each layer in the same electrode group is the same as the distance between the electrode and an adjacent ground plate, and one or more of the electrode area of a single layer in different electrode groups, the distance between the electrode and the adjacent ground plate and the number of electrode layers are different.
2. The MLCC and SLC based multilayer ceramic binary capacitor according to claim 1, wherein said surface layer green ceramic tape and dielectric layer are made of ceramic dielectric material; the dielectric constant of the ceramic dielectric material is 2-20000.
3. The MLCC and SL-based device according to claim 1The multilayer ceramic binary capacitor of C is characterized in that the upper surface area of the multilayer ceramic binary capacitor based on MLCC and SLC is 100 mu m 2 ～100cm 2 。
4. The MLCC and SLC multilayer ceramic binary capacitor according to claim 1, wherein said dielectric layer printed with multiple electrodes has the same layout as single layer binary multiple electrode chip capacitor.
5. The MLCC and SLC based multilayer ceramic binary capacitor according to claim 1, wherein said dielectric layer has through holes with a diameter of 10-500 μm; the electrode group is connected by filling holes with conductive metal slurry.
6. The MLCC and SLC multilayer ceramic binary capacitor as claimed in claim 1, wherein one or more dielectric layers printed with ground plane are disposed between adjacent dielectric layers printed with multiple electrodes.
7. The MLCC and SLC based multilayer ceramic binary capacitor of claim 1, wherein said electrodes are spaced from adjacent ground plane by 10 μm to 3000 μm; the thickness of the electrode is 1-1000 μm; the thickness of the grounding flat plate is 1-1000 μm.
8. The MLCC and SLC based multilayer ceramic binary capacitor of claim 1, wherein the MLCC and SLC based multilayer ceramic binary capacitor is obtained by LTCC, HTCC or PCB processing.
9. The method for adjusting capacitance of MLCC and SLC based multilayer ceramic binary capacitor as claimed in claim 1, which is performed by the following steps:
in the multilayer ceramic binary capacitor based on the MLCC and the SLC, one or more of the area of a single-layer electrode in different electrode groups, the distance between the electrode and an adjacent ground plate and the number of the electrode layers are different, and the capacitance value is changed by changing the connection of different electrode groups.
10. The capacitance adjusting method of the MLCC-SLC multilayer ceramic binary capacitor as claimed in claim 9, wherein when the MLCC-SLC multilayer ceramic binary capacitor has the same electrode-to-adjacent ground plate spacing and electrode layer number, and the area of the single layer electrode in different electrode groups is different, the capacitance value is changed by changing the electrode area to be connected to different electrode groups;
when the area of a single-layer electrode in different electrode groups is the same as the number of electrode layers and the distance between the electrode in different electrode groups and an adjacent ground plate is different in the multilayer ceramic binary capacitor based on the MLCC and the SLC, the capacitance value is changed by changing the distance between the control electrode and the adjacent ground plate by changing and connecting different electrode groups;
in the multilayer ceramic binary capacitor based on the MLCC and the SLC, the area of a single-layer electrode in different electrode groups and the distance between the electrode and an adjacent horizontal plate are the same, and the number of electrode layers in different electrode groups is different, the number of electrode layers is controlled to change the capacitance value by changing and connecting different electrode groups.
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