JPS5814072B2 - Semiconductor integrated circuit device and its manufacturing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device having a configuration including a MIS field effect transistor and a resistive element connected in series with the MIS field effect transistor, and a method for manufacturing the same.

Conventionally, semiconductor integrated circuit devices having configurations as shown in FIGS. 1A and 1B have been proposed.

That is, semiconductor regions 3 and 4 are formed in, for example, a P-type semiconductor substrate 1 made of, for example, silicon, into which an N-type impurity is introduced from the main surface 2 side.

Further, a relatively thin insulating layer 5 is provided on the main surface 2 of the semiconductor substrate 1.
and a relatively thick insulating layer 6 surrounding the insulating layer 5.

On the other hand, a window 7 in the insulating layer 5 allows the semiconductor region 3 to be exposed to the outside.
is formed.

Further, a polycrystalline semiconductor layer 8 made of, for example, polycrystalline silicon is formed on the insulating layer 5, connected to the semiconductor region 3 through the window 7, and doped with an N-type impurity and extending onto the insulating layer 6. has been done.

In this case, the polycrystalline semiconductor layer 8 has a configuration in which a high-resistance polycrystalline semiconductor layer portion 8a is formed in an extended manner on the insulating layer 6. The crystalline semiconductor layer 8 has a structure consisting of a high-resistance polycrystalline semiconductor layer portion 8a and low-resistance polycrystalline semiconductor layer portions 8b and 8c sandwiching it, and the low-resistance polycrystalline semiconductor layer portion 8b
is connected to the semiconductor region 3.

Further, on the insulating layer 5, a polycrystalline semiconductor layer 10, which faces the region 9 between the semiconductor regions 3 and 4 of the semiconductor substrate 1 and into which an N-type impurity is introduced, extends across the insulating layer 5. It is formed in such a manner that it extends above 6.

Further, polycrystalline semiconductor layers 8 and 10 are formed on the insulating layers 5 and 6.
An insulating layer 11 is formed to cover and extend, and a window 12 is formed in the insulating layer 11 so that the low resistance polycrystalline semiconductor layer portion 8c of the polycrystalline semiconductor layer 8 is exposed to the outside.

Further, a window 13 is formed in the insulating layers 5 and 11 so that the semiconductor region 4 is exposed to the outside.

Further, conductive layers 14 and 1 are formed on the insulating layer 11 and are connected to the low resistance polycrystalline semiconductor layer portion 8c of the polycrystalline semiconductor layer 8 and the semiconductor region 4 through the windows 12 and 13, respectively.
5 is formed.

Furthermore, as a method for manufacturing the above-mentioned semiconductor integrated circuit device, the method described below with reference to FIGS. 2A to 2G has conventionally been proposed.

That is, a P-type semiconductor substrate 1 as shown in FIG. 2A is prepared in advance, and then, for example, by thermal oxidation treatment of its main surface 2, a p-type semiconductor substrate 1 as shown in FIG. 2B is prepared. , a relatively thin insulating layer 5 and a relatively thick insulating layer 6 surrounding the insulating layer 5 are formed.

Next, by etching the insulating layer 5, the second
As shown in FIG. C, a window 7 is formed in the insulating layer 5 so that the substrate 1 can be exposed to the outside.

Next, as shown in FIG. 2D, a layer is formed on the insulating layer 5 by, for example, a CVD method, and is connected to a region of the semiconductor substrate 1 facing outside through the window 7 and extends onto the insulating layer 6. A polycrystalline semiconductor layer 28 made of, for example, polycrystalline silicon and having a relatively high resistance is formed, and a polycrystalline semiconductor layer 30 similar to the polycrystalline semiconductor layer 28 is formed across the insulating layer 5.

Next, polycrystalline semiconductor layers 28 and 30 and semiconductor substrate 1
N by thermal diffusion of N-type impurities, ion implantation, etc.
By introducing type impurities, as shown in Fig. 2E,
At least only the layer portion facing the window 7 and the layer portion on the opposite side of the polycrystalline semiconductor layer 28 are formed as low-resistance polycrystalline semiconductor layer portions 8b and 8c doped with N-type impurities. The crystalline semiconductor layer 28 is formed into a low resistance polycrystalline semiconductor layer section 8.
A polycrystalline semiconductor layer 8 is formed of layers b and 8c and a high-resistance polycrystalline semiconductor layer portion 8a made up of other layer portions, and the polycrystalline semiconductor layer 30 is a polycrystalline semiconductor layer doped with N-type impurities. 10, and the semiconductor substrate 1
When viewed from the region 9 of the polycrystalline semiconductor layer 10 on the main surface 2 side, the region below the polycrystalline semiconductor layer 8 is connected to and extended to the low resistance polycrystalline semiconductor layer portion 8b of the polycrystalline semiconductor layer 8. In addition to forming a semiconductor region 3 into which an N-type impurity is introduced, on the main surface 2 side of the semiconductor substrate 1,
Viewed from region 9, in the region opposite to the semiconductor region 3 side,
Similarly, a semiconductor region 4 doped with N-type impurities is formed.

Next, on the insulating layers 5 and 6, for example, by CVD method,
As shown in FIG. 2F, an insulating layer 11 covering polycrystalline semiconductor layers 8 and 10 is formed.

Next, by selective etching treatment, as shown in FIG. 2G, a window 12 is formed in the insulating layer 11 through which the low resistance polycrystalline semiconductor layer portion 8c of the polycrystalline semiconductor layer 8 is exposed to the outside. A window 13 is formed in the insulating layers 11 and 5 to expose the semiconductor region 4 to the outside. Next, as shown in FIGS.
A conductive layer 1 connected and extended to the low resistance polycrystalline semiconductor layer portion 8c of the polycrystalline semiconductor layer 8 and the semiconductor region 4, respectively.
4 and 15 are formed.

In this way, the desired semiconductor integrated circuit device is obtained.

As described above, the conventionally proposed semiconductor integrated circuit device and its manufacturing method have been clarified.

According to the configuration of the conventional semiconductor integrated circuit device described above, each of the semiconductor regions 3 and 4 is used as a drain (or source).
MIS field effect transistor M in which a region and a source (or drain) region, a region 9 as a channel region, a polycrystalline semiconductor layer 10 as a gate electrode or wiring layer, and a region under the polycrystalline semiconductor layer 10 of an insulating layer 5 as a gate insulating layer. The high-resistance polycrystalline semiconductor layer portion 8a of the polycrystalline semiconductor layer 8 is connected in series with the MIS field effect transistor M as a resistor element body, and the low-resistance polycrystalline semiconductor layer portions 8b and 8c are used as wiring layer portions of the resistor element body. The electrical circuit that constitutes the resistive element R has the configuration shown in FIG.

Therefore, the conventional semiconductor integrated circuit device described above cannot be applied when configuring a static MI3 random access memory circuit using the resistive element R as a load, an MIS logic circuit using a resistive load type inverter, etc. It's something you get.

Furthermore, in the case of the conventional semiconductor integrated circuit device described above, since the resistive element body and the wiring layer portion that constitute the resistive element R are composed of one polycrystalline semiconductor layer 8, the semiconductor integrated circuit device The device is characterized by a simple configuration.

Further, for this reason, the above-described conventional method for manufacturing a semiconductor integrated circuit device is characterized in that the intended semiconductor integrated circuit device can be manufactured relatively easily.

However, in the case of the conventional semiconductor integrated circuit device and its manufacturing method described above, only the low-resistance polycrystalline semiconductor layer portion 8b of the polycrystalline semiconductor layer 8, which constitutes the wiring layer portion of the resistance element R, has a window. 7 to the semiconductor region 3 and thus:
Since the high-resistance polycrystalline semiconductor layer portion 8a of the polycrystalline semiconductor layer 8, which constitutes the resistive element body of the resistive element R, is formed on the insulating layer 6, the resistive element R The area occupied by an integrated circuit device increases, and the stray capacitance of a semiconductor integrated circuit device increases accordingly.Therefore, it is difficult to increase the density and speed of a semiconductor integrated circuit device to a certain extent. had.

In addition, in the case of the conventional semiconductor integrated circuit device and its manufacturing method described above, the drain of the MIS field effect transistor M (
The drain (or source) of the MIS field effect transistor M is connected to the third
As shown by the dotted line in the figure, even if there is a request for direct output to the outside, the problem has been that the request cannot be satisfied.

Further, a semiconductor integrated circuit device having a configuration as shown in FIGS. 4A and 4B has also been proposed.

In FIGS. 4A and 4B, parts corresponding to those in FIGS. 1A and B are designated by the same reference numerals, and detailed description thereof will be omitted.

The conventional semiconductor integrated circuit device shown in FIGS. 4A and 4B has the same structure as that shown in FIGS. 1A and 1B, except for the following points. has.

That is, the polycrystalline semiconductor layer 8 is a low resistance polycrystalline semiconductor layer portion 8.
It has a structure in which a high resistance polycrystalline semiconductor layer portion 8a is laminated on a low resistance polycrystalline semiconductor layer portion 8b having a resistivity.

Further, the insulating layer 11 extends to cover the low resistance polycrystalline semiconductor layer portion 8b and the polycrystalline semiconductor layer 10.
and an insulating layer 1l extending to cover the insulating layer 11a.
Furthermore, the high-resistance polycrystalline semiconductor layer portion 8a has a structure consisting of
The conductive layer 14 is connected to the high resistance polycrystalline semiconductor layer 8a through a window 12b formed in advance in the insulating layer 1lb. have

Furthermore, as a method for manufacturing the semiconductor integrated circuit device shown in FIG.
Conventionally, although detailed explanation is omitted, as shown in FIG. 5 AB, C, D, and E, semiconductors are manufactured by sequentially performing steps similar to the steps described above in FIG. 2 A, B, C, D, and E. On board 1,
forming insulating layers 5 and 6, forming a window 7 in insulating layer 5, forming polycrystalline semiconductor layers 28 and 30 having high specific resistance;
A low resistance polycrystalline semiconductor layer portion 8b, a polycrystalline semiconductor layer 10, and semiconductor regions 3 and 4 are formed.

Next, as shown in FIG. 5F, an insulating layer 11a is formed on the insulating layers 5 and 6 so as to cover the low resistance polycrystalline semiconductor layer portion 8b and the polycrystalline semiconductor layer 10.

Next, as shown in FIG. 5G, a window 12a is formed in the insulating layer 11a to allow the low resistance polycrystalline semiconductor layer portion 8b to be exposed to the outside.

Next, as shown in FIG. 5H, a window 1 is placed on the insulating layer 11a.
A high resistance polycrystalline semiconductor layer section 8a is formed which is connected to a low resistance polycrystalline semiconductor layer section 8b through 2a.

Next, as shown in FIG.
form lb.

Next, as shown in FIG. 5J, a window 12b is formed in the insulating layer 11b to expose the high-resistance polycrystalline semiconductor layer 8a to the outside, and a semiconductor region 4 is formed in the insulating layers 5, 11a and 1lb. A window 13 facing the outside is formed.

Next, as shown in FIGS. 4A and 4B, the insulating layer 1Ib is connected and extended to the high resistance polycrystalline semiconductor layer portion 8a and the semiconductor region 4 through windows 12b and 13, respectively.

Conductive layers 14 and 15 are formed.

In this way, the desired semiconductor integrated circuit device is obtained.

As described above, other conventional semiconductor integrated circuit devices and their manufacturing methods have been clarified.

According to the configuration of such a conventional semiconductor integrated circuit device,
As in the case of the conventional semiconductor integrated circuit device shown in FIG. 1, the configuration includes an MIS field effect transistor M and a resistance element R connected in series with the MIS field effect transistor M.

Therefore, the above-described conventional semiconductor integrated circuit device shown in FIG. 1 can also be applied to the case of configuring a static MIS random access memory circuit or an MIS logic circuit in the same manner as described above in FIG.

In addition, in the case of the above-described conventional semiconductor integrated circuit device and its manufacturing method shown in FIGS. Since the semiconductor layer section 8a is stacked and formed on the low resistance polycrystalline semiconductor layer section 8b, the resistance element R is formed in a semiconductor integrated circuit device, compared to the cases of FIGS. 1 and 2. The area occupied by the semiconductor integrated circuit device is small, and the stray capacitance of the semiconductor integrated circuit device is correspondingly small. Compared to the device and its manufacturing method, it has the characteristics of being able to achieve higher density and higher speed.

However, in the case of the manufacturing method of the semiconductor integrated circuit device described above in FIG. 4 and the semiconductor integrated circuit device described above in FIG.
It is necessary to form the high-resistance polycrystalline semiconductor layer portion 8a and the low-resistance polycrystalline semiconductor layer portion 8b of the polycrystalline semiconductor layer 8 in separate steps, and also to form the insulating layers 11a and 1lb.
Similarly, it is necessary to form each layer in separate steps, and the surface of the insulating layer 11b is different from that of the high-resistance polycrystalline semiconductor layer portion 8a.
It was obtained as having a large step at the upper position, which had the disadvantage that it was difficult to form the conductive layer 13 reliably.

In addition, in the case of the conventional semiconductor integrated circuit device and its manufacturing method described above in FIGS. 4 and 5, the drain (or source) of the MIS field effect transistor M is As in the case of conventional semiconductor integrated circuit devices and their manufacturing methods, the drain (or source) of the MIS field effect transistor M is connected to the third
As shown by the dotted line in the figure, even if there is a request for direct output to the outside, the problem has been that the request cannot be satisfied.

Therefore, the present invention provides a novel MI system that does not have the above-mentioned drawbacks.
The purpose of the present invention is to propose a semiconductor integrated circuit device having a configuration comprising an S field effect transistor and a resistive element connected in series with the S field effect transistor, and a method for manufacturing the same. Dew.

First, with Figure 6 A and B. An embodiment of a semiconductor integrated circuit device according to the present invention will be described.

FIGS. 6A and BK: In FIGS. 6A and BK, corresponding parts to those in FIGS. 1A and B are designated by the same reference numerals, and detailed description thereof will be omitted.

The embodiment of the semiconductor integrated circuit device according to the present invention shown in FIGS. 6A and 6B has the structure of the conventional semiconductor integrated circuit device described above in FIGS. 1A and B except for the following points.
It has the same configuration as in Figures A and B.

That is, the high resistance polycrystalline semiconductor layer portion 8a of the polycrystalline semiconductor layer 8
and extends over the entire region of the semiconductor region 3 facing the window 7.

Next, an embodiment of the method for manufacturing a semiconductor integrated circuit device according to the present invention shown in FIGS. 6A and 6B will be described with reference to FIGS. 7A to 7H.

In FIGS. 7A to 7H, parts corresponding to those in FIGS. 2A to 2G are designated by the same reference numerals, and detailed description thereof will be omitted.

In an embodiment of the method for manufacturing a semiconductor integrated circuit device according to the present invention, as shown in FIGS. 7A, B, C, D, and E, the second
Insulating layers 5 and 6 are formed on the main surface 2 of the semiconductor substrate 1 by sequentially performing steps similar to those described above in FIGS. Window 7 facing the outside
A polycrystalline semiconductor layer 28 having a layer portion extending to the window 7 is formed on the insulating layer 5, and a polycrystalline semiconductor layer 30 is formed extending across the insulating layer 5. , an N-type impurity is introduced into the entire region of the polycrystalline semiconductor layers 28 and 30, and the semiconductor region 3 connected to the polycrystalline semiconductor layers 10 and 10 and the polycrystalline semiconductor layer 8' is formed. and,
A semiconductor region 4 connected to the polycrystalline semiconductor layer 10 is formed on the side opposite to the semiconductor region 3 when viewed from the region 9.

Next, for the polycrystalline semiconductor layer, for example, 0+
As shown in FIG. 7F, by selectively introducing a substance that reduces conductivity such as The polycrystalline semiconductor layer 8a is formed as a high-resistance polycrystalline semiconductor layer portion 8a in which a Semiconductor region 3 made up of layer portion 8a and other layer portions
The polycrystalline semiconductor layer 8 includes a low resistance polycrystalline semiconductor layer portion 8b connected to the other region of the region facing the window 7.

Next, as shown in FIG. 7G, the insulating layers 5 and 6 are extended to cover the polycrystalline semiconductor layers 8 and 10 by performing a step similar to the step described above in FIG. 2F. An insulating layer 11 is formed.

Next, as shown in FIG. 7H, a window 12 is formed in the insulating layer 11 to allow the high-resistance polycrystalline semiconductor layer portion 8a of the polycrystalline semiconductor layer 8 to be exposed to the outside, and a window 12 is formed in the insulating layer 5 and 11. A window 13 is formed that exposes the semiconductor region 4 to the outside.

Next, as shown in FIGS. 6A and 6B, on the insulating layer 11,
Conductive layers 14 and 15 are formed to connect and extend through windows 12 and 13 to high-resistance polycrystalline semiconductor layer portion 8a of polycrystalline semiconductor layer 8 and semiconductor region 4, respectively.

In this way, the desired semiconductor integrated circuit device is obtained.

The embodiments of the semiconductor integrated circuit device and method for manufacturing the same according to the present invention have been clarified above.

According to the semiconductor integrated circuit device according to the present invention shown in FIGS. 6A and 6B, although detailed explanation is omitted, as in the case of the conventional semiconductor integrated circuit device described above in FIG. , and a resistance element R connected in series with this.

Therefore, the semiconductor integrated circuit device according to the present invention shown in FIGS. 6A and 6B also includes a static MI3 random access memory circuit, an MIS
It can be applied when configuring a logic circuit.

Further, according to the semiconductor integrated circuit device according to the present invention shown in FIGS. 6 and 7, and the manufacturing method thereof, the high-resistance polycrystalline semiconductor layer 8 of the polycrystalline semiconductor layer 8 constituting the resistive element body of the resistive element R is Since the semiconductor layer portion 8a is formed connected to a part of the semiconductor region 3, the area occupied by the resistance element R in the semiconductor integrated circuit device is smaller than that of the conventional semiconductor device described above in FIGS. 1 and 2. The semiconductor integrated circuit device is sufficiently smaller than the case of the integrated circuit device and its manufacturing method, and the stray capacitance of the semiconductor integrated circuit device is correspondingly small. Compared to the conventional semiconductor integrated circuit device and its manufacturing method described above, the present invention has the characteristics of being able to achieve higher density and higher speed.

Further, in the case of the semiconductor integrated circuit device according to the present invention shown in FIGS. 6 and 7, and the manufacturing method thereof, the drain (or source) of the MIS field effect transistor M is connected to the resistive element R.
MIS
Since the drain (or source) of the field effect transistor M is directly led out to the outside as shown by the dotted line in FIG. It has the characteristic that it can also satisfy requests that are directly derived to the outside.

Furthermore, in the case of the semiconductor integrated circuit device according to the present invention shown in FIGS. 6 and 7, and the manufacturing method thereof, after forming the polycrystalline semiconductor layer 10, from the polycrystalline semiconductor layer 8',
In contrast, the polycrystalline semiconductor layer 8 forming the high-resistance polycrystalline semiconductor layer portion 8a and the low-resistance polycrystalline semiconductor layer portion 8b can be obtained simply by introducing a substance that lowers the conductivity. Therefore, the resistance element R can be easily formed.

Further, in the case of the semiconductor integrated circuit device and the manufacturing method thereof according to the present invention shown in FIGS. 6 and 7, the high resistance polycrystalline semiconductor layer portion 8a and the low resistance polycrystalline semiconductor layer portion 8b of the polycrystalline semiconductor layer 8 Since they are not superimposed on each other, the surface of the insulating layer 11 is the same as that of the insulating layer 1lb in the conventional semiconductor integrated circuit device and its manufacturing method described above in FIGS. 4 and 5. Therefore, the conductive layer 13 can be formed reliably.

Note that in the above description, the semiconductor integrated circuit device of the present invention,
For each of the embodiments and the manufacturing method thereof, only one embodiment has been shown, and various modifications and changes may be made without departing from the spirit of the present invention.

[Brief explanation of drawings]

FIGS. 1A and 1B are a schematic plan view and a cross-sectional view, respectively, showing a conventional semiconductor integrated circuit device. FIGS. 2A to 2G are schematic cross-sectional views showing successive steps in the manufacturing method of the conventional semiconductor integrated circuit device shown in FIGS. 1A and 1B. FIG. 3 is a connection diagram electrically showing the configuration of the semiconductor integrated circuit device shown in FIG. 1. 4A and 4B are a schematic plan view and a cross-sectional view, respectively, showing another conventional semiconductor integrated circuit device. 5A to 5J are schematic cross-sectional views showing sequential steps in the manufacturing method of the conventional semiconductor integrated circuit device shown in FIGS. 4A and 4B. 6A and 6B are a schematic plan view and a sectional view thereof, respectively, showing an embodiment of a semiconductor integrated circuit device according to the present invention. FIGS. 7A-H are schematic cross-sectional views showing sequential steps showing an embodiment of the manufacturing method of the embodiment of the semiconductor integrated circuit device according to the present invention shown in FIGS. 6A and 6B. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Main surface, 3, 4... Semiconductor region, 5, 6, 11... Insulating layer, 7, 12, 13... Window, 8
, 8', 10, 28, 30...polycrystalline semiconductor layer, 8a...
... High resistance polycrystalline semiconductor layer portion, ab, 8c ... Low resistance polycrystalline semiconductor layer portion, 9 ... Region, 14, 15 ... Conductive layer,
M...MIS field effect transistor, R...resistance element.

Claims (1)

[Claims] 1. A semiconductor substrate having a first conductivity type, into which an impurity is introduced from the main surface side to give a second conductivity type opposite to the first conductivity type. and a second semiconductor region are formed, a first insulating layer is formed on the main surface of the semiconductor substrate, and a first insulating layer in which the first semiconductor region is exposed to the outside. a window is formed on the first insulating layer, passing the first window through the first insulating layer;
The impurity is introduced into a high-resistance polycrystalline semiconductor layer portion connected to a part of the semiconductor region of the semiconductor region, and connected to another region of the first semiconductor region through the first window. a fifth polycrystalline semiconductor layer forming a low-resistance polycrystalline semiconductor layer portion, a fifth polycrystalline semiconductor layer facing the region between the first and second semiconductor regions, and into which the impurity is introduced; a second insulating layer extending to cover the fourth and fifth polycrystalline semiconductor layers is formed on the first insulating layer; A second window is formed in the insulating layer to expose the high-resistance polycrystalline semiconductor layer portion of the fifth polycrystalline semiconductor layer to the outside, and on the second insulating layer, through the second window, A semiconductor integrated circuit device, further comprising a conductive layer connected to the high-resistance polycrystalline semiconductor layer portion of the fifth polycrystalline semiconductor layer. 2. On the main surface of the semiconductor substrate having the first conductivity type, a first
forming an insulating layer on the first insulating layer, forming a first window for exposing the semiconductor substrate to the outside; forming a first polycrystalline semiconductor layer having a layer portion extending over a region facing the first window; and a second polycrystalline semiconductor layer extending across the first insulating layer. and a process of introducing impurities into the first and second polycrystalline semiconductor layers and the semiconductor substrate to impart a second conductivity type opposite to the first conductivity type. and third and fourth polycrystalline semiconductor layers formed by introducing the impurity into the second polycrystalline semiconductor layer, respectively, and the fourth polycrystalline semiconductor on the main surface side of the semiconductor substrate. A first layer into which the impurity is introduced, which extends in connection with the third polycrystalline semiconductor layer in a region on the side of the region below the third polycrystalline semiconductor layer when viewed from the region below the layer. forming a semiconductor region and introducing the impurity into a region on the main surface side of the semiconductor substrate on the opposite side to the first semiconductor region side when viewed from the region under the fourth polycrystalline semiconductor layer; selectively introducing a substance that reduces electrical conductivity into at least a layer portion of the third polycrystalline semiconductor layer facing the first window; a high-resistance polycrystalline semiconductor layer portion formed by introducing a substance that reduces the conductivity into at least a layer portion of the third polycrystalline semiconductor layer facing the first window; a step of forming a fifth polycrystalline semiconductor layer forming a low-resistance polycrystalline semiconductor layer formed by a layer portion other than a layer portion into which a substance that reduces conductivity is introduced; and a step of forming a fifth polycrystalline semiconductor layer on the first insulating layer. forming a second insulating layer extending to cover the third and fifth polycrystalline semiconductor layers; forming a second window that exposes the resistive polycrystalline semiconductor layer portion to the outside; and forming the high-resistance polycrystalline semiconductor of the fifth polycrystalline semiconductor layer on the second insulating layer through the second window. 1. A method for manufacturing a semiconductor integrated circuit device, comprising the step of forming a conductive layer connected to a layer section.