JP2000058580A - Semiconductor device having bonding pad - Google Patents
Semiconductor device having bonding padInfo
- Publication number
- JP2000058580A JP2000058580A JP10228458A JP22845898A JP2000058580A JP 2000058580 A JP2000058580 A JP 2000058580A JP 10228458 A JP10228458 A JP 10228458A JP 22845898 A JP22845898 A JP 22845898A JP 2000058580 A JP2000058580 A JP 2000058580A
- Authority
- JP
- Japan
- Prior art keywords
- pad
- layer
- semiconductor device
- film
- bonding pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明はボンディングワイヤ
が接合されるボンディングパッドを有する半導体装置及
びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a bonding pad to which a bonding wire is bonded, and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】図４に示すように、一般的に、半導体装
置は半導体基板１上にトランジスタ及び抵抗等の素子を
設け、この素子を任意に接続して回路構成している。ま
た、接続された配線の一部は、ボンディングワイヤが接
続される外部接続用端子としてボンディングパッド４ａ
を構成している。2. Description of the Related Art As shown in FIG. 4, a semiconductor device is generally provided with elements such as a transistor and a resistor on a semiconductor substrate 1, and these elements are arbitrarily connected to form a circuit. A part of the connected wiring is used as a bonding pad 4a as an external connection terminal to which a bonding wire is connected.
Is composed.
【０００３】そして、基板１上の最上層の配線を覆うカ
バー膜２におけるボンディングパッド４ａ上の位置に開
孔窓を選択的に設け、この開孔窓を介してボンディング
パッド４ａの表面を露出させ、Ａｕ等のボンディングワ
イヤ３をボンディングパッド４ａに接合し、このボンデ
ィングワイヤ３によりパッド４ａと外部とを接続してい
る。An opening window is selectively provided at a position on the bonding pad 4a in the cover film 2 covering the uppermost wiring on the substrate 1, and the surface of the bonding pad 4a is exposed through the opening window. , Au or the like is bonded to the bonding pad 4a, and the bonding wire 3 connects the pad 4a to the outside.
【０００４】ところで、近年半導体装置の高集積化、低
電圧化に伴い配線層の幅も狭くする必要があり、寸法精
度よく加工するために配線の膜厚も薄くする必要があ
る。In recent years, the width of a wiring layer has to be narrowed with the increase in the degree of integration and the voltage of a semiconductor device, and the thickness of the wiring has to be reduced in order to process with high dimensional accuracy.
【０００５】しかし、ボンディングパッド部の配線の膜
厚が薄くなると、図５に示すように、ボンディングワイ
ヤ３をパッド４ａにボンディングする場合に、パッド４
ａの金属膜の一部がワイヤ３と共に、基板１の表面から
剥がれてしまうことがある。However, when the thickness of the wiring in the bonding pad portion is reduced, as shown in FIG. 5, when the bonding wire 3 is bonded to the pad 4a, the pad 4
A part of the metal film a may be peeled off from the surface of the substrate 1 together with the wire 3.
【０００６】このため、複数の金属配線を使用する場
合、ボンディングパッド部のみ、配線を積層構造にする
ことが提案されている（特開昭６２−２４２３３３、特
開昭６３−２９３９３０）。For this reason, when a plurality of metal wirings are used, it has been proposed that the wirings have a laminated structure only in the bonding pad portion (JP-A-62-242333, JP-A-63-293930).
【０００７】[0007]
【発明が解決しようとする課題】しかしながら、１層の
金属配線しか使用しない製品においては、依然として上
記問題点を回避できない。また、上記公報に記載された
ように、ボンディングパッド部に複数の金属配線を積層
しても、合計した膜厚がボンディング強度に耐える膜厚
に達していない場合は、その効果がなく、パッドの剥離
を回避できない。However, in a product using only one layer of metal wiring, the above problem cannot be avoided. Also, as described in the above publication, even if a plurality of metal wirings are stacked on the bonding pad portion, if the total film thickness does not reach the film thickness that can withstand the bonding strength, there is no effect, and Peeling cannot be avoided.
【０００８】また、長期間又は温度変化が烈しい環境で
使用すると、プラスチックパッケージ樹脂の劣化又は延
び縮みでカバー膜に応力が加わる。そうすると、図５に
示すように、カバー膜２表面に起伏があると、起伏の高
い部分に応力が集中し、配線がスライドして、配線の断
線又は短絡が生じることがある。Further, when the cover film is used for a long period of time or in an environment in which the temperature changes drastically, stress is applied to the cover film due to deterioration or expansion and contraction of the plastic package resin. Then, as shown in FIG. 5, if the surface of the cover film 2 has undulations, stress concentrates on a portion with high undulations, the wiring slides, and the wiring may be disconnected or short-circuited.
【０００９】本発明はかかる問題点に鑑みてなされたも
のであって、ボンディングパッドの剥離を確実に防止す
ることができ、配線がスライドすることもなく、信頼性
が高いボンディングパッドを有する半導体装置を提供す
ることを目的とする。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and a semiconductor device having a highly reliable bonding pad which can surely prevent peeling of a bonding pad, does not slide wiring, and has a high reliability. The purpose is to provide.
【００１０】[0010]
【課題を解決するための手段】本発明に係るボンディン
グパッドを有する半導体装置は、半導体基板上に設けら
れた１又は複数層の第１層配線の一部により構成される
パッド第１層と、このパッド第１層上に形成された１又
は複数層のパッド第２層と、前記半導体基板の表面を覆
うカバー膜と、を有し、前記パッド第１層とパッド第２
層とによりボンディングパッドが構成され、前記パッド
第２層の表面は前記カバー膜と面一で露出していること
を特徴とする。According to the present invention, there is provided a semiconductor device having a bonding pad, comprising: a pad first layer formed by a part of one or a plurality of first layer wirings provided on a semiconductor substrate; One or more pad second layers formed on the pad first layer, and a cover film covering a surface of the semiconductor substrate; the pad first layer and the pad second layer;
A bonding pad is constituted by the layer and the surface of the pad second layer is exposed flush with the cover film.
【００１１】このボンディングパッドを有する半導体装
置において、前記パッド第１層及びパッド第２層は、金
属膜又は多結晶半導体膜とすることができる。In the semiconductor device having the bonding pad, the first pad layer and the second pad layer may be a metal film or a polycrystalline semiconductor film.
【００１２】また、本発明に係るボンディングパッドを
有する半導体装置の製造方法は、半導体基板上に第１層
配線を形成する工程と、この第１層配線を含む半導体基
板表面上を覆うようにしてカバー膜を形成する工程と、
前記第１層配線上で前記カバー膜に選択的に開口部を形
成する工程と、前記開口部を含む領域に１層又は複数層
の導電膜を形成する工程と、全面を研磨して前記開口部
内の導電膜と前記カバー膜とを同一平面に加工する工程
と、を有することを特徴とする。In a method of manufacturing a semiconductor device having a bonding pad according to the present invention, a step of forming a first layer wiring on a semiconductor substrate and a step of covering a surface of the semiconductor substrate including the first layer wiring are performed. Forming a cover film;
Selectively forming an opening in the cover film on the first layer wiring, forming one or more conductive films in a region including the opening, and polishing the entire surface to form the opening. Processing the conductive film in the part and the cover film on the same plane.
【００１３】このボンディングパッドを有する半導体装
置の製造方法において、前記カバー膜の厚さは前記第１
層配線の厚さの１．５倍以上の厚さを有することが好ま
しく、また、前記研磨は、化学的機械的研磨法により研
磨するものであることが好ましい。In the method of manufacturing a semiconductor device having the bonding pads, the thickness of the cover film is equal to the first thickness.
The thickness is preferably 1.5 times or more the thickness of the layer wiring, and the polishing is preferably performed by a chemical mechanical polishing method.
【００１４】本発明においては、パッド第２層の表面が
カバー膜の表面と同一平面になるように、パッド第１層
及びパッド第２層がカバー膜内に埋め込まれているの
で、カバー膜の厚さとパッド第２層の厚さとを任意に組
み合わせることにより、パッド第１層及びパッド第２層
から構成されるボンディングパッドを十分に厚く設ける
ことができる。In the present invention, the pad first layer and the pad second layer are embedded in the cover film so that the surface of the pad second layer is flush with the surface of the cover film. By arbitrarily combining the thickness and the thickness of the pad second layer, a sufficiently thick bonding pad composed of the pad first layer and the pad second layer can be provided.
【００１５】また、この平坦面を、化学的機械的研磨法
（ＣＭＰ）により研磨することにより、パッド第２層及
びカバー膜の表面を容易に平坦化することができる。The surface of the second pad layer and the cover film can be easily flattened by polishing the flat surface by a chemical mechanical polishing method (CMP).
【００１６】[0016]
【発明の実施の形態】以下、本発明の実施例について添
付の図面を参照して具体的に説明する。図１は本発明の
実施例に係るボンディングパッドを有する半導体装置を
示す断面図、図２及び図３はその製造工程を示す断面図
である。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be specifically described below with reference to the accompanying drawings. FIG. 1 is a sectional view showing a semiconductor device having a bonding pad according to an embodiment of the present invention, and FIGS. 2 and 3 are sectional views showing the manufacturing steps.
【００１７】図１に示すように、本実施例に係る半導体
装置は、半導体基板１の表面に形成された素子を接続す
る種々の配線６の一部として、パッド第１層４が設けら
れており、このパッド第１層４の上に、金属又は多結晶
シリコン層等の導電膜により形成されたパッド第２層５
が形成されている。この配線６、パッド第１層４及びパ
ッド第２層５は基板１上を被覆する絶縁性のカバー膜２
に埋め込まれている。このカバー膜２の表面とパッド第
２層５の表面とは面一、即ち同一平面を構成している。
そして、パッド第１層４及びパッド第２層５によりボン
ディングパッドが構成される。As shown in FIG. 1, in the semiconductor device according to the present embodiment, a first pad layer 4 is provided as a part of various wirings 6 connecting elements formed on the surface of a semiconductor substrate 1. And a pad second layer 5 formed of a conductive film such as a metal or polycrystalline silicon layer on the pad first layer 4.
Are formed. The wiring 6, the first pad layer 4 and the second pad layer 5 form an insulating cover film 2 covering the substrate 1.
Embedded in The surface of the cover film 2 and the surface of the pad second layer 5 are flush with each other, that is, they are flush with each other.
The pad first layer 4 and the pad second layer 5 form a bonding pad.
【００１８】このように構成された半導体装置において
は、配線６の一部であるパッド第１層４の厚さは、近年
の半導体装置の高集積化及び低電圧化に伴う薄膜化の要
求により十分に薄くしても、このパッド第１層４の上に
形成されるパッド第２層５の厚さを、カバー膜２の厚さ
を厚くすることにより、十分に厚くすることができる。
このため、パッド第１層４及びパッド第２層５により構
成されるボンディングパッドとしては、ワイヤボンディ
ングに十分耐えられる強度を有するものとなる。In the semiconductor device configured as described above, the thickness of the first pad layer 4, which is a part of the wiring 6, is required to be reduced due to recent demand for higher integration and lower voltage of the semiconductor device. Even if it is sufficiently thin, the thickness of the pad second layer 5 formed on the pad first layer 4 can be made sufficiently large by increasing the thickness of the cover film 2.
For this reason, the bonding pad constituted by the first pad layer 4 and the second pad layer 5 has sufficient strength to withstand wire bonding.
【００１９】次に、本発明の実施例に係る半導体装置の
製造方法について説明する。図２に示すように、先ず、
半導体基板１上に、この基板表面に形成した素子を接続
する配線６を形成し、この配線６の一部としてパッド第
１層４を形成する。Next, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described. As shown in FIG.
On the semiconductor substrate 1, a wiring 6 for connecting elements formed on the substrate surface is formed, and a pad first layer 4 is formed as a part of the wiring 6.
【００２０】次に、カバー膜２をボンディングパッドの
パッド第１層４の膜厚（即ち、第１層配線６の膜厚）の
１．５倍以上の膜厚で設け、パッド第１層４の上の部分
を選択的に開孔し、開口部７を形成する。これにより、
パッド第１層４の表面の一部が露出する。Next, the cover film 2 is provided with a thickness of 1.5 times or more the thickness of the first pad layer 4 of the bonding pad (that is, the thickness of the first layer wiring 6). The upper part is selectively opened to form an opening 7. This allows
Part of the surface of the pad first layer 4 is exposed.
【００２１】次に、図３に示すように、全面に第２の金
属膜５ａを形成し、化学的機械的研磨法（ＣＭＰ）技術
により、所望の膜厚だけ、即ち、パッド第１層４上の第
２の金属膜５ａ部分の研磨が開始されるまで、第２の金
属膜５ａ及びカバー膜２を研磨する。これにより、図１
に示すように、パッド第１層４上の第２の金属膜５ａ
（パッド第２層５）の表面とカバー膜２の表面とが同一
平面に平坦化される。Next, as shown in FIG. 3, a second metal film 5a is formed on the entire surface, and a desired film thickness, that is, the first pad layer 4 is formed by a chemical mechanical polishing (CMP) technique. The second metal film 5a and the cover film 2 are polished until the polishing of the upper second metal film 5a starts. As a result, FIG.
As shown in FIG. 5, the second metal film 5a on the pad first layer 4
The surface of (pad second layer 5) and the surface of cover film 2 are planarized on the same plane.
【００２２】本実施例においては、カバー膜２をボンデ
ィングパッドのパッド第１層４（即ち、配線膜厚）の
１．５倍以上の厚さで厚く設けているので、ＣＭＰ後
は、パッド第１層４のみならず、他の配線６の間も埋め
込んでこれらを完全に平坦化できる。従って、ボンディ
ング後、プラスチック樹脂等で封入する際もカバー表面
に均一に応力が加わる。In this embodiment, since the cover film 2 is provided with a thickness of 1.5 times or more of the first pad layer 4 of the bonding pad (that is, the wiring film thickness), the pad film is formed after the CMP. By embedding not only the first layer 4 but also the space between the other wirings 6, these can be completely flattened. Therefore, even after sealing with a plastic resin or the like after bonding, stress is uniformly applied to the cover surface.
【００２３】半導体装置を長期間又は温度変化が烈しい
環境で使用すると プラスチックパッケージ樹脂の劣化
又は延び縮みでカバー膜２に応力が加わる。従来の図５
に示すように、カバー膜２の表面に起伏があると、この
起伏が高い部分に応力が集中し、配線がスライドして配
線の断線又は短絡が生じやすくなる。When the semiconductor device is used for a long period of time or in an environment in which the temperature changes drastically, stress is applied to the cover film 2 due to deterioration or expansion and contraction of the plastic package resin. Conventional FIG.
As shown in (2), when the surface of the cover film 2 has undulations, stress concentrates on the portion where the undulations are high, and the wiring slides to easily cause disconnection or short circuit of the wiring.
【００２４】これに対し、本発明実施例では、カバー膜
２及びボンディングパッドにより構成される半導体装置
表面を平坦に設けているので、この表面には均一に応力
が加わる。従って、本実施例においては、配線がスライ
ドすることもなく、信頼性が高いカバー膜を形成するこ
とができ、従って、高信頼性の半導体装置を製造するこ
とができる。On the other hand, in the embodiment of the present invention, since the surface of the semiconductor device constituted by the cover film 2 and the bonding pad is provided flat, stress is uniformly applied to this surface. Therefore, in this embodiment, a highly reliable cover film can be formed without wiring sliding, and a highly reliable semiconductor device can be manufactured.
【００２５】また、ＣＭＰ技術を用いてカバー膜２と第
２の金属膜５ａを同時に研磨して半導体基板表面を平坦
にしているので、平坦化処理に伴う製造工程の増大を防
止でき、半導体装置の製造コストを上昇させることがな
い。Further, since the cover film 2 and the second metal film 5a are simultaneously polished by the CMP technique to flatten the surface of the semiconductor substrate, it is possible to prevent an increase in the number of manufacturing steps accompanying the flattening process, and to prevent the semiconductor device Does not increase the manufacturing cost.
【００２６】例えば、ＣＭＰの代わりに、フォトリゾグ
ラフィ技術を用いて、第２の金属膜５ａを選択エッチン
グする場合は、フォトレジストを選択的に設ける工程、
フォトレジストをマスクに第２の金属膜を選択エッチす
る工程及び前記フォトレジストを除去する工程が必要に
なり、製造工程も長く、製造コストを増大させる。しか
し、本実施例のように、ＣＭＰ研磨することにより、こ
のような問題点を回避できる。For example, in the case where the second metal film 5a is selectively etched using a photolithography technique instead of the CMP, a step of selectively providing a photoresist,
A step of selectively etching the second metal film using a photoresist as a mask and a step of removing the photoresist are required, so that the manufacturing process is long and the manufacturing cost is increased. However, such problems can be avoided by performing CMP polishing as in the present embodiment.
【００２７】なお、上述の実施例においては、ボンディ
ングパッドを構成するパッド第１層４は１層の金属配線
であるが、このパッド第１層としては、複数の金属膜を
積層したものでもよく、又は多結晶シリコン膜等の導電
膜を使用してもよい。In the above-described embodiment, the first pad layer 4 constituting the bonding pad is a single-layer metal wiring, but the first pad layer may be formed by laminating a plurality of metal films. Alternatively, a conductive film such as a polycrystalline silicon film may be used.
【００２８】[0028]
【発明の効果】以上説明したように、本発明によれば、
ボンディングパッドの剥離を防止することができると共
に、配線のスライドのような問題もなく、高信頼性の半
導体装置を製造することができる。As described above, according to the present invention,
It is possible to prevent peeling of the bonding pad and to manufacture a highly reliable semiconductor device without problems such as sliding of wiring.
【図１】本発明の実施例に係る半導体装置を示す断面図
である。FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention.
【図２】同じくその製造工程を示す断面図である。FIG. 2 is a cross-sectional view showing the same manufacturing process.
【図３】同じくその製造工程を示す断面図である。FIG. 3 is a cross-sectional view showing the same manufacturing process.
【図４】従来の半導体装置のボンディングパッド部分を
示す断面図である。FIG. 4 is a cross-sectional view showing a bonding pad portion of a conventional semiconductor device.
【図５】同じくその従来技術の欠点を説明する断面図で
ある。FIG. 5 is a cross-sectional view for explaining the disadvantages of the related art.
１：半導体基板 ２：カバー膜 ３：ボンディングワイヤ ４ａ：ボンディングパッド ４：パッド第１層 ５：パッド第２層 ５ａ：第２の金属膜 ６：配線 ７：開口部 1: Semiconductor substrate 2: Cover film 3: Bonding wire 4a: Bonding pad 4: Pad first layer 5: Pad second layer 5a: Second metal film 6: Wiring 7: Opening
Claims (5)
の第１層配線の一部により構成されるパッド第１層と、
このパッド第１層上に形成された１又は複数層のパッド
第２層と、前記半導体基板の表面を覆うカバー膜と、を
有し、前記パッド第１層とパッド第２層とによりボンデ
ィングパッドが構成され、前記パッド第２層の表面は前
記カバー膜と面一で露出していることを特徴とするボン
ディングパッドを有する半導体装置。A pad first layer formed by a part of one or a plurality of first layer wirings provided on a semiconductor substrate;
One or more pad second layers formed on the pad first layer, and a cover film covering the surface of the semiconductor substrate, and a bonding pad is formed by the pad first layer and the pad second layer. Wherein the surface of the pad second layer is exposed flush with the cover film.
金属膜又は多結晶半導体膜であることを特徴とする請求
項１に記載のボンディングパッドを有する半導体装置。2. The pad first layer and the pad second layer,
The semiconductor device having a bonding pad according to claim 1, wherein the semiconductor device is a metal film or a polycrystalline semiconductor film.
程と、この第１層配線を含む半導体基板表面上を覆うよ
うにしてカバー膜を形成する工程と、前記第１層配線上
で前記カバー膜に選択的に開口部を形成する工程と、前
記開口部を含む領域に１層又は複数層の導電膜を形成す
る工程と、全面を研磨して前記開口部内の導電膜と前記
カバー膜とを同一平面に加工する工程と、を有すること
を特徴とするボンディングパッドを有する半導体装置の
製造方法。3. A step of forming a first layer wiring on a semiconductor substrate, a step of forming a cover film so as to cover a surface of the semiconductor substrate including the first layer wiring, and a step of forming a cover film on the first layer wiring. A step of selectively forming an opening in the cover film, a step of forming one or more conductive films in a region including the opening, and polishing the entire surface to form a conductive film in the opening and the cover. Processing a film on the same plane, and a method of manufacturing a semiconductor device having a bonding pad.
厚さの１．５倍以上の厚さを有することを特徴とする請
求項３に記載のボンディングパッドを有する半導体装置
の製造方法。4. The method according to claim 3, wherein the thickness of the cover film is at least 1.5 times the thickness of the first layer wiring. Method.
研磨するものであることを特徴とする請求項３又は４の
いずれか１項に記載のボンディングパッドを有する半導
体装置の製造方法。5. The method of manufacturing a semiconductor device having a bonding pad according to claim 3, wherein the polishing is performed by a chemical mechanical polishing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10228458A JP2000058580A (en) | 1998-08-13 | 1998-08-13 | Semiconductor device having bonding pad |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10228458A JP2000058580A (en) | 1998-08-13 | 1998-08-13 | Semiconductor device having bonding pad |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000058580A true JP2000058580A (en) | 2000-02-25 |
Family
ID=16876813
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10228458A Pending JP2000058580A (en) | 1998-08-13 | 1998-08-13 | Semiconductor device having bonding pad |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000058580A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102005019574A1 (en) * | 2005-04-27 | 2006-11-09 | Infineon Technologies Ag | Contact arrangement for semiconductor component e.g. integrated circuit (IC) has reinforcement layer formed on contact surface and protrudes above insulating layer |
| JP2011181825A (en) * | 2010-03-03 | 2011-09-15 | Omron Corp | Method of manufacturing connection pad |
| WO2011148819A1 (en) * | 2010-05-28 | 2011-12-01 | 日本碍子株式会社 | Impedance matching element |
| JP2014110280A (en) * | 2012-11-30 | 2014-06-12 | Mitsubishi Electric Corp | Electronic device and method of manufacturing the same |
-
1998
- 1998-08-13 JP JP10228458A patent/JP2000058580A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102005019574A1 (en) * | 2005-04-27 | 2006-11-09 | Infineon Technologies Ag | Contact arrangement for semiconductor component e.g. integrated circuit (IC) has reinforcement layer formed on contact surface and protrudes above insulating layer |
| DE102005019574B4 (en) * | 2005-04-27 | 2009-07-30 | Infineon Technologies Ag | Contacting arrangement for a semiconductor device |
| JP2011181825A (en) * | 2010-03-03 | 2011-09-15 | Omron Corp | Method of manufacturing connection pad |
| WO2011148819A1 (en) * | 2010-05-28 | 2011-12-01 | 日本碍子株式会社 | Impedance matching element |
| US8878625B2 (en) | 2010-05-28 | 2014-11-04 | Ngk Insulators, Ltd. | Impedance matching device |
| JP2014110280A (en) * | 2012-11-30 | 2014-06-12 | Mitsubishi Electric Corp | Electronic device and method of manufacturing the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2974022B1 (en) | Bonding pad structure of semiconductor device | |
| US7566944B2 (en) | Package structure for optoelectronic device and fabrication method thereof | |
| US5521434A (en) | Semiconductor chip and electronic module with integrated surface interconnects/components | |
| JP5474534B2 (en) | Passivation and contact surrounded by polyimide and method of manufacturing the same | |
| JP2003100894A (en) | Integrated circuit chip and multi-chip package | |
| WO2006019156A1 (en) | Method for manufacturing semiconductor device having three-dimensional multilayer structure | |
| US7227214B2 (en) | Semiconductor device and method of manufacturing the same | |
| JPH10223636A (en) | Manufacture of semiconductor integrated circuit device | |
| JP2948018B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP2000150429A (en) | Semiconductor device and its manufacture | |
| JP2000058580A (en) | Semiconductor device having bonding pad | |
| US6831368B2 (en) | Semiconductor device and method of manufacturing the same | |
| JP2003110108A (en) | Method of manufacturing semiconductor device and structure thereof | |
| JP2006210802A (en) | Semiconductor device | |
| JP5291946B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP2001024056A (en) | Multi-layered wiring device for semiconductor device, and manufacture thereof | |
| JPH0845935A (en) | Forming method of multilayer interconnection | |
| JP2580324B2 (en) | Semiconductor device | |
| JPH07202066A (en) | Mounting construction of semiconductor | |
| JP2869978B2 (en) | Semiconductor device | |
| JPH11284066A (en) | Semiconductor device and manufacture thereof | |
| KR100422343B1 (en) | stack package and method of fabricating the same | |
| JPH1074836A (en) | Semiconductor device | |
| JP2004281916A (en) | Semiconductor device and manufacturing method for the same | |
| JP2004158678A (en) | Bonding pad |