JPS6387762A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6387762A JPS6387762A JP23362086A JP23362086A JPS6387762A JP S6387762 A JPS6387762 A JP S6387762A JP 23362086 A JP23362086 A JP 23362086A JP 23362086 A JP23362086 A JP 23362086A JP S6387762 A JPS6387762 A JP S6387762A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- resistor
- polycrystalline silicon
- silicon layer
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000002184 metal Substances 0.000 claims abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims abstract description 6
- 239000012535 impurity Substances 0.000 claims abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 30
- 239000011368 organic material Substances 0.000 claims description 7
- 238000001312 dry etching Methods 0.000 claims description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 7
- 229910052710 silicon Inorganic materials 0.000 abstract description 7
- 239000010703 silicon Substances 0.000 abstract description 7
- 230000010354 integration Effects 0.000 abstract description 5
- 150000002739 metals Chemical class 0.000 abstract description 2
- 238000001259 photo etching Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 235000006732 Torreya nucifera Nutrition 0.000 description 1
- 244000111306 Torreya nucifera Species 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の製造方法に関し、特に多結晶シ
リコンを用いた抵抗の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a resistor using polycrystalline silicon.
従来、半導体装置に使用される抵抗は例えばシリコン基
板中の単結晶領域に形成される拡散抵抗と、基板上の多
結晶シリコンを抵抗として使用する多結晶シリコン抵抗
に大別されるが、近年、高周波化、高集積化が進むにつ
れ、寄生容量や占有面積の点で有利な多結晶シリコン抵
抗が多用されるようになってきた。Conventionally, resistors used in semiconductor devices are roughly divided into, for example, diffused resistors formed in a single crystal region in a silicon substrate, and polycrystalline silicon resistors that use polycrystalline silicon on the substrate as a resistor. As higher frequencies and higher integration progress, polycrystalline silicon resistors, which are advantageous in terms of parasitic capacitance and occupied area, have come into widespread use.
第2図に多結晶シリコン抵抗の一例を示す。FIG. 2 shows an example of a polycrystalline silicon resistor.
第2図において、1は半導体基板、2は基板上のフィー
ルド用酸化膜、7AはN型又はP型の不純物がドープさ
れた多結晶シリコン層からなる抵抗体層、4は抵抗体層
7A上の酸化シリコン膜等からなる絶縁層、5は抵抗体
層7Aと電気的接触をとるための電極引出し用金属であ
る。In FIG. 2, 1 is a semiconductor substrate, 2 is a field oxide film on the substrate, 7A is a resistor layer made of a polycrystalline silicon layer doped with N-type or P-type impurities, and 4 is on the resistor layer 7A. An insulating layer 5 is made of a silicon oxide film or the like, and 5 is an electrode lead metal for making electrical contact with the resistor layer 7A.
しかしながら上述した従来の多結晶シリコン抵抗には次
のような欠点がある。即ち、
(1)一般に、抵抗値の精度を確保するため、第2図に
示したように抵抗体層の断面形状はできるだけ垂直であ
ることが望ましいが、その結果第2図に示したような段
差8が生じてしまうために、電極引出し用金属5の被覆
性が悪くなり、ひいては断線等を生じ、信頼度上の大き
な問題となる。However, the conventional polycrystalline silicon resistor described above has the following drawbacks. That is, (1) Generally, in order to ensure the accuracy of the resistance value, it is desirable that the cross-sectional shape of the resistor layer be as vertical as possible, as shown in Figure 2. Since the step 8 is formed, the coverage of the metal 5 for leading out the electrode is deteriorated, and wire breakage and the like occur, which poses a serious problem in terms of reliability.
(2)更に、高集積化を図るためには、素子サイズの縮
少化と共に素子間隔も減少させる必要がある。しかしな
がら、通例、多結晶シリコンからなる抵抗体層7Aの膜
厚は2000〜3000人が使用され、しかも多結晶抵
抗体層7A上の絶縁層4の膜厚も2000〜3000人
であるため、抵抗全体の厚さは4000〜6000人に
も達する。(2) Furthermore, in order to achieve higher integration, it is necessary to reduce the element size and the element spacing. However, the thickness of the resistor layer 7A made of polycrystalline silicon is usually 2,000 to 3,000 µm, and the thickness of the insulating layer 4 on the polycrystalline resistor layer 7A is also 2,000 to 3,000 µm. The total thickness reaches 4,000 to 6,000 people.
従って、隣接する素子との間隔を、−室以上に保たない
とフォトレジスト工程での光の干渉等により抜は不良や
、寸法精度の誤差を生じてしまい、微細パターンを形成
する上で重大な障害となり、また、結局は、高集積化を
妨げる原因となる。Therefore, if the distance between adjacent elements is not kept at least -100 cm, interference of light during the photoresist process will result in defective punching and errors in dimensional accuracy, which is critical when forming fine patterns. This becomes a major hindrance, and ultimately becomes a cause of hindering high integration.
本発明の目的は、上記問題点を除去し、抵抗値の精度の
高い抵抗を有する高集積化された半導体装置の製造方法
を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned problems and provide a method for manufacturing a highly integrated semiconductor device having a resistor with a highly accurate resistance value.
本発明の半導体装置の製造方法は、半導体基板上にフィ
ールド用酸化膜を形成する工程と、酸化膜に選択的に凹
部を形成する工程と、不純物を添加した多結晶シリコン
層を少なくとも前記凹部の深さ以上に積層する工程と、
多結晶シリコン層上に、有機物質膜を積層し表面を平坦
化する工程と、前記多結晶シリコンと有機物質膜とに対
しほぼ同一のエツチングレートを有するガスを用いるド
ライエツチングにより、前記凹部領域以外の多結晶シリ
コン層と有機物質膜を除去する工程と、少な 。The method of manufacturing a semiconductor device of the present invention includes the steps of forming a field oxide film on a semiconductor substrate, selectively forming a recess in the oxide film, and depositing an impurity-doped polycrystalline silicon layer at least in the recess. The process of laminating layers beyond the depth,
By stacking an organic material film on the polycrystalline silicon layer and flattening the surface, and by dry etching using a gas having approximately the same etching rate for the polycrystalline silicon and the organic material film, the areas other than the recessed areas are etched. a process of removing the polycrystalline silicon layer and the organic material film;
くとも凹部領域中の多結晶シリコン層上に選択的に絶縁
膜を形成する工程と、前記凹部領域中の多結晶シリコン
層と電気的接触を行なう金属層を形成する工程とを含ん
で構成される。At least the step of selectively forming an insulating film on the polycrystalline silicon layer in the recessed region, and the step of forming a metal layer making electrical contact with the polycrystalline silicon layer in the recessed region. Ru.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第1図(a)〜(e)は本発明の一実例例を説明するた
めの工程順に示した半導体チップの断面図である。FIGS. 1A to 1E are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an example of the present invention.
まず、第1図(a)に示すように半導体基板1上にフィ
ールド用酸化膜2を形成し、写真食刻法により、四部6
を形成する。First, as shown in FIG. 1(a), a field oxide film 2 is formed on a semiconductor substrate 1, and four parts 6 are formed by photolithography.
form.
次に第1図(b)に示すようにN又はP型不純物を添加
した多結晶シリコン層を積層し、更に、この多結晶シリ
コン層7の上部に、フォトレジスト層9を堆積し、平坦
な表面に形成する。このとき多結晶シリコン層7の厚さ
は凹部6の深さ以上であればよい。また、多結晶シリコ
ン層7の上の層は適度な粘性があって、表面の平坦化が
図れるポリイミド等の有機物質であれば、フォトレジス
ト以外のものでもよい。Next, as shown in FIG. 1(b), a polycrystalline silicon layer doped with N or P type impurities is laminated, and then a photoresist layer 9 is deposited on top of this polycrystalline silicon layer 7 to form a flat layer. Form on the surface. At this time, the thickness of the polycrystalline silicon layer 7 may be at least the depth of the recess 6. Further, the layer above the polycrystalline silicon layer 7 may be made of an organic material other than photoresist as long as it has an appropriate viscosity and can flatten the surface, such as polyimide.
次に、第1図(C)に示すように、多結晶シリコン層7
とフォトレジスト層9に対してほぼ同一のエツチング・
レートを有するガス、例えばCCe4と02との混合ガ
スを用いる異方性エツチングを行ない、フォトレジスト
層9及び多結晶シリコン層7を除去すると四部6に多結
晶シリコンからなる抵抗体層7Aが残される。Next, as shown in FIG. 1(C), a polycrystalline silicon layer 7
and photoresist layer 9 with almost the same etching process.
When the photoresist layer 9 and the polycrystalline silicon layer 7 are removed by anisotropic etching using a gas having a certain rate, for example, a mixed gas of CCe4 and 02, a resistor layer 7A made of polycrystalline silicon is left in the four parts 6. .
次に第1図(d)に示すように、抵抗体層7A上に選択
的に絶縁層4(例えば酸化膜)を形成したのち、抵抗体
層7Aの両端に電極引出し用金属5を付着することによ
り多結晶シリコンからなる抵抗体を完成させる。。Next, as shown in FIG. 1(d), after selectively forming an insulating layer 4 (for example, an oxide film) on the resistor layer 7A, electrode lead metals 5 are attached to both ends of the resistor layer 7A. As a result, a resistor made of polycrystalline silicon is completed. .
尚、第1図(e)に示すように、抵抗体層7A上を含む
フィールド用酸化膜2の全面に酸化膜や、窒化膜等の絶
縁膜4Aを積層し、コンタクト用開孔部を形成したのち
、電極引出し用金属5Aを設けてもよい。As shown in FIG. 1(e), an insulating film 4A such as an oxide film or a nitride film is laminated on the entire surface of the field oxide film 2 including on the resistor layer 7A, and a contact opening is formed. After that, a metal 5A for drawing out the electrode may be provided.
以上説明したように本発明は、多結晶シリコン層をフィ
ールド用酸化膜中に埋め込み抵抗体層を形成し、表面を
平坦化して抵抗体を形成した結果、次のような効果があ
る。As explained above, the present invention has the following effects as a result of forming a resistor layer by burying a polycrystalline silicon layer in a field oxide film and flattening the surface to form a resistor.
(1)従来の製造方法で問題となった抵抗層の段差は無
くせるのみならず、断面形状はそのまま維持できるため
精度の高い抵抗値を有する抵抗を備えた半導体装置が得
られる。(1) Not only can the step difference in the resistance layer, which is a problem in conventional manufacturing methods, be eliminated, but also the cross-sectional shape can be maintained as it is, so a semiconductor device equipped with a resistor having a highly accurate resistance value can be obtained.
(2)多結晶シリコン抵抗部によるフォトレジスト工程
における露光時の光の干渉等を除くことができるため、
抵抗体のごく近傍にも素子領域が形成でき、半導体装置
の高集積化が実現できる。(2) Light interference during exposure in the photoresist process due to the polycrystalline silicon resistor can be eliminated;
The element region can be formed very close to the resistor, and high integration of the semiconductor device can be realized.
第1図(a)〜(e)は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面図、第2図は従
来の半導体装置の一例を説明するための断面図である。
1・・・半導体基板、2・・・フィールド用酸化膜、4
゜4A・・・絶縁層、4,5A・・・電極引出し用金属
、6・・・凹部、7・・・多結晶シリコン層、7A・・
・抵抗体層、8・・・段差、9・・・フォトレジ・スト
層。
乙I!I名p
茅 / 圀FIGS. 1(a) to (e) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention, and FIG. 2 is a cross-sectional view for explaining an example of a conventional semiconductor device. be. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Oxide film for field, 4
゜4A...Insulating layer, 4,5A...Metal for electrode extraction, 6...Concave portion, 7...Polycrystalline silicon layer, 7A...
- Resistor layer, 8... Step, 9... Photoresist layer. Otsu I! I name p Kaya/Ki
Claims (1)
、該酸化膜に選択的に凹部を形成する工程と、全面に不
純物を添加した多結晶シリコン層を少なくとも前記凹部
の深さ以上に積層する工程と、該多結晶シリコン層上に
、有機物質膜を積層し表面を平坦化する工程と、前記多
層結晶シリコンと有機物質膜とに対しほぼ同一のエッチ
ングレートを有するガスを用いるドライエッチングによ
り前記凹部領域以外の前記多結晶シリコン層と有機物質
膜を除去する工程と、少なくとも前記凹部領域中の多結
晶シリコン層上に選択的に絶縁膜を形成する工程と、前
記凹部領域中の多結晶シリコン層と電気的接触を行なう
金属層を形成する工程とを含むことを特徴とする半導体
装置の製造方法。A step of forming a field oxide film on a semiconductor substrate, a step of selectively forming a recess in the oxide film, and a step of stacking a polycrystalline silicon layer doped with impurities over the entire surface to a depth at least equal to or greater than the depth of the recess. The recessed portion is formed by stacking an organic material film on the polycrystalline silicon layer and flattening the surface, and dry etching using a gas having substantially the same etching rate for the multilayer crystalline silicon and the organic material film. a step of removing the polycrystalline silicon layer and an organic material film other than the region; a step of selectively forming an insulating film on at least the polycrystalline silicon layer in the recessed region; and a step of selectively forming an insulating film on the polycrystalline silicon layer in the recessed region. 1. A method of manufacturing a semiconductor device, comprising: forming a metal layer for making electrical contact with the semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23362086A JPS6387762A (en) | 1986-09-30 | 1986-09-30 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23362086A JPS6387762A (en) | 1986-09-30 | 1986-09-30 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6387762A true JPS6387762A (en) | 1988-04-19 |
Family
ID=16957900
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP23362086A Pending JPS6387762A (en) | 1986-09-30 | 1986-09-30 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6387762A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03154372A (en) * | 1989-11-10 | 1991-07-02 | Toshiba Corp | Semiconductor device and manufacture thereof |
JPH0499366A (en) * | 1990-08-17 | 1992-03-31 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
US6524941B2 (en) | 1998-06-08 | 2003-02-25 | International Business Machines Corporation | Sub-minimum wiring structure |
JP2008270333A (en) * | 2007-04-17 | 2008-11-06 | Sony Corp | Semiconductor device and its manufacturing method |
JP2009055029A (en) * | 2007-08-23 | 2009-03-12 | Samsung Electronics Co Ltd | Semiconductor device having resistive element, and method of forming the same |
-
1986
- 1986-09-30 JP JP23362086A patent/JPS6387762A/en active Pending
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03154372A (en) * | 1989-11-10 | 1991-07-02 | Toshiba Corp | Semiconductor device and manufacture thereof |
JPH0499366A (en) * | 1990-08-17 | 1992-03-31 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
US6524941B2 (en) | 1998-06-08 | 2003-02-25 | International Business Machines Corporation | Sub-minimum wiring structure |
JP2008270333A (en) * | 2007-04-17 | 2008-11-06 | Sony Corp | Semiconductor device and its manufacturing method |
JP4600417B2 (en) * | 2007-04-17 | 2010-12-15 | ソニー株式会社 | Manufacturing method of semiconductor device |
US7858484B2 (en) | 2007-04-17 | 2010-12-28 | Sony Corporation | Semiconductor device and method for producing the same |
JP2009055029A (en) * | 2007-08-23 | 2009-03-12 | Samsung Electronics Co Ltd | Semiconductor device having resistive element, and method of forming the same |
US8610218B2 (en) | 2007-08-23 | 2013-12-17 | Samsung Electronics Co., Ltd. | Semiconductor device having a stable resistor and methods of forming the same |
US9379115B2 (en) | 2007-08-23 | 2016-06-28 | Samsung Electronics Co., Ltd. | Semiconductor device having a resistor and methods of forming the same |
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