JPS5823745B2 - MOS - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing an MO8 type integrated circuit device, and an object of the present invention is to provide a MO8 type integrated circuit device with high density and high manufacturing yield.

FIG. 1 shows a conventional method of manufacturing an MO8 type integrated circuit.

First, a silicon nitride film 12 is formed in an island shape on the main plane of a silicon semiconductor substrate 11 having one conductivity type, and a portion 13 of the a1 silicon semiconductor substrate 11 that is not covered with the silicon nitride film 12 is selectively oxidized to make silicon An oxide film 14 is formed, and the silicon nitride film 12 is removed.

Next, polycrystalline silicon films 15 and 15' containing impurities of conductivity type opposite to that of the silicon semiconductor substrate 11 are formed in the form of islands.
0 The surfaces of the polycrystalline silicon film 15.15'A and the silicon semiconductor substrate 11 are entirely oxidized to form a silicon oxide film 1.
At the same time, the ease and drain regions 17 of a MOS transistor are formed using the polycrystalline silicon film 15 as an impurity diffusion source.

The silicon oxide film 16 is selectively etched to remove the wiring metal 19 and the polycrystalline silicon films 15, 15 that will become the wiring layer.
'A contact hole 18 is formed for connection with the metal 19, and a predetermined wiring metal 19 is formed.e.

In the manufacturing method shown in FIG.
? The insulation between the polycrystalline silicon film 15, which also serves as a contact, and the polycrystalline silicon film 15b, which is used as the first layer wiring, is maintained by the distance 20 shown in FIG. has been done,
Usually 5μ or more is required.

Therefore, in the case of a large-scale MO3 type integrated circuit, the chip area becomes large and the manufacturing cost becomes high.

Further, as is clear from FIG. 1e, since the wiring metal 19 is wired across a highly uneven cross section, disconnection is likely to occur, which poses a major problem in terms of manufacturing yield of MO8 type integrated circuits.

Therefore, the present invention realizes high integration density of MO8 type integrated circuits, reduces the unevenness on the surface of the integrated circuits to prevent disconnection of metal wiring, improves the manufacturing yield of MO8 type integrated circuits, and reduces manufacturing costs. The aim is to reduce this.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 shows an embodiment of the method for manufacturing an MO8 type integrated circuit according to the present invention.

A silicon nitride film 22 is formed in an island shape on the main plane of a silicon semiconductor substrate 21 having one conductivity type, and a portion 23 of the A1 silicon semiconductor substrate 21 that is not covered with the silicon nitride film 22 is selectively oxidized to oxidize silicon. A membrane 24,
The silicon nitride film 22 is removed 80. Next, a three-layer film consisting of the silicon semiconductor substrate 21, a polycrystalline silicon film 25 containing impurities of opposite conductivity type, a silicon nitride film 26, and an alumina film 27 is formed. D forming island-like regions 28 and 29 using an etching method or a physical etching method
oHere, the source and drain regions of the MOS transistor are formed in the base body 21 directly below the island region 28, and the island region 2
The polycrystalline silicon film 25 portion 9 is used as the first layer wiring.

Next, the silicon semiconductor substrate 21 and the polycrystalline silicon film 25
The exposed portions of the polycrystalline silicon film 25 are oxidized using a thermal oxidation method to form a silicon oxide film 30, and the portions where the polycrystalline silicon film 25 and the silicon semiconductor substrate 21 are in contact with each other are oxidized using the thermal oxidation method. Diffusion of impurities
After forming the source and drain regions 31 of the OS transistor, a second polycrystalline silicon film 32 and 33 is deposited over the entire surface by vapor deposition, but as shown in the figure, this polycrystalline silicon film does not adhere to the side surfaces 34. Or, even if Fo is deposited, the film thickness will be extremely thin. After this, if the alumina film 27 is removed using an etching solution for the alumina film 27 (for example, caustic soda) that does not attack the silicon nitride film 26 and the silicon oxide film 30, the alumina film 27 will be removed. Second polycrystalline silicon film 3 formed on alumina film 27
2 is removed.

Furthermore, the second polycrystalline silicon film 33 remaining without being removed
G is oxidized using a thermal oxidation method to form a silicon oxide film 34.

In this state, as shown in G, a smooth surface with no irregularities is formed in which silicon nitride films 26 and silicon oxide films 34 are alternately arranged, and polycrystalline silicon films 25, 34 are formed under the respective oxide films 26, 34. The source and drain regions formed in step 33 and a region used for wiring are formed.

After that, the silicon nitride film 26 and the silicon oxide film 3 described above are
3 selectively with an etching solution that does not attack each other (for example, hot phosphoric acid for the silicon nitride film 26 and hydrofluoric acid for the silicon oxide film 34),
Contact holes 35 are formed in a self-aligned manner.

That is, the oxide film 341. The contact window is determined by the width of the nitride film 26 and is not dependent on the photoresist used for this etching.

Next, the metal film 36 is selectively wired to complete the MOS type integrated circuit device. Figure 2 I is a top view of the completed sectional view R, and ■ is the n-mm of H.
The cutting lines are shown, and the same numbers as H are given the same numbers.

In FIG. 2I, the outer part shows a contact hole 35 between the metal film 36 formed on the silicon oxide film 34 or the silicon nitride film 26 and the polycrystalline silicon film 25 or 31.

40 to 43 indicate MOS transistor formation regions.

The present invention is not limited to the materials used in the explanation of FIG. 2; for example, instead of the polycrystalline silicon films 25 and 33, a film of a high melting point metal such as W, Ta, Mo, or Ti containing impurities may be formed. Instead of the heated silicon oxide films 30 and 34, an insulating film may be formed on the surface of the metal film by anodic oxidation.

Further, instead of the alumina film 27, it is also possible to use a high melting point metal such as W2MO.

In addition, in Fig. 2, the source of the MOS) transistor,
Although the polycrystalline silicon film 25 containing impurities was used to form the drain region 31, a Schottky barrier diode between a metal film such as Mo, W+TitAu, or AA and the silicon semiconductor substrate was formed to form the source of the MOS transistor. It is also possible to use it as a drain.

By using the present invention, as is clear from FIG. 2 (2), most of the main plane of the silicon semiconductor substrate is used as a MOS transistor or wiring area, and the chip area is effectively utilized.

In addition, the insulation between polycrystalline silicon films is extremely thin (100
(0 to 5,000 people) It is made of silicon oxide film and can be significantly higher in density than the conventional 5μ.

Furthermore, as is clear from FIG. 2H, since the metal film used for the wiring is formed on a surface with no unevenness, there is no disconnection of the metal film at the uneven portions that exist in the past, and the manufacturing yield is improved. Combined with the reduction in chip area, it is possible to significantly reduce manufacturing costs.

[Brief explanation of drawings]

1A to 1E are cross-sectional views of the manufacturing process of a conventional MOS type integrated circuit device, and FIGS.
FIG. 2 (2) is a cross-sectional view of the manufacturing process of an OS type semiconductor device, and FIG. 21... Silicon semiconductor substrate, 24.30.3
4... Silicon oxide film, 26... Silicon nitride film, 25, 32, 33... Polycrystalline silicon film, 27... Alumina film, 36...・・・・・・
・Metal film.

Claims (1)

[Claims] 1. A first electrode wiring on the whole surface of the silicon semiconductor substrate,
A step of forming a second insulating film by patterning both the first insulating film and the lift-off layer and oxidizing the exposed base and the side surface of the first electrode wiring; The layer that will become the second electrode wiring is selectively lifted off using the lift-off layer.
forming an electrode wiring adjacent to the first electrode wiring; and forming a third insulating film having etching selectivity with respect to the first insulating film by oxidizing the second electrode wiring. a step of forming the first electrode wiring on the second electrode wiring; Third
forming a contact hole in a self-aligned manner in the first and second electrode wirings using the etching selectivity of the insulating film.