JPS59130445A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To form a semiconductor integrated circuit device of multilayer wiring without disconnections due to stepwise differences by shape-forming a wiring layer on an Si nitride film, and introducing an impurity to the exposed Si nitride film. CONSTITUTION:After providing an oxide film on the surface of a P type Si substrate 11, a field oxide film 12 is left by a photoetching method. Next, after forming a gate oxide film 13, an Si layer 14 is formed, which layer is so etched as to leave a gate electrode part, wiring part 14, etc. Then, the gate oxide film 13 is removed, thereafter an N type region 15 is formed in the substrate 11, the Si layer 14 is changed into an N type, and the field oxide film 2 into a phosphorus glass by diffusing phosphorus into the substrate 11 and the Si layer 14. An Si oxide film 16 is provided again, and the Si nitride film 17 is adhered thereon. An Si layer 18 is formed, and a pattern is formed by etching this layer 18. Phosphorus is diffused into the Si layer 18 and the Si nitride film 17. Then an Si oxide film 20 is provided, a hole is bored through this film, and an Al wiring 21 is provided, thereby a three layer N-channel MOS type integrated circuit device is completed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor integrated circuit device, and particularly to a method of forming multilayer wiring.

In semiconductor integrated circuit devices, there is a great need to improve the degree of integration, and one method for meeting this demand is multilayer wiring. Although wiring usually has a two-layer structure of a polycrystalline silicon layer and an aluminum layer, multilayer wiring can be realized by forming one or more polycrystalline silicon layers between these two layers.

FIG. 1 is a cross-sectional view of an example of a conventional semiconductor integrated circuit device with multilayer wiring.

After providing a field oxide film 2 on a P-type silicon substrate 1,
A hole is opened and a gate oxide film 3 is provided. After a first polycrystalline silicon layer 4 is provided on the oxide films 2 and 3, a region to become an active region is opened and phosphorus is diffused to form an N-type region 5. A silicon oxide film 6 is formed by oxidation, a second polycrystalline silicon layer is provided thereon, and a pattern of a second polycrystalline silicon layer 7 is formed by selectively etching by photolithography. Since a hydrofluoric acid-nitric acid solution is normally used for this selective etching, the silicon oxide film 6 is also attacked at the same time, and the silicon oxide film under the edge of the second polycrystalline silicon layer 7 is removed.

If manufacturing is continued with such an undercut, the aluminum wiring may break due to the step, the dielectric strength voltage between the silicon substrate 1 and the polycrystalline silicon 7 may drop at the undercut, or the dielectric strength may drop significantly. If the temperature is too high, dielectric breakdown may occur at this point, resulting in a short circuit. In addition, the field silicon oxide film 2 is also attacked, and the original field oxide film 2 is
There is a drawback that a so-called parasitic MO8 field effect transistor is generated in which a leakage current flows between the adjacent diffusion layers 5 due to the zero reduction. For this purpose, a method of arranging a silicon nitride film at the peripheral portion may be considered, but in this case, a recess is formed under the end of the silicon nitride film, which may cause a disconnection in multilayer wiring. Moreover, an extra patterning step is required to provide this silicon nitride film in the peripheral area.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit device with multilayer wiring, which eliminates the above-mentioned drawbacks and is free from disconnections due to steps.

A feature of the present invention is that in a method for manufacturing a semiconductor integrated circuit device with multilayer wiring formed by laminating a lower wiring layer via an insulating material layer, a silicon oxide film and a silicon nitride film are laminated on the lower wiring layer, A method of manufacturing a semiconductor integrated circuit device includes forming an upper wiring layer on the silicon nitride film, and introducing impurities into the exposed portion of the silicon nitride film to change the quality of the film.

In the present invention, since no undesired recesses are formed in any part of the insulating layer such as a silicon oxide film, the wiring layout can be freely set.

Furthermore, the manufacturing process can be shortened because the selective etching process for the silicon nitride film or the like can be omitted. Furthermore, each part at the point where the multilayer wiring intersects each other is at a constant interval and no unevenness occurs, resulting in a preferable multilayer structure.Also, since each part is at a constant interval in this way, the capacitor between each wiring is a constant value. This makes it easier to set 9IC to a predetermined value.

Next, the present invention will be explained by examples.

2 to 6 are process cross-sectional views when the method of the present invention is applied to a three-layer N-channel silicon gate MO8 type integrated circuit device.

After forming an oxide film with a thickness of approximately 1 μm on the surface of the P-type silicon substrate 11, a field oxide film 12 is left in areas other than the active regions of the b transistors etc. by ordinary photolithography (Fig. 2). .

Subsequently, after forming a gate oxide film 13 with a thickness of approximately 1,000 mm, a first polycrystalline silicon layer with a thickness of approximately 50,000 mm is formed by vapor phase growth, etc., and the gate electrode portion, wiring portion 14, etc. of the transistor are formed. The first polycrystalline silicon layer is etched so as to remain intact (FIG. 3).

Subsequently, after etching away the gate oxide film 13 in the portion of the substrate 11 where the diffusion layer is to be formed, phosphorus is diffused into the substrate 11 and the first polycrystalline silicon layer 14 at 1000°C to form the substrate 1.
An N-type region 15 is formed in the polycrystalline silicon layer 1.
4 is changed to N type, and the field oxide film 12 is changed to phosphorus glass. A silicon oxide film 16 with a thickness of about 5,000 mm is formed again by thermal oxidation, and a silicon nitride film 17 with a thickness of several hundreds of mm is deposited thereon as a protection (FIG. 4).

Next, a second polycrystalline silicon layer 18 having a thickness of about 5000 nm is formed, and a pattern is formed by etching this layer 18 with a hydrofluoric acid-nitric acid solution using photolithography. Since the silicon nitride film 17 is not attacked by the hydrofluoric acid-nitric acid based etching solution, it protects the underlying silicon oxide film 16. Therefore, an undercut as shown in FIG. 1 does not occur. Subsequently, a second polycrystalline silicon layer 18 and a silicon nitride film 17 are formed.
Diffuse phosphorus into. Silicon nitride film 17 by phosphorus diffusion
The exposed portion changes into phosphorus glass 19. Therefore, the step of removing the silicon nitride film 17 is unnecessary (FIG. 5).

A silicon oxide film 20 is provided again by thermal oxidation.

Since the silicon nitride film is altered in quality by introducing impurities in this way, it becomes possible to form thermally oxidized silicon. A 1ffi#N channel MO8 type integrated circuit device is completed by making holes by photolithography and providing aluminum wiring 21 (FIG. 6).

In the above embodiment, polycrystalline silicon is used as the metal wiring layer and silicon nitride is used as the protective film. It can also be applied. For example, when tantalum is used as the metal, the method of the present invention can be carried out using silicon nitride as the protective film.

According to the present invention, disconnections and short circuits due to steps, or parasitic M
The effect is great because a semiconductor product circuit with multilayer wiring without the occurrence of O8FET can be obtained.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of an example of a conventional semiconductor integrated circuit device with multilayer wiring, and FIGS. 2 to 6 show examples of the case where the method of the present invention is applied to a three-layer N-channel silicon gate (MO8) type integrated circuit device. It is a process sectional view. 1.11°°°°°°P-type silicon substrate, 2.12...
...Field oxide film, 3.13...Gate oxide film, 4.14.°°.°.First polycrystalline silicon film, 5,15...N-type region , 6.16...
...Silicon oxide film, 7°°゛°°°Second polycrystalline silicon film, 8=°°°...Silicon oxide film, 9.21--
--...Aluminum wiring 1.17...Silicon nitride film, 18...°/°°second polycrystalline silicon film,
19...Phosphorus glass, 20...Silicon oxide film. )) Heat / Times 1/ Figure 3 %4

Claims (1)

[Claims] In a method for manufacturing a semiconductor integrated circuit device with multilayer wiring formed by laminating a lower wiring layer and an upper wiring layer with an insulator layer in between, a silicon oxide film and a silicon nitride film are laminated on the lower wiring layer, and the silicon A method for manufacturing a semiconductor integrated circuit device, comprising forming an upper wiring layer on a silicon nitride film, and introducing impurities into the exposed portion of the silicon nitride film to alter the quality of the film. .