JPS62156857A - Manufacture of semiconductor device containing memory element - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device in which a transistor of double-layer polycrystalline silicon structure with a floating gate is used as a memory element easily and with high yield by etching 1st polycrystalline silicon layer and 2nd polycrystalline silicon layer separately. CONSTITUTION:After an oxide film 38 is formed on 1st polycrystalline silicon layer 36, 2nd polycrystalline silicon layer 40 is formed and resist patterns 42a and 42b are formed by photolithography and the 2nd polycrystalline silicon layer 40 is etched. Then the oxide film 38 and 1st polycrystalline silicon layer 36 are etched to form the gate electrode 44 of an EP-ROM (a). Then, after new resist patterns 46a-46c are formed, the 2nd polycrystalline silicon layer 40 in a peripheral transistor part (b) is etched to form the gate electrodes 48a and 48b of the peripheral transistor part (b).

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method of manufacturing a semiconductor device including a memory transistor having a two-layer polysilicon structure, such as an EPROM or an EEPROM (7).

(Prior art) When creating a memory transistor and a peripheral transistor with a two-layer polysilicon structure on the same chip, the gate electrode of the peripheral transistor is formed using the first polysilicon layer, the second polysilicon layer, or the polysilicon layer of both layers. It can be formed from a silicon layer.

FIG. 2 shows an example in which the gate electrode of the peripheral transistor is formed using the same two polysilicon layers as the EPROM memory transistor.

a is an EPROM, and b is a peripheral transistor.

2 is a silicon substrate, 4 is a field oxide film, 6°8 is a gate oxide film, 10 is a floating goo 1-electrode (first
12 is a control I-roll gate electrode (second layer polysilicon), 14 is an interlayer oxide film, 16 is a gate electrode of a peripheral transistor, 18 is an insulating layer, 20.
22 is wiring.

This method requires a connection between the first polysilicon layer and the second polysilicon layer in the gate electrode 16 of one peripheral transistor, so a contact layer with a fine pattern is required. Also.

The channel length of the peripheral transistor and the channel length of the EPROM cannot be controlled separately depending on the process conditions.Furthermore, since the gate electrode 16 of the peripheral transistor also has a two-layer polysilicon structure, the step difference becomes large and causes disconnection of the metal wiring. becomes.

FIG. 3 shows an example in which the second polysilicon layer is used for the gate electrode of one peripheral transistor, and the gate electrode and the peripheral transistor are simultaneously formed by one lithography.

In this method, when the second polysilicon layer, interlayer oxide film, and first polysilicon layer are etched to form the gate electrode portion of the EPROM, the silicon substrate 2 around the gate electrode 12a of the peripheral transistor is also etched. It is etched and holes 24 are left.

In FIG. 4, the gate electrode 10a of the peripheral transistor is
An example in which the second layer is formed using a polysilicon layer will be shown.

In this method, when etching the first polysilicon layer to form the gate electrode of the EPROM, it is necessary to cover the peripheral transistor portion with resist 28. Even if patterning of the resist 28 fails, E
Because there is a resist pattern 26 for the FROM gate electrode.

This pattern forming process of the resist 28 cannot be redone. Furthermore, in order to avoid increasing the resistance of the gate electrode and wiring of one peripheral transistor, it is necessary to make the first polysilicon layer thick. Therefore, the height of the gate electrode of the EPROM becomes high and the step difference becomes large.

(Objective) An object of the present invention is to provide a method for easily manufacturing a semiconductor device using a two-layer polysilicon transistor with a floating gate as a memory element with good controllability (high yield). It is something to do.

(Structure) In the present invention, after gate oxidation, a first polysilicon layer is formed, this first polysilicon layer is patterned to form a floating electrode of a memory transistor, and the memory transistor is formed by oxidation. An interlayer oxide film and a gate oxide film of the peripheral transistor are formed, a second polysilicon layer is formed, and this second polysilicon layer is patterned to form the control gate electrode of the memory transistor and the gate electrode of the peripheral transistor. A method for forming a memory transistor having a two-layer polysilicon structure with a peripheral transistor, the method comprising the step of forming a second polysilicon structure for forming a control gate electrode of the memory transistor.
This is a method for manufacturing a semiconductor device in which an etching process for the second polysilicon layer and an etching process for the second polysilicon layer for forming a gate electrode of a peripheral transistor are separate processes.

Examples will be specifically described below with reference to FIGS. 1(A) to 1(D).

Although this embodiment is exemplified for a CMO5 type, it can also be applied to an NMO8 type, a PMO5 type, or a Bi-MOS type (combined bipolar transistor and MOS transistor).

FIG. 1(A) shows that an N well 31, a field oxide film 32, and a gate oxide film 34 are formed on a P-type substrate 30, a first layer polysilicon layer 36 is formed and patterned, and the first layer polysilicon layer 36 is formed and patterned. An oxide film 38 is formed on the layer 36, a second polysilicon layer 40 is formed, resist patterns 42a and 42b are formed by photolithography, and the second polysilicon layer 40 is etched.

At this time, the peripheral transistor portion is covered with resist pattern 4.
Covered by 2b.

Subsequently, as shown in FIG. 1(B), oxidized nMo38
Etching and 1st F! The J-th polysilicon layer 36 is etched. This completes the gate electrode 44 of EPROMa. At this time, since the first peripheral transistor part is covered with the resist pattern 42b, the EPROM
A second polysilicon layer 40 for forming a gate electrode of
It is not affected by the three etching steps of etching, etching of the oxide film 38, and etching of the first polysilicon layer 36.

Next, as shown in FIG. 1(C), the resist patterns 42a and 42b are removed and a new resist pattern 4 is created.
6a, 4, 6b, and 46c are formed, and the second polysilicon layer 40 of the peripheral transistor portion is etched.

As a result, the gate electrode 48a of the peripheral transistor section,
48b is completed.

At this time, since the EPROM section a is covered with the resist pattern 46C, it is not affected by etching.

After removing the resist patterns 46a, 46b, and 46c, as shown in FIG. 1(D), an insulating film 50 is formed by a conventional method, contact holes are formed, and a metal wiring layer 52 is formed. After that, a pancivation film (the path shown) is formed.

In FIGS. 1B and 1C, an overlapping portion (offset) A is provided on the field oxide film 32 between the etching region of the EPROM section a and the etching region of the peripheral transistor section. The width of this offset A is 0.5 to 5μ
A value of about m is appropriate.

If this offset A does not exist, the polysilicon layer will remain when the etched region of the EPROM section a and the etched region of the peripheral transistor section do not overlap due to misalignment.

If this offset part is not on the field oxide film but on the gate oxide film, it will be etched during etching of the second polysilicon layer → etching of the interlayer insulating film → etching of the first polysilicon layer → etching of the peripheral transistor part. Deep grooves are formed in the wafer, resulting in a significant decrease in yield.

Therefore, it is necessary to provide the offset portion on the field oxide film.

(Effects) In the method of the present invention, the etching process of the second polysilicon layer for forming the control gate electrode of the memory transistor and the etching process of the second polysilicon layer for forming the gate electrode of the peripheral transistor are performed. Since the process is a separate process, the following effects can be achieved.

(1) The length of the gate electrode of the memory transistor and the length of the gate electrode of the peripheral transistor can be controlled separately.

(2) The phosphorography process can be redone.

(3) It is possible to form an element with a relatively small step difference,
Yield improves.

[Brief explanation of drawings]

1(A) to 1(D) are cross-sectional views of an apparatus according to an embodiment of the present invention, showing the steps in the order of steps, and FIGS. 2-4 are cross-sectional views of the apparatus showing a conventional manufacturing method. 34:...Gate oxide film, 36...First layer polysilicon layer, 38...
Interlayer oxide film, 40...Second layer polysilicon layer.

Claims (3)

[Claims] (1) After gate oxidation, form a first polysilicon layer, pattern this first polysilicon layer to form a floating gate electrode of the memory transistor, and oxidize the interlayer oxide film of the memory transistor and the surrounding area. The method includes forming a gate oxide film of the transistor, forming a second polysilicon layer, and patterning the second polysilicon layer to form a control gate electrode of the memory transistor and a gate electrode of the peripheral transistor. , a method for forming a peripheral transistor and a memory transistor having a two-layer polysilicon structure, comprising etching the second polysilicon layer for forming a control gate electrode of the memory transistor, and forming a gate electrode of the peripheral transistor. A method for manufacturing a semiconductor device, characterized in that the step of etching the second polysilicon layer is a separate step. (2) In etching the second polysilicon layer,
Claim 1, wherein a resist pattern is formed so that an etched region for forming a control gate electrode of a memory transistor and an etched region for forming a gate electrode of a peripheral transistor partially overlap on the field oxide film. A method for manufacturing a semiconductor device. (3) The method of manufacturing a semiconductor device according to claim 2, wherein the control gate electrode of the memory transistor and the gate electrode of the peripheral transistor are connected by metal wiring.