JPH0210771A - Semiconductor device - Google Patents

Abstract

PURPOSE:To seek to increase contact resistance value by constituting a connection hole out of the recess of a layer and through holes of an insulating film. CONSTITUTION:A field oxide silicon film 2 is formed on a semiconductor substrate 1 by both technologies of chemical etching and thermal oxidation, and a gate oxide film 4 and a gate polycrystalline silicon film 5 are patterned by both technologies of photoengraving and chemical etching. With the film 5 as a mask, the ions of impurity of the opposite conductivity type to the substrate 1 are implanted and a source/ drain diffusion region 3 is formed using a heat diffusion technology. The substrate 1 upper layer part of the region 3 becomes a channel region. Further, by thermal oxidation technology, an interlayer insulating film 6 is formed on the substrate 1, and by both technologies of photoengraving and chemically etched through holes 7a are provided at a part above the region 3. Next, etching treatment high in etching selectively is done to the region 3 so as to form a recess 7b which constitutes connection hole 7 together with a hole 7a. A metallic layer is accumulated on the whole face and a metallic wiring layer 8 is formed, which is connected electrically with the region 3 through the hole 7. By doing it this way, the increase of a contact resistance value can be restrained in spite of micronization of the device.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device having connection holes.

(Prior Art) FIG. 2 is a cross-sectional view showing a conventional semiconductor device having connection holes disclosed in, for example, Japanese Patent Publication No. 62-52474. In the figure, reference numeral 1 denotes a semiconductor substrate made of, for example, a silicon substrate, and source/drain diffusion regions 3 are formed between field silicon oxides 1112 for element isolation in the upper layer of the semiconductor substrate 1. Gate oxide silicon on semiconductor substrate 1 between source and drain diffusion regions 3! 1
A gate polycrystalline silicon film 5 is formed on the gate oxide silicon substrate. Furthermore, field silicon oxide film 2 and gate polycrystalline silicon g
An interlayer insulating film 6 for electrically protecting an element region on the semiconductor substrate 1 is formed on the semiconductor substrate 1 including the semiconductor substrate 15 . This interlayer insulating film 6 has contact holes 7 formed in layers on a portion of the source/drain diffusion region 3 .

Then, a metal wiring layer 8 is formed in a predetermined area on this interlayer insulating film 6.
is provided, and this metal wiring 1I18 is electrically connected to the source/drain diffusion region 3 via the contact hole 7.

A semiconductor device having the connection hole 7 described above is manufactured as shown below. First, photolithography technology is applied on the semiconductor substrate 1.
A field silicon oxide film 2 functioning as an element isolation region is formed using chemical etching technology and thermal oxidation technology.

Then, a silicon oxide film is formed on the semiconductor substrate 1, and further,
A polycrystalline silicon film is formed on this silicon oxide ridge, and gate silicon oxide film 4 and gate polycrystalline silicon film 5 are patterned using photolithography and chemical etching.

Using this gate polycrystalline silicon film 5 as a mask, an impurity of the opposite conductivity type to that of the semiconductor substrate 1 is implanted using ion implantation technology, and then diffused using thermal diffusion technology to form the impurity as shown in the figure. , forming source/drain diffusion regions 3. The upper layer of the semiconductor substrate 1 between the source/drain diffusion regions 3 becomes a channel region.

Then, gate polycrystalline silicon film 5 and field oxide silicon F! An interlayer insulating film 6 is formed on the semiconductor substrate 1 including the semiconductor substrate 2 using thermal oxidation technology, and a contact hole 7 is formed in a part above the source/drain diffusion region 3 using photolithography technology and chemical etching technology.

As a chemical etching technique for forming the connection hole 7, an etching process is performed in which the etching rates for the interlayer insulating film 6 and the semiconductor substrate 1 are different (approximately 10:1) and the etching selectivity for the interlayer insulating film 6 is high. Specifically, CH
Examples include dry etching using F3+02 gas or wet etching using diluted HF solution. For this reason, when the connection hole 7 is opened, the source and drain diffusion regions 3
However, it will not be etched by more than 0.1 μm.

After opening connection hole 7, a metal layer is deposited on the entire surface and patterned using photolithography and chemical etching technology to form metal wiring M8.
form. At this time, metal wiring layer 8 is electrically connected to source train diffusion region 3 through connection hole 7 .

When a predetermined potential is applied from the metal wiring layer 8 to the source/drain diffusion region 3 of the semiconductor device manufactured in this way in an on state (a predetermined potential is applied to the gate polycrystalline silicon film 5), the metal wiring layer 8 A current flows between the source and drain diffusion regions 3 under restrictions such as the resistance value, the contact resistance value between the metal wiring layer 8 and the source/train diffusion region 3, and the resistance value in the channel region in the on state.

[Problem to be solved by the invention]

A conventional semiconductor device having a connection hole is constructed as described above, and as miniaturization progresses, the opening area of the connection hole 7 naturally becomes smaller, and the contact resistance value between the metal wiring 148 and the source/drain diffusion region 3 decreases. becomes larger. As a result, there was a problem in that a sufficient current could not flow between the source and drain diffusion regions 3 in the on state.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor device having contact holes whose contact resistance value does not increase even with miniaturization.

[Means to solve the problem]

A semiconductor device according to the present invention includes a layer having a recess, and is formed on the semiconductor substrate, and has a through hole above the recess of the layer, and the through hole and the recess form a connection hole to the layer. and a conductive layer formed on the insulating film and electrically connected to the layer through the connection hole.

[Effect]

Since the connection hole in this invention is constituted by a recess in the layer and a through hole in the insulating film, the contact area between the conductor layer and the layer is the surface area of the opening of the connection hole plus the surface area of the side surface of the recess. The value is taken into account.

(Embodiment) FIG. 1 is a sectional view showing a semiconductor device having a contact hole, which is an embodiment of the present invention. As shown in the figure, the connection hole 7 is composed of a through hole 7a provided in the insulation m6 similar to the conventional one, and a recess 7b provided in the upper layer of the source/drain diffusion region 3 below the through hole 7a. Ru. The other configurations are the same as the conventional one, so explanations will be omitted.

A semiconductor device having the above-mentioned connection holes 7 (7a, 7b) is manufactured as shown below.

First, a field silicon oxide film 2 functioning as an element isolation region is formed on a semiconductor substrate 1 using photolithography, chemical etching, and thermal oxidation.

Then, a silicon oxide film is formed on the semiconductor substrate 1, and further,
A polycrystalline silicon film is formed on this oxide film, and gate oxide film 4 and gate polycrystalline silicon film 5 are patterned using photolithography and chemical etching.

Then, using this gate polycrystalline silicon 1115 as a mask, impurities of the opposite conductivity type to the semiconductor substrate 1 are implanted using ion implantation technology, and then diffused using thermal diffusion technology, as shown in the figure. Diffusion depth 0.35μ
A source/drain diffusion region 3 having a thickness of approximately m is formed. The upper layer of the semiconductor substrate 1 between the source/drain diffusion regions 3 becomes a channel region.

Then, an interlayer insulation IPJ6 is formed on the semiconductor substrate 1 including the gate polycrystalline silicon I [i5 and the field silicon oxide yA2 using thermal oxidation technology, and on the source/drain region 3 using photolithography technology and chemical etching technology. A through hole 7a is provided in a part of the hole 7a.

As a chemical etching technique for forming the through hole 7a, an etching process with high etching selectivity for the interlayer insulating film 6, which has a different etching rate (approximately 10:1) for the interlayer insulating film 116 and the semiconductor substrate 1, is performed. Specifically, dry etching using CHF3+02 gas or wet etching using a diluted HF solution may be used. Therefore, the source/drain diffusion region 3 is not etched by more than 0.1 μm when the connection hole 7a is opened.

After the through hole 7a is formed, the photoresist used for the through hole 7a is used as it is, and an etching process with high etching selectivity for the source/drain diffusion region 3 is performed. Specifically, dry etching is performed using CF4 gas. As a result, a recess 7b having a depth of about 0.61 to 0.2 μm, which is shallower than the diffusion depth of the source/drain diffusion region 3, is formed under the through hole 7a. The connection hole 7 is constituted by the recess 7b and the through hole 7a.

After forming the recess 7b, a metal layer is deposited on the entire surface and patterned using photolithography and chemical etching to form a metal wiring layer 8.
form. At this time, metal wiring layer 8 is electrically connected to source/drain diffusion region 3 through connection hole 7 .

With this configuration, the metal wiring 118 and the source
The contact area with the drain diffusion region 3 is the surface area of the recess 7b. That is, in addition to the bottom area of the recess 7b (opening surface v4 of the connection hole 7), the surface area of the side surface is taken into consideration. For this reason,
Even if the opening area of the connection hole 7 is 1.0 μm or less, the metal wiring layer 8
A sufficient contact area can be maintained between the source/drain diffusion region 3 and the source/drain diffusion region 3. As a result, an increase in the contact resistance value between the metal wiring layer 8 and the source/drain diffusion region 3 can be suppressed.

In this embodiment, when forming the recess 7b, the depth of the recess 7b was set to be approximately 0.1 to 0.2 μm shallower than the diffusion depth of the source/drain diffusion region 3, but it was set to be approximately 0.5 μm or more deeper than the diffusion depth. The recess 7b may be formed to have a depth of . However, in this case, in order to avoid electrical connection between the metal wiring layer 8 and the semiconductor substrate 1, it is necessary to further form an impurity diffusion region opposite to the semiconductor substrate 1 around the recess 7b.

Furthermore, in this example, the photoresist used when forming the through hole 7a was also used as a mask when forming the recess 7b.
Another photoresist may be used as a mask. It is also conceivable to perform an etching process using the interlayer insulating film 6 as a mask without using a photoresist when forming the recess 7b.

Moreover, the interlayer insulating film 6. If the etching process has good etching characteristics for both the source and drain diffusion regions 3, the through hole 7a and the recess 7b can be formed at the same time by performing the etching process twice.

Further, in this embodiment, the metal wiring layer 8 is used as the wiring layer electrically connected to the source/drain diffusion region 3, but other conductive layers may be used as the wiring layer.

〔Effect of the invention〕

As explained above, according to the present invention, the contact hole is formed by the recess in the layer and the through hole in the insulating film, so that the contact area between the layer in which the recess is formed and the conductor layer is reduced by the side surface of the recess. Since the surface area can be increased, an increase in contact resistance value can be suppressed even when the device is miniaturized.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a semiconductor device having connection holes according to an embodiment of the present invention, and FIG. 2 is a sectional view showing a conventional semiconductor device having connection holes. In the figure, 1 is a semiconductor substrate, 3 is a source/drain diffusion region, 6 is an interlayer insulating film, 7 is a connection hole, 7a is a through hole,
7b is a recess, and 8 is a metal wiring layer. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) a layer having a recess; an insulating film formed on the semiconductor substrate and having a through hole above the recess of the layer; the through hole and the recess forming a connection hole to the layer; , formed on the insulating film,
A semiconductor device comprising a conductor layer electrically connected to the layer through the connection hole.