JPS60196936A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make high integration and acceleration of LSI feasible by a method wherein grooves are formed into a semiconductor substrate and after filling the grooves with organic solvent containing impurity or silicon dioxide, shallow impurity diffusion layer is formed on the bottom or sides of grooves by means of short time annealing process. CONSTITUTION:A gate film 14, a gate electrode 13 and a source.drain diffusion layer 12 formed by ion implantation are formed on an Si semiconductor substrate 11. After depositing an interlayer insulating film 15, contact holes are made for patterning photoresist 16 to form grooves in the hole regions. After coating the grooves and the photoresit 16 with organic solvent 17 containing impurity for diffusion to fill the contact holes and the grooves of semiconductor substrate, they are annealed for a short time using a halogen lamp. Further after removing the organic solvent 17 and the resist 16, an A wirings 19 are formed to fill the contact holes and the grooves of semiconductor substrate with Al. Through these procedures, a shallow diffusion layer may be formed on the bottom and side regions of grooves of Si semiconductor substrate in the contact hole regions while the grooves are filled with Al.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device that enables higher integration and higher speed of LSI. It is particularly effective in LSIs that highly integrate MO5FETs having low contact resistance and low diffusion layers. be.

Conventionally, impurity diffusion layers of semiconductor substrates have been formed by ion implantation or thermal diffusion. However, ion implantation method! In a trench formed in a semiconductor substrate, impurity ions cannot be implanted into the side surfaces of the trench. In addition, with the thermal diffusion method, it is possible to diffuse impurities into the bottom and one side area of the trench, but since the thermal diffusion method requires heat treatment at high temperatures and for a long time, the impurity diffusion region expands, making it difficult to diffuse the impurity into the source area of miniaturized MOSFETs. It is difficult to use it for drain formation. Therefore, in conventional semiconductor device manufacturing methods, grooves are created in the semiconductor substrate,
It was impossible to form a shallow impurity diffusion layer in the bottom and side regions of the trench.

In the present invention, a groove is created in a semiconductor substrate, and after filling the groove with an organic solvent or silicon dioxide containing a diffusion impurity,
This is a method for manufacturing a semiconductor device, characterized in that a shallow impurity diffusion layer is formed at the bottom of the trench and the [111 opening] by short-time annealing. In particular, miniaturized MOS'F with low resistance source/drain diffusion layers and low contact resistance.
It is most suitable for the manufacturing method of LSI made of KT.

This will be explained below using examples.

FIG. 1 shows a conventional ion implantation method for forming an impurity diffusion layer in a semiconductor substrate. A groove is formed in the semiconductor substrate 1 using the resist 2 as a mask. Subsequently, impurity ions 3 are implanted using an ion implantation device. In the ion implantation method, since the impurity ions 3 advance straight, a diffusion layer is formed only on the groove bottom surface 4, and no diffusion layer is formed on the side surfaces of the groove. In addition, the thermal diffusion method can form an impurity diffusion layer on the bottom and side surfaces of the groove, but since the thermal diffusion method requires heat treatment at high temperatures and for a long time, the impurity ions spread in the depth direction and the lateral direction, resulting in a shallow diffusion layer. cannot be formed, and the source of the miniaturized MOSFET
Difficult to apply to drain diffusion layer formation.

2 to 8 show a method of manufacturing a semiconductor device according to the present invention. In FIG. 2, after forming a SiO□ film 7 on a semiconductor substrate 5, a groove is dug, an organic solvent containing a diffusion impurity and silicon oxide is applied to the groove region, and the groove is filled with the organic solvent 6. After that, short-time high-temperature annealing (at least 900°C and within 10 seconds) is performed using a halogen lamp.
Shallow diffusion layers 8 are formed on the bottom and side surfaces of the grooves formed in the semiconductor substrate 5 (Fig. 3). In the present invention, since a liquid organic solvent with low viscosity is used, The groove can be completely filled. Therefore, the diffusion impurities contained in the organic solvent can be uniformly formed into a diffusion layer on the bottom and side surfaces of the groove by heat treatment. In addition, in the present invention, the heat treatment can be performed for a short time. Since this is carried out, the spread of impurity ions is small.As described above, by using the method of manufacturing a semiconductor device according to the present invention, a shallow diffusion layer can be formed in the bottom and side regions of a trench formed in a semiconductor substrate.

4 to 8, the present invention is applied to manufacturing a miniaturized MOSFET.

In conventional MOI9FETs, as LSIs become more highly integrated, the source/drain diffusion layers become shallower, and the contact holes connecting the AL wiring and the source/drain diffusion layers become smaller. For this reason, in the diffusion layer formed by the conventional ion implantation method, the resistance of the P-type diffusion layer with a junction depth of 0.3μm or less and the resistance of the N-type diffusion layer with a junction depth of 0.2μm or less. The resistance will be greater than 50Ω/mouth. Also, the contact resistance between AL and 81 semiconductor substrate diffusion layer is 100Ω when the contact hole is smaller than 1 μm.
exceed. Therefore, in the conventional manufacturing method, MO8FF
As LSIs made of iT progress in miniaturization, diffusion resistance and contact resistance increase, which prevents high-speed LSIs, and MOSF
This placed a limit on the high integration of ET. In the present invention,
By forming a shallow diffusion layer on the bottom and side surfaces of a trench formed in a semiconductor substrate in a contact hole region connecting a metal substrate and a semiconductor substrate diffusion layer separated by an interlayer insulating film,
Reduces source/drain diffusion layer and contact resistance. Hereinafter, a method for manufacturing a semiconductor device according to the present invention will be explained with reference to FIGS. 4 to 8.

In FIG. 4, the S1 conductor board 11 has a game) [41
4, Ga)'4fdfi1x and source/drain diffusion layers 12 formed by ion implantation.

After accumulating the interlayer insulating film 15, contact holes are formed by patterning the photoresist 16, and then S1! A groove is formed in the contact hole region of the conductive substrate (FIG. 5).

Subsequently, an organic solvent 17 containing diffusion impurities is applied to fill the contact holes and the grooves of the semiconductor substrate, and then short-time annealing is performed using a halogen lamp (sixth step).
figure). In FIG. 7, a shallow diffusion layer 18 is formed on the bottom and side surfaces of the trench in the S1 semiconductor substrate by this annealing. After removing the organic solvent 17 and the resist 16, 'A
An L wiring 19 is formed, and the contact hole and the groove of the semiconductor substrate are filled with AL. FIG. 8 is a cross-sectional view of MO8Fl'[' produced by the method of the present invention. According to the present invention, shallow diffusion layers are formed in the bottom and side regions of the groove of the semiconductor substrate 81 in the contact hole region, and the groove is filled with AL. Therefore, the resistance of the source/drain diffusion layer of MO5FIT becomes extremely small due to the embedded AL. In addition, the contact area between the AL wiring 19 and the diffusion layer 12.18 is small even if the contact hole is miniaturized to 1 μm.
If the depth of the groove is 1μ bait, there will be 5μ2. Therefore, by digging the trench deeply, it is possible to achieve a contact resistance of 20 Ω/region or less.As explained above, the method for manufacturing a semiconductor device according to the present invention uses a low-resistance source/drain diffusion layer and a microstructure with low contact resistance. This makes it possible to manufacture high-speed, highly integrated LSIs made of highly integrated MOSFETs.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a conventional method for forming an ion-implanted diffusion layer. FIGS. ．． s,
Figure 7.8 is a cross-sectional view of the manufacturing method of MO3IrlCT according to the present invention 1.5.11...Semiconductor substrate 2.16...Resist 3...Ion implantation 4.8 , 12.18... Diffusion layer 6.17...
...Organic solvent containing impurities for diffusion 7...5107
% 13...Gate electrode 14...Gate film 15...Interlayer insulating film and above Applicant Suwa Seikosha Co., Ltd. Agent Patent attorney Tsutomu Mogamijjjjllj~3 ゛1st Figure 2 Figure 3 Ward Dimensions ■ School Picture Q To ■ 沫 明

Claims (1)

[Claims] (1) After forming a groove in a semiconductor substrate and filling the groove with an organic solvent or silicon dioxide containing a diffusion impurity,
1. A method of manufacturing a semiconductor device, comprising performing annealing to form an impurity diffusion layer at the bottom and side surfaces of the groove of a semiconductor substrate. (2) The semiconductor according to claim 1, wherein the organic solvent or silicon dioxide containing diffusion impurities is subjected to short-time high-temperature annealing (at least 900°C and within 10 seconds) using a halogen lamp. Method of manufacturing the device. (a) After forming a groove in a part of the source and drain regions of the MOS F Fi T, the groove is filled with an organic solvent containing As, P, or B impurities or silicon dioxide, and then annealing is performed to fill the area around the groove. MO8FI in the area! '
2. The method of manufacturing a semiconductor device according to claim 1, further comprising forming diffusion layers for source and drain regions. (4) MO871[! After forming a groove in the semiconductor substrate in the contact hole region connecting the metal wiring separated by the interlayer insulating film and the semiconductor substrate diffusion layer in the I and S process consisting of T, the groove is treated with an organic solvent containing diffusion impurities or carbon dioxide. A method for manufacturing a semiconductor device, characterized by performing annealing after embedding with silicon.