JPH01168054A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To be adapted for a high integration and to satisfy a breakdown strength requirement by varying the thickness of a gate insulating film in response to the function of a transistor. CONSTITUTION:After an isolating oxide film 2 is so formed at a predetermined position as to obtain an active region on the main face of a semiconductor substrate 1, a thicker oxide film 3 is formed by thermally oxidizing, the whole film 3 is coated with resist 4 including the film 2, and so patterned by a photocomposing technique as to expose only the film 3 on the left side active region. After the exposed left side film 3 is removed by etching, the resist 4 is removed, the active region is thermally oxidized, and a new thin oxide film 5 is formed on the main surface of the substrate 1 exposed at its left side. Thus, the difference of the thicknesses of the films 3, 5 after the thermal oxidation can be set to approx. the thickness of the film 3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device constituted by MOS (MOS) transistors having gate insulating films of different thicknesses.

[Prior art] In recent years, the degree of integration of semiconductor integrated circuits has been remarkable.
Not only dimensional miniaturization but also three-dimensional vertical reduction has been attempted. In MO8 integrated circuits that constitute ordinary logic circuits, for example, the gate length machining accuracy is several 10
In the era of ~3 or 4 micron order, MO3 circuit elements for logic circuits were made with a film thickness of about 1,000 times, but as the processing accuracy became submicron order of 2 microns or 1 micron or less, The proportional reduction agent works and the gate film thickness becomes about 200A or less.

FIG. 2 is a schematic cross-sectional view of the structure of such a general MOS transistor.

This configuration will be explained below with reference to the drawings.

A gate electrode 14 is formed on the main surface of an N-type semiconductor substrate 1 via a thin gate oxide film 15, and a source region 17 and a drain region 16 are formed on the main surface of the semiconductor substrate 1 on both sides.
A P+ type impurity region is formed. As for the operation of the transistor, when a predetermined voltage is applied to the gate electrode 14, the conductivity type of the region sandwiched between the source region 17 and the drain region 16 under the gate electrode 14 is reversed from N type to P type, and the source This is done by electrically connecting region 17 and drain region 16. Here, when the thickness of the gate oxide film 15 becomes thinner, the withstand voltage of the source and drain of the MOS transistor decreases.

Generally, MOS transistors are bidirectional elements, so
The drain will be described below. That is, the electric field applied to the drain region 16 and the gate oxide film 15 is
4 and source region 17 are the same, the thinner the gate oxide film 15 is, the stronger the voltage is. Therefore, the interface near the surface of the drain region 16 is likely to break down.

FIG. 3 is a schematic cross-sectional view of a MOS transistor having an LDD structure having a structure for relaxing the drain electric field based on the above-mentioned background.

This configuration will be explained below with reference to the drawings.

The basic structure is the same as that of the MOS transistor shown in FIG. 2, but in this transistor, the drain region is divided into a P-type drain region 16a and a P-type drain region 16b having different impurity concentrations. Since the drain region 16b having high resistance alleviates the drain electric field, the drain breakdown voltage increases.

[Problems to be Solved by the Invention] As mentioned above, it is expected that the elements of semiconductor integrated circuit devices will continue to become smaller and smaller, but from the perspective of application of the elements, there is a growing demand for more complex functions. ing. For example, if we take a single-chip microcomputer with a built-in fluorescent display driver, the capacity of the built-in memory will continue to increase.
Also, ALU (Arithmetic Logic
As the functionality of chips (units) also improves, the demand for miniaturization processes will become even stronger in order to suppress the increase in overall chip size. On the other hand, due to an increase in the number of segments driven as a fluorescent display tube, improvement in color display and display brightness, etc., the withstand voltage required of the drive section becomes a high voltage of about 40V, for example. However, many of the input/output parts other than the drive part operate at about 5V or less,
The breakdown voltage required for each transistor is also not necessarily constant. Therefore, there is a conflict between the reduction in breakdown voltage brought about by higher integration of elements and the demand for higher breakdown voltage due to functionality, and attempts have been made to deal with this by adopting a structure as shown in Figure 3. There has been a problem in that there are limitations due to thinning of the gate insulating film.

On the other hand, if the gate oxide film is formed thickly with emphasis on breakdown voltage,
Other elements that do not require high breakdown voltage also have the same film thickness, making it difficult to miniaturize the elements, and increasing the thickness of the gate oxide film reduces the operating speed of the element, which is disadvantageous in terms of operating characteristics. be.

The present invention has been made to solve these problems, and an object of the present invention is to provide a semiconductor integrated circuit device that is suitable for high integration and can satisfy voltage resistance requirements.

[Means for Solving the Problems] In the semiconductor integrated circuit device according to the present invention, the thickness of the gate insulating film is changed depending on the function of the transistor.

[Operations] In this invention, the thickness of the gate insulating film is changed according to the function of the transistor, so that the breakdown voltage of a transistor that requires a high breakdown voltage will not be reduced regardless of the integration of the elements.

[Example] Figures 1A to 1H are schematic process cross-sectional views showing a manufacturing method according to an example of the present invention.

This manufacturing method will be described below with reference to the drawings.

First, in order to secure an active region on the main surface of a semiconductor substrate 1 made of a silicon substrate, an isolation oxide film 2 is formed at a predetermined position using the LOCO8 method (see FIG. 1A), and then the exposed semiconductor substrate 1 is A thick oxide film 3 is formed by thermally oxidizing the main surface (see FIG. 1B).

Next, a resist 4 is applied to the entire surface of the oxide film 3 including the isolation oxide film 2, and this is patterned using a photolithography technique so that only the oxide film 3 on the left active region is exposed. (See Figure 1C).

After removing only the exposed oxide film 3 on the left side by etching (see Figure 1D), removing the resist 4 and thermally oxidizing the active region, a new thin oxide film is formed on the exposed main surface of the semiconductor substrate 1 on the left side. 5 is formed. As a result of this thermal oxidation, an oxide film is similarly formed on the surface of the oxide film 3 on the right side.
The difference in film thickness between oxide film 3 and oxide film 5 after thermal oxidation is approximately 1.
The thickness is approximately the same as that of the oxide film 3 formed in Figure B (see Figure 1E).

Subsequently, a polysilicon layer is deposited on the entire surface of the oxide film 3.5 including the isolation oxide film 2, and this is oxidized 11!3. to form the gate electrode of the transistor using photolithography and etching. A polysilicon layer 7 is formed on each of the layers 5 (see first FII).

Further, isolation oxide film 2 and polysilicon film 2 are formed.

A resist is applied to the entire surface of the oxide film 3.5, including the upper surface of the oxide film 3. Ions are implanted into the semiconductor substrate 1 through the wafer (see FIG. 1G).

Finally, remove the resist 8 and remove the polysilicon.

By etching and removing the exposed oxide films 3 and 5 using 7 as a mask, a MOS transistor having impurity regions 12 serving as source/drain regions in each active region is formed. That is, a semiconductor integrated circuit device in which the right transistor has a thick gate oxide film 10 and the left transistor has a thin gate oxide film 11 are formed on the same semiconductor substrate 1 (see FIG. 1H).

Thereafter, steps for forming an interlayer insulating film, wiring, etc. continue, but since they are outside the scope of this invention, their explanations will be omitted here.

In the above embodiment, the present invention is applied to an N-channel MOS, but the present invention can be similarly applied to either a P-channel MOS or a C/MOS.

Furthermore, although the above embodiments are applied to normal MOS transistors, it goes without saying that the invention can also be applied to MOS transistors having an LDD structure.

Further, in the above embodiment, the gate insulating film has two types of film thickness, but it goes without saying that three or more types of film thickness can be used as necessary.

[Effects of the Invention] As explained above, the present invention provides a semiconductor integrated circuit which is suitable for higher integration of elements and is advantageous in terms of the functional characteristics of the elements because the thickness of the gate insulating film is changed according to the function of the transistor. It has the effect of becoming a device.

[Brief explanation of the drawing]

1A to 1H are schematic process sectional views showing a manufacturing method according to an embodiment of the present invention, FIG. 2 is a schematic sectional view of a general MOS transistor, and FIG. 3 is a MOS transistor having an LDD structure.
1 is a schematic cross-sectional view of an S transistor; FIG. In the figure, 1 is a semiconductor substrate, 6 and 7 are polysilicon,
10.11 is a gate oxide film, and 12 is an impurity region.

Claims (1)

[Scope of Claims] A semiconductor substrate having a main surface; a first transistor having a first gate insulating film formed on the main surface of the semiconductor substrate; a second gate insulating film having a second gate insulating film;
A semiconductor integrated circuit device, comprising: a transistor, wherein the first and second gate insulating films have different film thicknesses.