JPS61140164A - Manufacture of semiconductor ic - Google Patents

Abstract

PURPOSE:To allow the output N-channel type element to have higher dielectric strength than that of the signal processing part by a method wherein the N-type diffusion to form the channel stopper of the P-channel type MOS element is used to form the drain of the output N-channel type element, thus rounding the shape of a junction plane. CONSTITUTION:In coexistence of the output channel-type element, source 11a and a drain 12a which are deep diffused layers can be obtained by applying the process of N-type impurity diffusion to form the channel stopper 4 of a P-channel type element also for the formation of the source and drain of the output N-channel type element. Further, in order to improve dielectric strength from the viewpoint of element shape, the junction plane of the drain 12a is allowed to have a rounding of a curvature radius (r), so as to generate no edges, by using an N-type diffusion window 18 patterned during this diffusion.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a complementary field effect transistor integrated circuit (0MO
The present invention relates to a method of imparting a higher withstand voltage than the signal processing section to an output N-channel type MOS element formed coexisting with the signal processing section of a SIC.

[Prior art and its problems]

FIG. 3 is a sectional view showing an example of the basic structure of a conventional 0MOSIC. In FIG. 3, 1 is an N-type semiconductor substrate, 2 and 3 are P-well regions, 4 is a P+ channel stopper of an N-channel type element formed by a P-chip, 8 and 9 are long sources and drains, and 10 is a P-well region 3. P+ channel stopper of nine N-channel type devices formed in 11.1
Reference numeral 2 denotes a source and a drain, and each of these elements is provided with a wiring metal 13 and a gate electrode 14.

In such a structure, a single power supply of around 5V is normally used as the power supply voltage of 0MOSIC, but there are cases where an even higher withstand voltage is required for the output element only.
N-channel type elements are often used as output elements; for example, in FIG. It is necessary for the element to have a high withstand voltage. As is clear from FIG. 3, these two N-channel devices have similar structures, and the output N-channel device formed in the P-well region 3! The type source diffusion layer 11 and the V type drain diffusion layer 12 are manufactured by the same manufacturing process as the r type source diffusion layer 8 and the length type drain diffusion layer 9 of the N channel type element of the signal processing section formed in the P well region 2. Generally, it is provided.

However, when applying a higher withstand voltage to the output N-channel element than the N-channel element in the signal processing section, as mentioned above, the output N-channel element and the signal processing section N-channel element are basically Since they have the same structure and their respective sources and drains are formed in the same process, the following disadvantages arise.

That is, the N-channel type elements in the signal processing section are required to be increasingly miniaturized, and the area occupied by the diffusion layer in the lateral direction cannot be ignored, so the source 8. The diffusion depth of the drain 9 must be made very shallow, but as is well known, the reverse withstand voltage of the junction decreases due to the shallow diffusion layer. The withstand voltage of the mold element also inevitably decreases.

Figure 4 is a plan view showing the main parts of an N-channel type element in the signal processing section.It has the same parts as Figure 10. After selectively oxidizing the field portion excluding the diffusion region 15, a polysilicon gate 14 is formed, and then an impurity is introduced using the field portion and gate electrode 14 as a mask to form a source 8 and a drain 9. Form. 13 is a wiring metal, and 16 is a contact hole thereof. As shown in Fig. 2, it is effective to make the fine signal processing part rectangular in shape in order to reduce the occupied area. The fact that such a portion 17 is formed and has this spherical joint surface also contributes to a decrease in withstand voltage.

FIG. 5 is a diagram showing the relationship between reverse withstand voltage and drain junction depth regarding the shape of the junction. Figure 5 shows the case where the surface concentration of the P-well is I x 1016an-3, but even if the surface concentration of the P-well changes slightly, the trend of the curve remains the same, and the withstand voltage suddenly increases when the diffusion depth is around 1 μm. Changes to As for the shape of the joint, it can be seen from FIG. 5 that a joint having a part that is a part of a spherical surface has a withstand voltage lower by about IOV than a joint having a cylindrical part.

As mentioned above, in the conventional 0MOSIC, in order to make the output N-channel type element have a higher withstand voltage than the signal processing section, K
The obstacles were the diffusion depth of the source and drain y and the shape of their junction surfaces.

[Purpose of the invention]

The present invention has been made in view of the above points, and its purpose is to provide a method for manufacturing an output N-channel 11MOS element having a higher withstand voltage than the signal processing section in an 0MOSIC.

[Key points of the invention]

The present invention forms a channel stopper for the P-channel MOS element when forming a CMOS structure having an N-channel MOS element and a P-channel MOS element as a signal processing part and an output N-channel MOS element on the same semiconductor substrate. By using 8th generation diffusion to form at least the drain of the output N-channel type element to form a deep diffusion layer and rounding the shape of the junction surface of the output N-channel type element, The channel type element is made to have a higher withstand voltage than the signal processing section. [Embodiments of the Invention] The present invention will be described below based on embodiments.

First, FIG. 1 shows a cross-sectional view of the structure of a 0MOSIC obtained according to the present invention. Portions in FIG. 1 that are common to FIG. 3 are designated by the same reference numerals.

As already mentioned, a CMOS circuit includes a P-channel type device, and especially when manufactured using a selective oxidation method, a P-channel type device is included.
A channel stopper 4 made of N-type impurities is arranged around the channel type element before the selective oxidation process. After this channel stopper 4 is formed, it undergoes a long heat treatment, so that the final diffusion depth reached is equal to that of the source 8 of the N-channel device, which is equal to that of the same type of impurity. It becomes deeper than the diffusion layer of the drain 9. Therefore, when an N-channel output device is used, the N-type impurity diffusion process for forming the channel stopper 4 of the P-channel device can be applied to the source and drain of the output N-channel device. Source lla of deep diffusion layer as shown in Figure 1
and a drain 12a can be obtained. Note that the source 8 of the N-channel type element in the signal processing section. In the step of shallowly diffusing the drain 9, the source lla and drain 12aK of the output N-channel type element are also applied to form shallow furnace diffusion layers 11b and 12b, which play a role in making good contact with the wiring metal 13. accomplish

Regarding the diffusion depth, as shown in FIG. 5 above, the drop in withstand voltage due to shallow diffusion junctions becomes severe near the junction depth 11Ifn, so P-channel type elements applied to output N-channel type elements It is effective if the depth of the N-type diffusion forming the channel stopper 4 is 1- or more, and the upper limit depth is the allowable limit of the effective area of the P-channel type element determined by the diffusion depth of the channel stopper 4. The thickness should be 5 μm or less in accordance with this.

Note that the source lla of the output N-channel element is normally P.
Since the potential is the same as that of the well region 3, it is sufficient from the viewpoint of withstand voltage that the deep N-type diffusion layer is formed only in the drain 12a. However, forming the source in the shallow diffusion layer and the drain in the deep diffusion layer in separate processes in the same device causes alignment errors and variations in channel length. Deep diffusion layers 11a and 12a may be formed in both.

Next, FIG. 2 shows a plan view of essential parts of the shape of an output N-channel type element to which the present invention is applied.

In FIG. 2, parts common to those in FIG. 4 are indicated by the same reference numerals.

As explained in FIGS. 4 and 5 above, when the planar shape of the element is rectangular, a bonding surface that is a part of a spherical surface is formed at the edge, and this spherical bonding surface forms a cylindrical bonding surface. The electric field concentration is greater than that on the surface, and the withstand voltage decreases. In the present invention, in order to increase the withstand voltage of the output N-channel type element, at least the drain 12a is formed as a deep diffusion layer in the output N-channel type element at the same time as the channel stopper 4 of the P-channel type element is formed. However, in order to further improve the withstand voltage from the viewpoint of the element shape, the shape of the junction surface of the drain 12a is changed to the edge part by using the patterned N-type diffusion window 18 during this diffusion, as shown in FIG. It has a roundness with a radius of curvature r shown by the arrow so that it does not occur.@Moreover, the drain 1
The bonding surface of 2a is the boundary with the selective oxide film of the diffused region 15, which is formed in a later process and is drawn with a dashed line, and the gate electrode 1.
4 as a mask to position it outside the diffusion front of the N-type shallow diffusion layer 12b. In this way, the spherical junction 17a with a small radius of curvature due to the edge of the shallow diffusion layer 12b becomes a deeply diffused drain. Since K is contained within the junction surface of 12 m, there is no adverse effect on the withstand voltage of the output N-channel type element.

Furthermore, if the radius of curvature r of the roundness formed on the junction surface of the drain 12a is too small, it will approach a spherical junction and the effect of improving withstand voltage will not be obtained, so it is better to set it to 5 μm or more. The withstand voltage of a joint surface with a cylindrical joint surface is approximately the same as that of a cylindrical joint surface. Although the explanation regarding the source side in FIG. 2 will be omitted, when providing the deep diffusion layer 11a, it can be done in exactly the same way as the drain 12a.

As described above, the present invention forms a deep N-type diffusion layer in the source and drain, or the drain alone, without adding any special manufacturing process, in order to increase the withstand voltage of the output N-channel dielectric element, and also forms a deep N-type diffusion layer in the junction surface of the source and drain, or the drain alone. Shape radius 5μ
The edge portion is eliminated by adding a curvature of m or more.

〔Effect of the invention〕

CMOS structure with N-channel MOS element and P-channel MOS element, and N-channel MOS for output
N for output of 0MOSIC which is formed on the same substrate as the device
In order to improve the withstand voltage of the channel 11 MOS element, we have conventionally used a fine N-channel MOS element source in the signal processing section where the source and drain diffusion depths of the output N-channel MOS element are formed in the same process. However, according to the present invention, the embodiment of the present invention As explained above, the process of diffusing the channel stopper of a P-channel MOS device is
By simultaneously applying the method to diffusion for forming the source and drain or only the drain of a channel type MOS device, a deep diffusion layer can be obtained, and in this case, a spherical junction is formed in the source and drain diffusion layers. In order to prevent this, the bonding surface at the edge portion has a curvature of 5 μm or more, so the two points of providing a deep diffusion layer and rounding the bonding area work effectively to reduce the output N. This has succeeded in providing a channel type MOS element with a higher withstand voltage than the signal processing section.

Furthermore, the present invention has the advantage that the object can be easily achieved by simply rearranging the nine-step process procedure or changing the diffusion pattern without introducing any special manufacturing steps.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of the structure of 90 MOSIC to which the present invention is applied, and Figure 2 is the output N-channel type MOS in Figure 1.
A plan view of the main parts of the device, Fig. 3 is a cross-sectional view of the structure of 0MOSIC including a conventional output N-channel type MOS element, and Fig. 4 shows the junction depth and the cylindrical junction surface of the output N-channel surface and the cylindrical junction surface in Fig. 3. ◇ 1...N'' type semiconductor substrate, 2, 3...
P well region, 4, 7.10... Channel stopper, 5.8.11゜11 a --- Source, 6, 9.12, 12a... Drain, llb
. 12b... Shallow diffusion layer, 13... Wiring metal, 14... Gate electrode, 15...
Diffused region, 16... Contact hole, 17, 1
7a... Spherical joint part, 18... Diffusion window. Figure 2 Figure 4 Figure 5

Claims (1)

[Claims] 1) N-channel MOS element and P-channel MOS
CMOS circuit consisting of elements and N-channel type M for output
In manufacturing a semiconductor integrated circuit having an OS element and an OS element on the main surface of the same semiconductor substrate, a process of diffusing and forming a channel stopper to be disposed around the P-channel MOS element is used. N-channel type MO
At least the drain diffusion layer of both the source and drain diffusion layers of the S element is formed at the same time as the channel stopper, and the formed diffusion layer is patterned so as to have a rounded periphery around the bonding surface. A method for manufacturing semiconductor integrated circuits. 2) In the method described in claim 1, the depth of the N^+ diffusion layer forming the channel stopper is 1 to 5.
A method for manufacturing a semiconductor integrated circuit, characterized in that the size of the semiconductor integrated circuit is .mu.m. 3) A method for manufacturing a semiconductor integrated circuit according to claim 1 or 2, characterized in that the radius of curvature of the roundness around the bonding surface is 5 μm or more.