JPS61114552A - Semiconductor device - Google Patents

Abstract

PURPOSE:To curb the coupling of function elements by a method wherein a contact region defined by a field insulating film is formed on a substrate and surrounds a function element also defined by the field insulating film. CONSTITUTION:In the vicinity of a p-channel MOS transistor defined by a field oxide film 3 including a region wherein gate electrodes 7a, 7b extend, a frame-shape n<+> type substrate contact region 110 is provided, defined by the field oxide film 3 surrounding the p-channel MOS transistor. The contact region 110 is located some distance from p<+> type source.drain regions 9a, 9b, 9c. Similarly, in the vicinity of an n-channel MOS transistor, a frame-shape p<+> type well.contact region 111 is provided, surrounding the n-channel MOS transistor. The p<+> type well.contact region 111 is located some distance from n<+> type source.drain region 8a, 8b, 8c.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to improvements in the structure of semiconductor devices, and particularly relates to the structure of complementary gate arrays (hereinafter abbreviated as CMOS gate arrays) aimed at improving operating speed. .

Today, as large-scale integrated circuits become larger, there is a remarkable trend toward high-mix, low-volume production.
Manufacturing of large-scale integrated circuits using the master 5lice method has become popular.

In such gate arrays, CMOS gate arrays, which are advantageous in terms of low power consumption, are often used;
There is a strong desire to improve the operating speed of S-gate arrays.

[Conventional technology]

Figure 4 is a plan view (a) schematically showing a unit cell in a conventional CMOS gate array, and a cross-sectional view taken along the line A-A (b).
and BB arrow sectional view (C1, in the same figure, 1 is an n-type silicon substrate, 2 is a p-type well, 3 is a field oxide film, 4 is an n° type channel/force/node region, 5 is a p channel cant region, 6 is a gate oxide film, ?a, 7b are first and second gate electrodes, and 8a, 8b, and 8c are first and second gate electrodes.
．． n-type region n that becomes the third source or drain
' type source/drain region), 9a, 9b, 9c are p''
' type source/drain region, 10 is an n°° substrate contact region, 11 is a p+ type well contact region, 12 is an oxide film for impurity blocking (hereinafter abbreviated as block oxide film), 13 is phosphosilicate glass (PSG) Represents an insulating film.

Note that in the figure, wiring connections to the gate electrode, source/drain region, and base contact region are omitted.

In a conventional CMOS gate array, as shown by diagonal lines in different directions in the same figure, p-channel MOAs are functional elements.
An n-type channel cut region 4 is formed in the substrate surface under the field oxide film 3 defining the 3I-transistor (p-MOS). p°° on the well surface
Channel cut regions 5 were respectively provided to prevent coupling between adjacent functional elements, ie transistors, and between adjacent functional regions, ie source-drain regions.

[Problem that the invention seeks to solve]

However, in the conventional structure described above, since the channel cut region having a high impurity concentration is in direct contact with each source/drain region, a potential different from that of the substrate or well is applied to these source/drain regions and the CMO3I-transistor is When driving the CMOS transistor, the junction capacitance of the source/drain region increases, causing a problem that the operating speed of the CMOS transistor decreases.

Furthermore, not only the MO3) transistor mentioned above, but also a resistance element of the conductivity type opposite to the base body disposed on the semiconductor base body is connected to the base body by a channel cut region having a high impurity concentration of @1 conductivity type, as in the case of the above transistor. Since coupling with the element was prevented, a large capacitance was parasitic to the resistor element,
There was also the problem that the operating speed of the circuit was delayed.

[Means for solving problems]

A solution to the above problem is to have a field insulating film on a semiconductor substrate, a device region and a substrate contact region respectively defined by blooming of the field insulating film, and the substrate contact region surrounds the device region and forms a channel. - Achieved by the semiconductor device according to the present invention that also has a cutting function.

[Effect]

That is, the present invention provides a base contact region defined by the field insulating film surrounding a functional element such as a transistor or a resistor defined by a field insulating film on the surface of a semiconductor substrate such as a substrate or a well, and a base contact region defined by the field insulating film. By also having a channel cut function, the functional elements are separated, and furthermore, the functional area to be separated in the functional element is completely surrounded by the gate electrode of the functional element and the base contact region, This prevents binding between the functional regions.

Thus, each functional region has a high concentration impurity region, that is, a channel region.
Since it is no longer in direct contact with the cut region and its junction capacitance is reduced, the operating speed of the semiconductor device is improved.

〔Example〕

The present invention will be specifically described below with reference to illustrated embodiments.

FIG. 1 is a plan view (al) schematically showing a first embodiment of a CMOS gate array;
BB arrow sectional view (C1 and C-C arrow sectional view + d),
FIG. 2 is a plan view (a) schematically showing a second embodiment of the CMOS gate array, and a cross-sectional view taken along the line A-A (b).
FIG. 3 is a plan view (al) and a cross-sectional view along A-A (BL) schematically showing one embodiment of the resistance element.

Identical objects are indicated by the same reference numerals throughout the figures.

In FIG. 1, 1 is an n-type silicon substrate, 2 is a p-type well, 3 is a field oxide film, 6 is a gate oxide film, and 7 is a p-type well.
a, 7b are the first. Second gate electrode, 8a, 8b, 8c
is the first. Second. n that becomes the third source or drain
° type region n'' type source/drain region), 9a, 9b
, 9c are p-type source/drain regions, 110 is an n-type substrate contact region, 111 is a p-well contact region, and 12 is an oxidized n! for impurity block. (Block oxide film), 13 indicates a PSG (phosphosilicate glass) insulating film.

In the first embodiment, as shown in the figure, a p-channel MOS transistor (p-M
A frame-shaped n゛゛ substrate contact region 110 defined by a field oxide film β surrounding the p-M○S is provided in the peripheral part of the p-M○S in the peripheral part of the p-M○S.
A frame-shaped p° type well contact region 111 is provided at a distance from the n-channel MOS transistor (n-MOS) and similarly surrounds the n-channel MOS transistor (n-MOS).
It is provided apart from type source/drain regions 8a, 8b, and 8c.

Note that the structure of the cross section corresponding to the A-A and B-B arrows on the p-MOS side is such that the source/drain regions are p'source/drain regions except for the p-type well 2 in Figures (b) and [0] In drain region i regions 9a, 9b, and 9c, well contact regions are only replaced with n'substrate contact regions 110, and the rest remains unchanged, so a description thereof will be omitted.

In the structure of this embodiment, the illustrated p-MO3 and n-MOS
The coupling due to the extension of the depletion layer between the transistors and adjacent transistors (not shown) is achieved through the frame-shaped n° type substrate contact region 1.
10 and p'well contact region 111.

Also, n1 type source/drain regions 3a, 3b.

8c is completely surrounded by gate electrode 7a or 7b and p1 type well contact region 111, respectively, and p
“type source/drain regions 9a, 9b.

9C are completely surrounded by the gate electrode 7a or 7b and the n" type substrate contact region 110, respectively, so that
Coupling due to the extension of the depletion layer to each adjacent source/drain region is prevented.

Furthermore, since no channel stopper is formed, each source/drain region does not come into contact with the high concentration layer, and its junction capacitance is reduced.

Is the gate electrode in Figure 2? a, 7b wiring connection area 70a,
In order to flatten the area 70b and facilitate wiring connections, the frame-shaped n゛゛ substrate contact region 210 and the p゛゛ well contact region 211 are connected to the gate electrodes 7a, 7b.
This is an example in which the gate electrodes are terminated at the lower part of the gate electrodes 7a and 7b, and a part of the lower part of the gate electrodes 7a and 7b is cut out.

Other parts are the same as the example shown in FIG. Here, D indicates the missing part of the above-mentioned contact) %J[area.

In this structure, the missing contact area is used as the gate electrode. The gate electrodes covered by electrodes a and 7b and to which a - potential is applied serve as channel cuts in the gaps and regions, so that the source and drain regions are completely separated by the gate electrodes and the substrate contact regions. become surrounded.

Therefore, in this structure as well, coupling between the sources and drains is completely prevented.

In the first embodiment, the impurity introduction for forming the source and drain and the impurity introduction for forming the base contact are performed separately, but they may be performed simultaneously. However, in that case, there is no base contact region under the gate electrode extension part in FIG.
This is a modification of the second embodiment in which the region ends under the gate electrode.

FIG. 3 shows an example of a resistive element.

In the figure, 21 denotes p-type low resistance layers 22a, 22b,
22c is a wiring contact window, 23a and 23b are wirings connected to the resistance element, 23c is a substrate contact wiring, and other symbols indicate the same objects as in FIGS. 1 and 2.

In this structure, the resistance layer 21 is surrounded by a frame-shaped n° type contact region 110 formed around the periphery of the resistance layer 21, so that the resistance element and other elements caused by the expansion of the depletion layer at the resistance layer junction are Coupling with the device is prevented by the substrate contact region.

Furthermore, since no channel stopper is formed around the resistance layer, the resistance layer does not come into contact with the high concentration region, and the parasitic capacitance of the resistance layer is reduced.

In all of the embodiments described above, the impurity concentration of the n'' substrate contact regions 110, 210 and the p'' well contact regions 111, 211 is usually formed at a high concentration of about 10''cm@-3.

The substrate contact area and the well contact area are
It is not necessary to form the layer separately from the functional region to which the same potential as that of the substrate and the well is applied.

It goes without saying that the present invention is not limited to the above-mentioned embodiments, but can also be applied to CMO5 semiconductor devices having an n-well, CMOS semiconductor devices with a twin-tub structure, and single-channel MOS semiconductor devices.

〔Effect of the invention〕

As explained above, according to the present invention, functions between and within functional elements can be maintained even without forming channel cut regions around elements such as transistors and resistors formed on a semiconductor substrate such as a substrate or well. Coupling between regions can be prevented.

Therefore, the functional region to which a potential different from that of the substrate of the semiconductor element is applied does not come into direct contact with the channel cut region having a high impurity concentration, and its junction capacitance is reduced, which reduces the operating speed of CMOS semiconductor integrated circuit devices, etc. Improvements can be made.

[Brief explanation of drawings]

FIG. 1 is a plan view (al) schematically showing a first embodiment of a CMOS gate array, and a cross-sectional view taken along the line A-A (bl).
, B-B arrow sectional view (C1 and C-C arrow sectional view [dl
, FIG. 2 is a plan view (a) schematically showing a second embodiment of a CMOS gate array, a cross-sectional view along A-A (fb), and a cross-sectional view along B-B (C1, FIG. 3 shows a resistor). A plan view schematically showing an example of an element (aLA-A sectional view (bl), FIG. 4 is a plan view (al, A-A cross-sectional view schematically showing a unit cell in a conventional CMOS gate array) Cross-sectional view (BL and BB arrow cross-sectional view (C). In the figure, 1 is an n-type silicon substrate, 2 is a p-type well, 3 is a field oxide film, 6 is a gate oxide film, 7a, 7b is the first and second gate electrodes, 8a, 8b, 8
c is an n9 type source/drain region; 9a, 9b, 9c are p' type source/drain regions; 12 is an oxide film for impurity blocking; 13 is a PSG (phosphosilicate glass) insulating film; 110 is an n°
type substrate contact region; 111 indicates a p4 type well contact region; Leather f Ward (I2) n-MOS fi-MθS
Stem Z Drunken leather 3 ward 2/ / yta

Claims (1)

[Scope of Claims] 1. A field insulating film on a semiconductor substrate, and an element region and a substrate contact region each defined by an opening in the field insulating film, and the substrate contact region surrounds the device region. A semiconductor device characterized by having a channel cut function. 2. The substrate contact region terminates under the gate, and the gate pattern and the substrate contact region completely surround the functional region to be separated in the device region. A semiconductor device according to scope 1.