JP2738602B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor integrated circuit device having a BiCMOS structure.

[0002]

2. Description of the Related Art FIG. 3 is a cross-sectional view showing a part of a chip of a conventional semiconductor integrated circuit device having a CMOS structure, showing an N-channel MOS transistor and a P-channel MOS transistor, and the vicinity of a scribe line which is a chip dividing line around a chip area. It is. In the figure, 1 is a p-type Si semiconductor substrate, 17 is an n-type well diffusion region formed in the substrate 1, 16 is a p-type well diffusion region, and 11a is a P ⁺ source / drain formed in the n-type well diffusion region 17. The diffusion region 12a is formed by N ⁺ formed in the p-type well diffusion region 16.
These are source / drain diffusion regions. Reference numeral 14 denotes contact electrodes of the N-channel MOS transistor and the P-channel MOS transistor, and reference numeral 10 denotes a PolySi gate electrode formed with the gate oxide film 9 interposed therebetween. Reference numeral 7 denotes a field oxide film, 13 denotes an insulating film, and 18 denotes a scribe line for separating chips.

FIG. 4 is a cross-sectional view showing a part of a chip of a conventional semiconductor integrated circuit device having a bipolar structure, showing the vicinity of a scribe line around an NPN transistor and a chip area. 3, the same reference numerals as those in FIG. 3 denote the same or corresponding parts, 2 denotes an n ⁺ -type impurity buried diffusion region formed on the substrate 1, and 3 denotes a p ⁺ -type impurity buried diffusion region formed on the substrate 1. The region 4 is an n-type epitaxial growth layer formed on the substrate 1. 5a is a p-type isolation diffusion region formed in the epitaxial growth layer 4, 8 is a deep n ⁺ type collector diffusion region, and 11b is a p-type diffusion region formed in the epitaxial growth layer 4.
^{A +} type base diffusion region, 12b is an n ⁺ type emitter diffusion region, and 14 is each contact electrode.

FIG. 2 shows a part of a semiconductor integrated circuit chip having a conventional BiCMOS structure obtained by combining the CMOS structure shown in FIG. 3 and the bipolar structure shown in FIG. FIG. 3 is a cross-sectional view showing a P-channel MOS transistor, an NPN transistor, and a vicinity of a scribe line around a chip area. In the drawings, the same reference numerals as those in FIGS. 3 and 4 denote the same or corresponding parts, 5b denotes a p-type well diffusion region which is an impurity diffusion region of the same conductivity type as the substrate 1 formed in the epitaxial growth layer 4, and 6 denotes an n-type diffusion region. This is a well diffusion region.

Next, a manufacturing flow will be described. In FIG. 3, a p-type well diffusion region 1 is formed in a p-type Si semiconductor substrate 1.
6 and an n-type well diffusion region 17 are formed. Here, the p-type well diffusion region 16 can be omitted. Next, the field oxide film 7 is formed by oxidizing portions other than the transistor forming portion and the scribe lines 18 by the LOCOS method. Next, a gate oxide film 9 and a PolySi gate electrode 10 are formed. Next, a P ⁺ source / drain diffusion region 11a and an N ⁺ source / drain diffusion region 12a are formed in a self-aligned manner. Next, an insulating film 13 is formed by a CVD method, a contact for electrode connection is opened, and a metal electrode 14 of Al or the like and a wiring (not shown) connected to the electrode 14 are formed. Next, after cutting the Si substrate 1 along the scribe line and dividing it into chips,
The integrated circuit device having the CMOS structure is completed by being incorporated in a package. Here, the n-type well diffusion region 17 of the P-channel MOS transistor is electrically separated by setting the pn junction between the p-type substrate 1 and the p-type well diffusion region 16 to a reverse bias.

Next, referring to FIG. 4, a p-type Si semiconductor substrate 1 is formed.
Then, an n ⁺ type buried diffusion region 2 and a p ⁺ type buried diffusion region 3 are formed. Next, n-type Si is deposited on the entire surface of the substrate by CVD.
An epitaxial growth layer 4 is formed. Next, a p-type isolation diffusion region 5a and a field oxide film 7 are formed. Next, a deep n ⁺ -type collector diffusion region 8 is formed. Next, ap ⁺ -type base diffusion region 11b and an n ⁺ -type emitter diffusion region 12b are sequentially formed. Thereafter, as in the case of the CMOS shown in FIG. 3, an insulating film 13, each contact electrode 14, and wiring (not shown) are formed, then divided into chips, and assembled into a package to complete an integrated circuit device having a bipolar structure. . Here, each bipolar transistor is electrically isolated by the p ⁺ -type buried diffusion region 3 and the p-type isolation diffusion region 5a.

Next, a manufacturing flow of the semiconductor integrated circuit having the BiCMOC structure shown in FIG. 2 will be described. First, an n ⁺ -type buried diffusion region 2 is formed in a p-type (first conductivity type) Si semiconductor substrate 1 by forming a bipolar transistor forming portion and a P-channel M
It is formed in an OS transistor formation portion. Next, ap ⁺ type (first conductivity type) buried diffusion region 3 is formed around the bipolar transistor and in the N-channel MOS transistor formation portion. Next, an n-type (second conductivity type) Si epitaxial growth layer 4 is formed on the entire surface of the substrate by a CVD method. Next, a p-type (first conductivity type) well diffusion region 5b
Is formed in the portion other than the N-channel MOS transistor forming portion and the transistor forming portion so as to reach the p ⁺ type buried diffusion region 3. Next, the n-type well diffusion region 6
Is formed in the P-channel MOS transistor forming portion.
However, this can be omitted. Then, FIG.
After the field oxide film 7 is formed, a deep n ⁺ -type collector diffusion region 8 is formed as in the case of the CMOS.
Next, the gate oxide film 9 and the PolySi gate electrode 1
0 is formed. Next, a P ⁺ source / drain diffusion region 11a and ap ⁺ type base diffusion region 11b are formed. Next, an N ⁺ source / drain diffusion region 12a and an n ⁺ emitter diffusion region 12b are formed. Hereinafter, the CMO of FIG.
Similarly to the case of S, after forming the insulating film 13, each collector electrode 14, and wiring (not shown), the chip is divided into chips.
BiCM incorporated in a package and combining the CMOS structure shown in FIG. 3 and the bipolar structure shown in FIG.
An integrated circuit device having an OS structure is completed.

In the integrated circuit device having the BiCMOS structure obtained as described above, the n-type well diffusion region 6 of the P-channel MOS transistor is different from the bipolar transistor formation portion, and the p ⁺ -type buried diffusion region 3 is provided therearound. Since the p-type substrate 1 is not formed, the p-type well diffusion region 5b alone does not completely electrically separate the p-type well diffusion region 5b, and may cause an electric leak to the p-type substrate 1. Specifically, Bi shown in FIG.
Since the integrated circuit device having the CMOS structure differs from the CMOS structure of FIG. 3 in that the p-type well diffusion region 5b is formed in the n-type epitaxial growth layer 4, the p-type well diffusion region 5b is formed.
And the p-type substrate 1 are not completely connected, that is, the substrate 1
In this state, there is a thin n-type epitaxial growth layer 4 between the n-type well diffusion region 5b and the p-type well diffusion region 5b. An electric leak path is generated, and the p-type Si
This is because the substrate 1 is electrically short-circuited. As described above, in the conventional integrated circuit device having the BiCMOS structure, the P ⁺ source / drain diffusion region 11a of the P-channel MOS transistor may electrically leak from the p-type Si substrate 1.

[0009]

Since the conventional semiconductor device having the BiCMOS structure is configured as described above,
For example, the source and drain of a P-channel MOS transistor are liable to cause electrical leakage with the Si substrate,
It becomes very difficult to design a circuit. To prevent this, forming ap ⁺ -type buried diffusion region around a P-channel MOS transistor as well as a bipolar transistor portion leads to an increase in chip area. There were problems such as a reduction in yield.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a semiconductor device capable of completely preventing inter-substrate leakage without increasing the chip area. .

[0011]

According to the present invention, there is provided a semiconductor device, which is provided at a boundary between a substrate and an impurity diffusion region formed in an epitaxial growth layer and between a chip region and a chip dividing line around the chip region. In this region, a semiconductor layer of the same conductivity type as the substrate is formed so as to surround the entire chip region.

[0012]

According to the present invention, at the boundary between the substrate and the impurity diffusion region formed in the epitaxial growth layer,
In addition, since a semiconductor layer of the same conductivity type as the substrate is formed in a region between the chip region and the chip dividing line around the chip region so as to surround the entire chip region, a region between the substrate and the impurity diffusion region is formed. The electrical leak path is blocked.

[0013]

1 is a sectional view showing a semiconductor device according to one embodiment of the present invention. 1, the same reference numerals as those in FIG. 2 denote the same or corresponding parts, and reference numeral 15 denotes ap ⁺ type buried diffusion region which is a semiconductor layer of the same conductivity type (first conductivity type) as the substrate.

The production flow is shown in FIG.
Similar to the integrated circuit device having the iCMOS structure, the p ⁺ -type buried diffusion region 15 is formed at the same time as the p ⁺ -type buried diffusion region 3 so that the entire chip region is interposed between the chip region and a scribe line 18 around the chip region. It is formed so as to surround it.

Next, the function and effect will be described. In the conventional example shown in FIG. 2, the n-type well diffusion region 6 of the P-channel MOS transistor does not have the p ⁺ -type buried diffusion region 3 formed around it, so that the p-type well diffusion region 5 is formed.
The electric leakage path of the n-type well diffusion region 6 was generated between the p-type well diffusion region 5b and the p-type substrate 1 without being completely electrically separated only by b. However, in the present embodiment, a p-type region is formed between the substrate 1 and the p-type well diffusion region 5b and between the scribe line 18 which is a chip region chip division line so as to surround the entire chip region.
^{Since the +} -type buried diffusion region 15 is formed, the cut portion of the scribe line 18 of the Si substrate 1 and the n-type well diffusion region 6 correspond to the p ⁺ -type buried diffusion region 15 and the p-type well diffusion region 5b. And is electrically separated completely. Therefore, the n-type well diffusion region 6 of the P-channel MOS transistor does not cause electrical leakage with the p-type substrate 1, and the P ⁺ source / drain diffusion region 11a is completely electrically separated from the p-type substrate 1. be able to.

Since the p ⁺ type buried diffusion region 15 can be formed around the bipolar transistor and simultaneously with the p ⁺ type buried diffusion region 3 in the N-channel MOS transistor forming portion, the number of steps is increased. Never.

Further, between the scribe line 18 surrounding the chip region and the chip area is patterned designed to ensure an area that does not form a functional element of the original such as a transistor, p ⁺ -type buried as described above Even if the diffusion region 15 is formed so as to surround the entire chip region, the chip area does not increase.

In the above embodiment, the manufacturing flow for simultaneously forming the P ⁺ source / drain diffusion region 11a and the p ⁺ -type base diffusion region 11b and the N ⁺ source / drain diffusion region 12a and the n ⁺ -type emitter diffusion region 12b. However, any of them may be formed separately. In addition, the order and method of the manufacturing flow may be different, and in such a case, the same effect as in the above embodiment can be obtained. Needless to say, the conductivity types of all the regions may be reversed.

In the above embodiment, the case of a BiCMOS integrated circuit device has been described. However, if an integrated circuit device having a CMOS structure has an epitaxial growth layer of the opposite conductivity type to the substrate, the above embodiment may be used. Similar effects can be obtained by forming a semiconductor layer of the same conductivity type as that of the substrate.

[0020]

As described above, according to the semiconductor device of the present invention, the chip region and the chip dividing line around the chip region at the boundary between the substrate and the impurity diffusion region formed in the epitaxial growth layer are formed. In between, a semiconductor layer of the same conductivity type as the substrate is formed so as to surround the entire chip region, so that an electric leak path between the substrate and the impurity diffusion region can be cut off, Therefore, there is an effect that a semiconductor device having no inter-substrate leakage of MOS transistors can be obtained without increasing the chip area.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a part of a chip of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a part of a chip of a conventional semiconductor device having a BiCMOS structure.

FIG. 3 is a cross-sectional view showing a part of a chip of a conventional semiconductor device having a CMOS structure.

FIG. 4 is a cross-sectional view showing a part of a chip of a conventional semiconductor device having a bipolar structure.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 2 n ⁺ type buried diffusion region 3, 15 p ⁺ type buried diffusion region 4 epitaxial growth layer 5 b p type well diffusion region 6 n type well diffusion region 11 a P ⁺ source / drain diffusion region 18 scribe line

Claims (1)

(57) [Claims] 1. A first conductivity type impurity buried diffusion region is formed in a first conductivity type semiconductor substrate, and a second conductivity type epitaxial growth layer serving as a well common to each element is formed on the entire surface of the semiconductor substrate. In a semiconductor device having a first conductivity type impurity diffusion region formed in a predetermined region of the epitaxial growth layer so as to reach the impurity buried diffusion region, an impurity diffusion region formed in the semiconductor substrate and the epitaxial growth layer is provided. And a region between the chip region of the semiconductor substrate on which the respective elements are formed and the chip dividing line around the chip region, so as to surround the entire chip region. A semiconductor device having a semiconductor layer formed thereon.