CN109599358B

CN109599358B - Method for manufacturing chip with isolation structure

Info

Publication number: CN109599358B
Application number: CN201811424782.6A
Authority: CN
Inventors: 王钊
Original assignee: Hefei Zhonggan Micro Electronic Co ltd
Current assignee: Hefei Zhonggan Micro Electronic Co ltd
Priority date: 2018-11-27
Filing date: 2018-11-27
Publication date: 2021-05-04
Anticipated expiration: 2038-11-27
Also published as: CN109599358A

Abstract

The invention provides a manufacturing method of a chip with an isolation structure, which comprises the following steps: providing a wafer comprising: a substrate; a first circuit formed on the substrate; a second circuit formed on the substrate adjacent to the first circuit; the metal connecting layer is positioned on the first surface of the substrate and crosses the substrate gap area, the metal connecting layer is used for electrically connecting the first circuit and the second circuit, the substrate gap area is a substrate part between the first circuit and the second circuit, and the substrate gap area is cut to form an isolation groove. This may enhance circuit isolation performance.

Description

Method for manufacturing chip with isolation structure

[ technical field ] A method for producing a semiconductor device

The invention relates to the technical field of chip design, in particular to a manufacturing method of a chip with an isolation structure.

[ background of the invention ]

In chip design, isolation between circuits is enhanced, and influence of a noise circuit on a sensitive circuit can be reduced. Referring to fig. 1, a schematic diagram of integrating two circuits of Part _ a and Part _ B on the same chip in the prior art is described. The advantages are high integration and high processing efficiency. However, there is a problem that one circuit interferes with another circuit, for example, Part _ a is a digital circuit in which noise is large (Part _ a may be referred to as a noise circuit), and Part _ B is an analog circuit which is sensitive to noise (Part _ B may be referred to as a sensitive circuit). This may cause interference of the digital circuit with the analog circuit, degrading the performance of the analog circuit, and in severe cases, causing the analog circuit to fail.

Therefore, it is necessary to provide a method for manufacturing a chip with an isolation structure to enhance circuit isolation performance.

[ summary of the invention ]

The invention aims to provide a manufacturing method of a chip with an isolation structure, which can enhance the circuit isolation performance.

In order to solve the above problems, the present invention provides a method for manufacturing a chip having an isolation structure, including: providing a wafer comprising: a substrate; a first circuit formed on the substrate; a second circuit formed on the substrate adjacent to the first circuit; the metal connecting layer is positioned on the first surface of the substrate and crosses the substrate gap area, the metal connecting layer is used for electrically connecting the first circuit and the second circuit, the substrate gap area is a substrate part between the first circuit and the second circuit, and the substrate gap area is cut to form an isolation groove.

In a preferred embodiment, when the substrate gap region is cut, a portion of the substrate gap region is cut,

the isolation trench penetrates from the first surface of the substrate to the second surface of the substrate, and the isolation trench penetrates through a part of the substrate gap region; the metal connecting layer crosses another part of the substrate gap region which is not penetrated by the isolation trench.

In a preferred embodiment, when cutting the substrate, the whole substrate gap region is cut, the isolation trench penetrates from the first surface of the substrate to the second surface of the substrate, and the isolation trench penetrates the whole substrate gap region; the metal connection layer spans the entire substrate gap region.

In a preferred embodiment, in the step of providing the wafer, the wafer further includes a sealing ring located on the first surface of the substrate, the sealing ring forming a ring-shaped structure along an edge of the isolation groove of the wafer and a cut edge when cut to form the wafer.

In a preferred embodiment, the seal ring comprises: an active region extending into the substrate from a first surface of the substrate; a contact hole layer over the first active region; a metal layer located over the contact hole layer, the metal layer connected to the active region through the contact hole layer.

In a preferred embodiment, the substrate has the same impurity type as the active region.

In a preferred embodiment, the seal ring comprises: a well region extending into the substrate from a first surface of the substrate; an active region extending into the well region from a first surface of the well region; a contact hole layer over the first active region; a metal layer located over the contact hole layer, the metal layer connected to the active region through the contact hole layer.

In a preferred embodiment, the substrate has an impurity type opposite to that of the well region; the impurity type of the well region is the same as that of the active region.

In a preferred embodiment, before the step of providing the wafer, the method further comprises: providing a wafer; grinding the back of the wafer to thin the wafer; and cutting the thinned wafer to obtain independent chips.

In a preferred embodiment, the isolation trenches are formed by laser cutting the substrate gap regions.

Compared with the prior art, the first circuit (such as a noise circuit) and the second circuit (such as a sensitive circuit) are positioned on the same substrate, and the substrate part positioned between the first circuit and the second circuit is cut by laser to form the isolation groove, so that the circuit isolation performance is enhanced.

[ description of the drawings ]

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise. Wherein:

FIG. 1 is a schematic diagram of a prior art circuit in which two circuits, Part _ A and Part _ B, are integrated on the same chip;

FIG. 2 is a schematic top view of a chip with an isolation structure according to a first embodiment of the present invention;

FIG. 3 is a schematic top view of a chip with an isolation structure according to a second embodiment of the present invention;

FIG. 4 is a cross-sectional view of the isolation trench in one embodiment of the present invention based on the implementation of FIG. 3;

FIG. 5 is a schematic top view of a chip with an isolation structure according to a third embodiment of the present invention;

FIG. 6 is a schematic top view of a chip with an isolation structure according to a fourth embodiment of the present invention;

FIG. 7 is a schematic cross-sectional view of the closed loop of FIGS. 5 and 6 in a first embodiment;

FIG. 8 is a schematic cross-sectional view of the closed loop of FIGS. 5 and 6 in a second embodiment;

FIG. 9 is a schematic cross-sectional view of the closed loop of FIGS. 5 and 6 in a third embodiment;

FIG. 10 is a schematic top view of a chip with isolation structures according to a fifth embodiment of the present invention;

fig. 11 is a flow chart illustrating a method for manufacturing a chip with an isolation structure according to an embodiment of the invention.

[ detailed description ] embodiments

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.

Reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic may be included in at least one implementation of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Unless otherwise specified, the terms connected, and connected as used herein mean electrically connected, directly or indirectly.

Based on the noise interference problem of Part _ a to Part _ B in fig. 1, the inventors have conducted a great deal of research and analysis to find that the main interference mechanism is: the noise circuit Part _ a injects current noise into the substrate, and substrate fluctuation causes the sensitive circuit Part _ B to be affected. For the same wafer, the noise circuit Part _ A and the sensitive circuit Part _ B are positioned on the same substrate, and the substrate has conductivity. Therefore, the inventor provides a new technical scheme: the first circuit (such as a noise circuit) and the second circuit (such as a sensitive circuit) are positioned on the same substrate, and the substrate part positioned between the first circuit and the second circuit is cut by laser to form an isolation groove, so that the circuit isolation performance is enhanced.

Fig. 2 is a schematic top view of a chip with an isolation structure according to a first embodiment of the present invention. The chip with isolation structure shown in fig. 2 includes a chip 200, and the chip 200 is a separate chip obtained by cutting after the wafer is manufactured. The wafer 200 includes: a substrate (not identified), a first circuit Part _ a, a second circuit Part _ B, an isolation trench 210, and a metal connection layer 220.

Wherein the first circuit Part _ A is formed on the substrate; a second circuit Part _ B formed on the substrate and adjacent to the first circuit Part _ a; the isolation trench 210 is located in a portion of the substrate between the first circuit Part _ a and the second circuit Part _ B, where the portion of the substrate between the first circuit Part _ a and the second circuit Part _ B is referred to as a substrate gap region 230; the metal connection layer 220 is located on the first surface of the substrate and crosses the substrate gap region 230, and the metal connection layer 220 is used for electrically connecting the first circuit Part _ a and the second circuit Part _ B.

In the embodiment shown in fig. 2, the isolation trench 210 penetrates from the first surface of the substrate to the second surface of the substrate, and the isolation trench 210 penetrates through a portion of the substrate gap region 230, so that only a right narrow region (which may be referred to as "another portion of the substrate gap region 230 not penetrated by the isolation trench") is reserved (or supported) for the metal connection layer 220 between the first circuit Part _ a and the second circuit Part _ B, so that the narrow region on the right side of the substrate gap region 230 is also referred to as a connection region. The metal connection layer 220 spans the line region (i.e., another portion of the substrate gap region not penetrated by the isolation trench).

Three thick solid lines in fig. 2 are metal connection lines in the metal connection layer 220, and the metal connection layer 220 realizes the electrical connection between the first circuit Part _ a and the second circuit Part _ B through the three metal connection lines. In fig. 2, "the first circuit Part _ a and the second circuit Part _ B are partially separated by the isolation trench 210, and only a narrow region on the right side" is reserved, so that the parasitic substrate resistance can be greatly increased, and the mutual influence between the first circuit Part _ a and the second circuit Part _ B can be reduced.

From the principle of equivalent parasitic resistance:

resistance value

Wherein R is a resistance value, ρ is a resistivity, L is a resistance length, and A is a sectional area. The implementation in fig. 2 corresponds to a reduced cross-sectional area of the substrate parasitic resistance.

In a preferred embodiment, the isolation trench 210 is formed by laser cutting a portion of the substrate between the first circuit Part _ a and the second circuit Part _ B.

It should be noted that, in the implementation manner shown in fig. 2, the remaining connection line region (i.e., another portion of the substrate gap region 230 that is not penetrated by the isolation trench) after cutting may also be located at the left side of the substrate gap region 230, or may be located in the middle of the substrate gap region 230, and the smaller the width of the remaining connection line region is, the better the effect of isolating noise is.

Fig. 3 is a schematic top view of a chip with an isolation structure according to a second embodiment of the present invention. The main differences between fig. 3 and fig. 2 are: the isolation trench 310 in fig. 3 penetrates from the first surface of the substrate to the second surface of the substrate, and the isolation trench 310 penetrates through the entire substrate gap region 330, and the metal connection layer 320 spans the entire substrate gap region 330. That is, in the embodiment shown in fig. 3, the substrate gap region 330 is completely cut to generate the isolation trench 310, the isolation trench 310 completely separates the first circuit Part _ a and the second circuit Part _ B, and an insulating layer (not identified) and a metal connection layer 320 of the top layer of the wafer 300 are remained.

The substrate is typically a P-type silicon substrate, and some semiconductor processes also use an N-type silicon substrate, or other semiconductor materials (such as silicon germanium, gallium arsenide, silicon carbide, etc.) of P-type or N-type. As shown in fig. 3, the semiconductor substrate material having conductivity is completely cut off, so that a complete electrical isolation effect can be achieved, and there is no problem of noise interference between the first circuit Part _ a and the second circuit Part _ B.

Please refer to fig. 4, which is a cross-sectional view of an embodiment of the present invention located near an isolation trench according to the implementation of fig. 3. The left side is Part _ A, the right side is Part _ B, and an isolation groove 310 left after cutting exists in the middle position below the left side and the right side; p-sub is a P-type substrate area, and circuit structures are formed on the left Part _ A and the right Part _ B respectively. In the embodiment shown in fig. 4, the circuits on both sides are NMOS transistors, which are composed of source, drain, and gate structures, and the N + region is generally a source or drain region, and generally for a common NMOS transistor, the source and drain regions are physically identical, but the source and drain are defined according to the carrier flow direction. The grid fill area in fig. 4 is a gate. The lower part of the grid is a grid oxide layer. The solid line filled region in fig. 4 is a metal connection line in the metal connection layer 340, and may connect Part _ a and Part _ B, and the metal connection line is connected to the source or drain of the NMOS through the contact hole 340 (as shown in the horizontal line filled pattern in fig. 4).

For the implementation of fig. 2, the dicing may result in the side of the chip being exposed to moisture, resulting in moisture attack that affects chip performance, and one improvement is to pre-design a closed loop on the wafer, as shown by the dotted line in fig. 5. Fig. 5 is a schematic top view of a chip with an isolation structure according to a third embodiment of the present invention. The difference between the wafer shown in fig. 2 and the wafer shown in fig. 5 is that the wafer is pre-designed with a sealing ring 550 before dicing, the sealing ring 550 is located on the first surface of the substrate, and the sealing ring 550 forms a ring-shaped structure along the edge of the isolation trench 510 of the wafer 500 and the dicing edge when the wafer is diced to form the wafer.

For the implementation of fig. 3, the dicing may result in the side of the chip being exposed to moisture, resulting in the chip performance being affected by moisture attack, and one improvement is to pre-design a closed loop on the wafer, as shown by the dotted line in fig. 6. Fig. 6 is a schematic top view of a chip with an isolation structure according to a fourth embodiment of the present invention. The difference between the wafer shown in fig. 3 and the wafer shown in fig. 6 is that the wafer is pre-designed with a sealing ring 650 before dicing, the sealing ring 650 is located on the first surface of the substrate, and the sealing ring 650 forms a ring structure along the edge of the isolation trench 610 of the wafer 600 and the dicing edge when the wafer is diced to form the wafer.

Fig. 7 is a schematic cross-sectional view of the closed ring shown in fig. 5 and 6 in a first embodiment. The seal ring includes: a P + active region extending into the P-Sub substrate from a first surface of the P-Sub substrate; a contact hole layer 710 over the P + active region; a metal layer 720 located above the contact hole layer 710, the metal layer 720 being connected to the P + active regions through the contact hole layer 710.

Please refer to fig. 8, which is a schematic cross-sectional view of the closed ring shown in fig. 5 and 6 in a second embodiment. The seal ring includes: an N + active region extending into the N-Sub substrate from a first surface of the N-Sub substrate; a contact hole layer 810 located over the N + active region; a metal layer 820 located above the contact hole layer 810, the metal layer 820 being connected to the N + active regions through the contact hole layer 810.

It should be noted that, in the embodiments shown in fig. 7 and 8, the impurity type of the substrate is the same as that of the active region.

Please refer to fig. 9, which is a schematic cross-sectional view of the closed ring shown in fig. 5 and 6 in a third embodiment. The seal ring includes: an N-type well region (NWell) extending from a first surface of a P-Sub substrate into the P-Sub substrate; an N + active region extending into the N-type well region from a first surface of the N-type well region; a contact hole layer 910 over the N + active region; a metal layer 920 located above the contact hole layer 910, the metal layer 920 being connected to the N + active region through the contact hole layer 910. In another embodiment, the P-Sub substrate in fig. 9 may be changed to an N-Sub substrate, the N-well region may be changed to a P-well region (PWell), and the N + active region may be changed to a P + active region, thereby forming another seal ring structure. That is, in the seal ring structure shown in fig. 9, the impurity type of the substrate is opposite to that of the well region; the impurity type of the well region is the same as that of the active region.

Isolation of 3 or more different circuit portions on the same substrate may also be achieved in accordance with the foregoing principles of the invention. Fig. 10 is a schematic top view of a chip with an isolation structure according to a fifth embodiment of the present invention. In the embodiment shown in fig. 10, the circuits Part _ A, Part _ B, Part _ C and Part _ D4 are both located on the first surface of the same substrate, and the four circuits are distributed adjacently on the first surface of the substrate. Wherein the substrate portion between each adjacent two circuits (i.e., the substrate gap region) is completely cut to form the isolation trench 110, and the metal connection layer 120 spans the substrate portion between the adjacent two circuits.

The following describes a method for manufacturing a chip having an isolation structure according to the present invention.

Fig. 11 is a schematic flow chart illustrating a method for manufacturing a chip with an isolation structure according to an embodiment of the invention. A method for manufacturing the chip having the isolation structure shown in fig. 11 is described below based on fig. 2 and 3.

Step 1110, providing a wafer (200, 300), the wafer (200, 300) comprising: a substrate (not shown); a first circuit Part _ A formed on the substrate; a second circuit Part _ B formed on the substrate adjacent to the first circuit Part _ a, located at the first surface of the substrate and adjacent to the first circuit Part _ a; a metal connection layer (220, 320) on the first surface of the substrate and crossing the substrate gap region (230, 330), the metal connection layer (220, 320) being used to electrically connect the first circuit Part _ a and the second circuit Part _ B, the substrate gap region (230, 330) being a portion of the substrate between the first circuit Part _ a and the second circuit Part _ B.

In step 1120, the substrate gap region (230, 330) is cut to form an isolation trench (210, 310) in the substrate gap region (230, 330). In one embodiment, the substrate gap region (230, 330) may be cut by a laser.

In the particular embodiment shown in fig. 2, only a portion of the substrate gap region 230 is cut when cutting the substrate gap region 230. The isolation trench 210 penetrates from the first surface of the substrate to the second surface of the substrate, the isolation trench 210 penetrates through a portion of the substrate gap region 230, and the metal connection layer 220 crosses another portion of the substrate gap region 230 that is not penetrated by the isolation trench 210.

In the particular embodiment shown in fig. 3, when the substrate gap region 330 is cut, the entire substrate gap region 330 is cut. The isolation trench 310 penetrates from the first surface of the substrate to the second surface of the substrate, and the isolation trench 310 penetrates through the entire substrate gap region 330, and the metal connection layer 320 spans the entire substrate gap region 330. That is, in the embodiment shown in fig. 3, the substrate gap region 330 is completely cut to generate the isolation trench 310, the isolation trench 310 completely separates the first circuit Part _ a and the second circuit Part _ B, and an insulating layer (not identified) and a metal connection layer 320 of the top layer of the wafer 300 are remained.

For the implementations of fig. 2 and 3, the dicing may result in the side of the chip being exposed to moisture, resulting in moisture attack that affects chip performance, and one improvement is to pre-design a closed ring on the wafer, as shown by the dotted lines in fig. 5 and 6. That is, in the provide wafer step 1110, the wafer further includes the seal ring (550, 650), the seal ring (550, 650) is located on the first surface of the substrate, and the seal ring (550, 650) forms a ring-shaped structure along the edge of the isolation trench (510, 610) of the wafer and the cut edge when cut to form the wafer. The specific structure of the seal ring (550, 650) can be found in the description of the seal ring shown in fig. 7-9.

For the convenience of laser dicing, the wafer thickness may be reduced before dicing the die, usually by grinding the back side of the wafer. Correspondingly, in one embodiment, the method for manufacturing the chip with the isolation structure before the step 1110 of providing the wafer further includes: providing a wafer; grinding the back of the wafer to thin the wafer; and cutting the thinned wafer to obtain independent chips.

It should be noted that, in the present invention, the substrate portion located between the first circuit and the second circuit is laser cut to form the isolation trench, which can not only isolate noise, but also achieve a thermal insulation effect. Because some circuits that generate heat severely may have adverse effects on other circuits that are sensitive to heat, the present invention may reduce heat conduction and thus provide thermal insulation.

In the present invention, the terms "connected", "connecting", and the like mean electrical connections, and direct or indirect electrical connections unless otherwise specified.

It should be noted that those skilled in the art can make modifications to the embodiments of the present invention without departing from the scope of the appended claims. Accordingly, the scope of the appended claims is not to be limited to the specific embodiments described above.

Claims

1. A method for manufacturing a chip with an isolation structure is characterized by comprising the following steps:

providing a wafer comprising: a substrate; a first circuit formed on the substrate; a second circuit formed on the substrate adjacent to the first circuit; a metal connection layer at the first surface of the substrate and spanning a substrate gap region for electrically connecting the first circuit and the second circuit, the substrate gap region being a portion of the substrate between the first circuit and the second circuit,

laser cutting the substrate gap region to leave an isolation trench completely separating the first circuit from the second circuit, the width of the isolation trench being the spacing between the first circuit and the second circuit,

wherein, when the substrate is cut, the whole substrate gap region is cut,

the isolation trench penetrates from the first surface of the substrate to the second surface of the substrate, the isolation trench penetrates through the whole substrate gap region, and the metal connecting layer crosses the isolation trench.

2. The method of manufacturing a chip with an isolation structure according to claim 1,

the metal connection layer spans the entire substrate gap region.

3. The method of manufacturing a chip with an isolation structure according to claim 1,

in the step of providing the wafer, the wafer further includes a sealing ring located on the first surface of the substrate, the sealing ring forming a ring-shaped structure along an edge of the isolation trench of the wafer and a cut edge when cut to form the wafer.

4. The method for manufacturing a chip with an isolation structure according to claim 3,

the seal ring includes:

an active region extending into the substrate from a first surface of the substrate;

a contact hole layer over the active region;

a metal layer located over the contact hole layer, the metal layer connected to the active region through the contact hole layer.

5. The method for manufacturing a chip with an isolation structure according to claim 4,

the impurity type of the substrate is the same as that of the active region.

6. The method for manufacturing a chip with an isolation structure according to claim 3,

the seal ring includes:

a well region extending into the substrate from a first surface of the substrate;

an active region extending into the well region from a first surface of the well region;

a contact hole layer over the active region;

7. The method for manufacturing a chip with an isolation structure according to claim 6,

the impurity type of the substrate is opposite to that of the well region;

the impurity type of the well region is the same as that of the active region.

8. The method for manufacturing a chip with an isolation structure according to claim 1, further comprising, before the step of providing a wafer:

providing a wafer;

grinding the back of the wafer to thin the wafer;

and cutting the thinned wafer to obtain independent chips.